CN104517921A - Bonded substrate and forming method thereof, and three-dimensional package structure and forming method thereof - Google Patents
Bonded substrate and forming method thereof, and three-dimensional package structure and forming method thereof Download PDFInfo
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- CN104517921A CN104517921A CN201310463714.1A CN201310463714A CN104517921A CN 104517921 A CN104517921 A CN 104517921A CN 201310463714 A CN201310463714 A CN 201310463714A CN 104517921 A CN104517921 A CN 104517921A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13017—Shape in side view being non uniform along the bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16111—Disposition the bump connector being disposed in a recess of the surface
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Abstract
Disclosed are a bonded substrate and a forming method thereof, and a three-dimensional package structure and a forming method thereof. The bonded substrate comprises a wafer, an insulating layer, and a plurality of pads; the insulating layer and the pads are arranged on the wafer; every two pads is isolated by the insulating layer; each pad comprises a pad bottom and a pad protrusion arranged above the pad bottom, the upper surface of the pad bottom is lower than or flush with the upper surface of the insulating layer, the upper surface of the pad protrusion is higher than the upper surface of the insulating layer, and a projection of the pad protrusion on the surface of the wafer is located in a projection of the pad bottom on the surface of the wafer. The problem that the existing method of forming the three-dimensional packaging structure by metal-metal bonding easily causes short circuit of the adjacent pads is solved.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, particularly relate to a kind of to be applied at the bottom of the bonding radical of three-dimension packaging and forming method thereof, and a kind of three-dimension packaging structure and forming method thereof.
Background technology
Along with the requirement of microelectronic component high integration, multifunction, existing two-dimentional encapsulation technology is difficult to meet encapsulation requirement, and three-dimension packaging have size little, lightweight, reduce the advantage such as signal delay, just becoming the mainstream technology of microelectronic device package.Bonding is the critical process realizing three-dimension packaging, the bonding method being applied to three-dimension packaging has multiple, comprising: metal-metal bonding, oxide Direct Bonding, anode linkage, bonding bonding, bonding, ultrasonic bonding, glass medium bonding etc. based on solder.
A kind of existing method utilizing metal-metal bonding method to form three-dimension packaging structure comprises:
As shown in Figure 1, to provide at the bottom of two bonding radicals 1, at the bottom of bonding radical, 1 comprises: wafer 11; Be positioned at the insulating barrier 12 on wafer 11 and multiple pad 13, separated between adjacent two pads 13 by insulating barrier 12, the upper surface of pad 13 is plane, and this plane is higher than the upper surface of insulating barrier 12.
As shown in Figure 2, to make at the bottom of two bonding radicals that the pad 13 on 1 is aimed at, line unit of going forward side by side closes.
In bonding process, under pressure, the pad 13 with certain ductility can deform, and makes to protrude from the part outside insulating barrier 12 upper surface in pad 13, extends to being positioned at the bottom of same bonding radical adjacent pad 13 on 1.And along with the raising of microelectronic component integrated level, the density of pad 13 is increasing, distance at the bottom of bonding radical on 1 between adjacent two pads 13 is more and more less, easily to cause at the bottom of same bonding radical on 1 and couples together between adjacent two pads 13, and then cause the short circuit of adjacent two pads 13.When two suprabasil pad sizes of bonding of wish bonding are unequal, the easier short circuit of pad that larger-size pad is less than size.
Summary of the invention
The problem to be solved in the present invention is: the existing method utilizing metal-metal bonding method to form three-dimension packaging structure easily causes adjacent two pad short circuits.
For solving the problem, the invention provides a kind of being applied at the bottom of the bonding radical of three-dimension packaging, comprising:
Wafer;
Be positioned at the insulating barrier on described wafer and multiple pad, adjacent two described pads are separated by insulating barrier, described pad comprises: bottom pad and to be positioned at bottom described pad the pad protuberance of top, upper surface bottom described pad lower than or the upper surface that flushes in insulating barrier, the upper surface of described pad protuberance is higher than the upper surface of insulating barrier, the projection on the wafer surface of described pad protuberance, is positioned at projection on the wafer surface bottom described pad.
Optionally, all there is interval between sidewall bottom all sidewalls of described pad protuberance and corresponding pad.
Optionally, described pad protuberance width accounts for 50% to 90% of pad bottom width.
Optionally, the partial sidewall of described pad protuberance is alignd with sidewall bottom corresponding pad.
Optionally, the width of described pad protuberance accounts for 50% to 95% of the width bottom pad.
Optionally, the material of described pad is copper.
Optionally, the section difference between described pad peak and insulating barrier upper surface is 0 to 10000 dust.
In addition, present invention also offers the formation method at the bottom of above-mentioned arbitrary bonding radical, comprising:
Wafer is provided;
Described wafer is formed the insulating barrier with multiple opening;
Formed and cover described insulating barrier and the bonding pad material layer of filling described opening;
Carry out planarization to described bonding pad material layer, to remove the bonding pad material layer on described insulating barrier, the upper surface of the remaining bonding pad material layer be filled in described opening is higher than the upper surface of insulating barrier;
Mask layer is formed above the described remaining bonding pad material layer be filled in opening;
With described mask layer for mask etches, to remove certain thickness bonding pad material layer, formed bottom described pad and pad protuberance;
Remove described mask layer.
In addition, present invention also offers a kind of three-dimension packaging structure, comprising:
At the bottom of first bonding radical, be at the bottom of above-mentioned arbitrary described bonding radical at the bottom of described first bonding radical;
At the bottom of second bonding radical, comprise at the bottom of described second bonding radical: the second wafer; Be positioned at the second insulating barrier on described second wafer and multiple second pad, the peak of described second pad is higher than the upper surface of the second insulating barrier;
Pad at the bottom of described first bonding radical and the second pad are fixed together by bonding method.
Optionally, be at the bottom of above-mentioned arbitrary described bonding radical at the bottom of described second bonding radical.
Optionally, described second pad, higher than the projection size of part on the second crystal column surface of the second insulating barrier, equals the projection size of part on the second crystal column surface that described second pad is positioned at the second insulating barrier.
In addition, present invention also offers the formation method of above-mentioned three-dimension packaging structure, comprising:
Said method is utilized to be formed at the bottom of the first bonding radical;
Formed at the bottom of described second bonding radical;
Pad alignment second pad at the bottom of described first bonding radical, line unit of going forward side by side are closed.
Optionally, described bonding is low-temperature thermocompression bonding.
Optionally, said method is utilized to form described second bonding radical.
Compared with prior art, technical scheme of the present invention has the following advantages:
Pad at the bottom of bonding radical comprises: bottom pad and to be positioned at bottom pad the pad protuberance of top, wherein, upper surface bottom pad lower than or the upper surface that flushes in insulating barrier, the upper surface of pad protuberance is higher than the upper surface of insulating barrier, the projection on the wafer surface of pad protuberance, be positioned at projection on the wafer surface bottom pad, make the interval between adjacent two pad protuberances protruding from insulating barrier upper surface, the interval between being greater than bottom adjacent two pads.Under the condition that interval in interval between keeping bottom measure-alike, adjacent two pads of pad in pad bottom size and prior art in the present invention and prior art between adjacent two pads is identical, be equivalent to increase the interval between the part protruding from insulating barrier upper surface in adjacent two pads, thus, in bonding process, reduce the possibility that adjacent two pads connect, and then reduce the possibility of adjacent two pad short circuits.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view at the bottom of existing bonding radical;
Fig. 2 is the generalized section be fixed together by bonding at the bottom of bonding radical shown in two Fig. 1;
Fig. 3 to Fig. 6 is the cross-sectional view in each production phase at the bottom of the first bonding radical in the first embodiment of the present invention;
Fig. 7 is the cross-sectional view in the first embodiment of the present invention at the bottom of the second bonding radical;
Fig. 8 is the generalized section be fixed together with bonding at the bottom of the second bonding radical at the bottom of the first bonding radical in the first embodiment of the present invention;
Fig. 9 is the cross-sectional view in the second embodiment of the present invention at the bottom of the second bonding radical;
Figure 10 is the generalized section be fixed together with bonding at the bottom of the second bonding radical at the bottom of the first bonding radical in the second embodiment of the present invention;
Figure 11 is the cross-sectional view in the third embodiment of the present invention at the bottom of the first bonding radical;
Figure 12 is the cross-sectional view in the fourth embodiment of the present invention at the bottom of the second bonding radical.
Embodiment
In order to solve the existing method utilizing metal-metal bonding method to form three-dimension packaging structure, easily cause the problem of adjacent two pad short circuits, the invention provides a kind of three-dimension packaging Structure formation method of improvement, in at the bottom of two bonding radicals of the method, define at the bottom of one of them bonding radical be at the bottom of the first bonding radical, another is at the bottom of the second bonding radical.
In order to reduce the possibility of adjacent two pad short circuits at the bottom of the first bonding radical, pad at the bottom of first bonding radical comprises: bottom pad and to be positioned at bottom pad the pad protuberance of top, wherein, upper surface bottom pad lower than or the upper surface that flushes in insulating barrier, the upper surface of pad protuberance is higher than the upper surface of insulating barrier, the projection on the wafer surface of pad protuberance, be positioned at projection on the wafer surface bottom pad, make the interval between adjacent two pad protuberances protruding insulating barrier upper surfaces, the interval between being greater than bottom adjacent two pads.
To keep in the present invention the measure-alike of pad in pad bottom size and prior art, under the condition that interval in interval between bottom adjacent two pads and prior art between adjacent two pads is identical, be equivalent to increase in adjacent two pads, protrude from interval between the part of insulating barrier upper surface, thus, in bonding process, reduce the possibility that adjacent two pads connect, and then reduce the possibility of adjacent two pad short circuits at the bottom of the first bonding radical.
Similarly, in order to reduce the possibility of adjacent two pad short circuits at the bottom of the second bonding radical, the pad at the bottom of the second bonding radical also can be made to adopt the structure of pad at the bottom of the first bonding radical.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
First embodiment
First, the method utilizing metal-metal bonding method to form three-dimension packaging structure of the present embodiment is described.
As shown in Figure 6,100 are provided at the bottom of the first bonding radical at the bottom of the 100, first bonding radical to comprise: wafer 110; Be positioned at the insulating barrier 120 on wafer 110 and multiple pad 130, adjacent two pads 130 are separated by insulating barrier 120, pad 130 comprises: bottom pad 131 and the pad protuberance 132 that to be positioned at bottom pad above in the of 131, bottom pad, the upper surface S1 of 131 is lower than the upper surface S3 of insulating barrier 120, the upper surface S2 of pad protuberance 132 is higher than the upper surface S3 of insulating barrier 120, the upper surface making whole pad 130 is rugged, the projection of pad protuberance 132 on wafer 110 surface, to be positioned at bottom pad 131 projections on wafer 110 surface.In other words, the size that the size of pad protuberance 132 is less than bottom pad 131, and the sidewall of pad protuberance 132 does not protrude outside the sidewall of bottom pad 131.And all there is interval between 131 sidewalls bottom all sidewalls of pad protuberance 132 and corresponding pad, in other words, all sidewalls of pad protuberance 132 are unjustified with 131 sidewalls bottom corresponding pad.
Wafer 110 is formed with circuit structure (not shown), and pad 130 is electrically connected with the circuit structure of wafer 110, to be electrically connected with external circuit by described circuit structure.
In the present embodiment, the material of pad 130 is copper.
In order to make in follow-up bonding technology, pad 130 and the second pad at the bottom of the second bonding radical can be bonded together securely, and need make has enough sections poor between the peak of pad 130 (i.e. the upper surface S2 of pad protuberance 132) and the upper surface S3 of insulating barrier 120.In the present embodiment, the section difference between the peak (i.e. the upper surface S2 of pad protuberance 132) of pad 130 and the upper surface S3 of insulating barrier 120 is 0 to 10000 dust (not comprising left end point).
In order to make in follow-up bonding technology, pad 130 and the second pad at the bottom of the second bonding radical can be bonded together securely, and have enough intervals between adjacent two pad protuberances 132 on 100 at the bottom of the first bonding radical, couple together to prevent adjacent two pads 130, in the present embodiment, the width W of pad protuberance 132
1, account for the width W of bottom pad 131
250% to 90%.Described width dimensions refers to along the size in pad 130 orientation.
In the present embodiment, at the bottom of first bonding radical, the formation method of 100 comprises: as shown in Figure 3, wafer 110 is provided, wafer 110 is formed the insulating barrier 120 with multiple opening (mark), in a particular embodiment, the formation method of insulating barrier 120 comprises: on wafer 110, form insulation material layer, forms graphical photoresist layer over which layer of insulating material, the position of described graphical photoresist layer definition opening; With described graphical photoresist layer for mask etches described insulation material layer, to form the insulating barrier 120 with opening;
Continue with reference to shown in Fig. 3, formed and cover insulating barrier 120 and the bonding pad material layer of filling described opening; Planarization is carried out to described bonding pad material layer, to remove the bonding pad material layer covered on insulating barrier 120, the upper surface of the remaining bonding pad material layer 130a be filled in described opening, higher than the upper surface S3 of insulating barrier 120, described planarization can be cmp process;
As shown in Figure 4, mask layer 140 is formed above the described remaining bonding pad material layer 130a be filled in opening, interval is there is between all sidewalls of mask layer 140 and sidewall corresponding to bonding pad material layer 130a, the formation method of mask layer 140 comprises: form the mask layer covering insulating barrier 120 and bonding pad material layer 130a, described mask layer can be photoresist layer, photoetching is carried out to this mask layer, to remove the mask layer covered on insulating barrier 120 and part bonding pad material layer 130a, mask plate that photoetching process adopts in this step, can be same mask plate with formation mask plate that above-mentioned graphical photoresist layer adopts,
As shown in Figure 5, with mask layer 140 for mask etches, to remove certain thickness bonding pad material layer 130a(as shown in Figure 4), to form bottom pad 131 and pad protuberance 132, in the present embodiment, described lithographic method can be wet etching, adopt etching agent to be FeCl
3, acetic acid, formic acid etc.;
As shown in Figure 6, mask layer 140(is removed as shown in Figure 5).
In a particular embodiment, before the described bonding pad material layer of formation, can be formed cover insulating barrier 120 and described opening bottom and sidewall on barrier layer (barrier layer, not shown), then form metal seed layer (not shown) over the barrier layer.Described barrier layer is the lamination of TaN layer, Ta layer or TaN layer and Ta layer, and the material of described metal seed layer is Cu.The effect on described barrier layer is: prevent the diffusion of bonding pad material layer in insulating barrier 120, increases the bonding force between bonding pad material layer and insulating barrier 120 simultaneously.
In a particular embodiment, the formation method of described bonding pad material layer is plating.
In a particular embodiment, the material of insulating barrier 120 is silica.
In a particular embodiment, as shown in Figure 3, after utilizing chemical mechanical milling tech formation bonding pad material layer 130a, in order to make the upper surface of bonding pad material layer 130a, and there are enough sections poor between the upper surface S3 of insulating barrier 120, after described cmp process, can etch insulating barrier 120, with the thickness of thinning insulating barrier 120.
As shown in Figure 7,200 are provided at the bottom of the second bonding radical at the bottom of the 200, second bonding radical to comprise: the second wafer 210, be positioned at the second insulating barrier 220 on the second wafer 210, and multiple second pad 230, adjacent two the second pads 230 are separated by the second insulating barrier 220, the upper surface S4 of the second pad 230 is the plane of the upper surface S5 higher than the second insulating barrier 220, make the second pad 230 higher than the projection size of part on the second wafer 210 surface of the second insulating barrier 220, equal the projection size of part on the second wafer 210 surface that the second pad 230 is positioned at the second insulating barrier 220, the projection size of the second pad 230 on the second wafer 210 surface, be less than the projection size of pad 130 on wafer 110 surface (shown in composition graphs 8).
In the present embodiment, the material of the second pad 230 is copper.
In order to make in follow-up bonding technology, the second pad 230 and pad 130 can be bonded together securely, and need make has enough sections poor between the peak of the second pad 230 (i.e. the upper surface S4 of the second pad 230) and the upper surface S5 of the second insulating barrier 220.In the present embodiment, the section difference between the upper surface S4 of the second pad 230 and upper surface S5 of the second insulating barrier 220 is 0 to 10000 dust (not comprising left end point).
In the present embodiment, at the bottom of the second bonding radical, the formation method of 200 comprises: provide the second wafer 210, and the second wafer 210 is formed second insulating barrier 220 with multiple second opening (mark); Form covering second insulating barrier 220 and fill the second bonding pad material layer of described second opening; Carry out planarization to described second bonding pad material layer, to remove the second bonding pad material layer covered on the second insulating barrier 220, remaining the second bonding pad material layer be filled in described second opening forms the second pad 230.
In a particular embodiment, before the described second bonding pad material layer of formation, the barrier layer (barrier layer, not shown) on the bottom of covering second insulating barrier 220 and described second opening and sidewall can be formed, then form metal seed layer (not shown) over the barrier layer.Described barrier layer is the lamination of TaN layer, Ta layer or TaN layer and Ta layer, and the material of described metal seed layer is Cu.The effect on described barrier layer is: prevent the diffusion of the second bonding pad material layer in the second insulating barrier 220, increase the bonding force between the second bonding pad material layer and the second insulating barrier 220 simultaneously.
In a particular embodiment, the formation method of described second bonding pad material layer is plating.
In a particular embodiment, the material of the second insulating barrier 220 is silica.
As shown in Figure 8, before bonding, to 100 and second 200 cleaning at the bottom of bonding radical at the bottom of the first bonding radical, to remove the oxide of pad 130 and the second pad 230 surface, pad 130 and the second pad 230 are fixed together more securely.
In the present embodiment, cleaning agent that described cleaning step adopts is acetic acid or citric acid.
Continue, with reference to shown in Fig. 8, to make pad 130 aim at the second pad 230, line unit of going forward side by side closes.
In the present embodiment, described bonding is low-temperature thermocompression bonding.In bonding process, under uniform temperature and pressure effect, phase counterdiffusion between the interface atoms of pad 130 and the second pad 230 and realize bonding, to make at the bottom of the first bonding radical 100 and second 200 to be fixed together at the bottom of bonding radical.Particularly, be the upper surface S2 of pad protuberance 132 in pad 130, be fixed together with the upper surface S4 of the second pad 230.
In a particular embodiment, the technological parameter of described low-temperature thermocompression bonding comprises: bonding temperature is 300 to 400 DEG C, and bonding time is 30 to 90min, and bonding pressure is 30 to 60KN.
Due at the bottom of the first bonding radical 100 the projection size of pad 130 on wafer 110 surface, be greater than the projection size of the second pad 230 on the second wafer 210 surface, therefore the possibility of adjacent two pads 130 short circuit, be greater than the possibility of adjacent two the second pad 230 short circuits.
Due to the projection of pad protuberance 132 in pad 130 on wafer 110 surface, to be positioned at bottom pad 131 projections on wafer 110 surface, make the interval between adjacent two pad protuberances 132 protruding from insulating barrier 120 upper surface S3, be greater than the interval between 131 bottom adjacent two pads.To keep bottom pad the measure-alike of pad in 131 sizes and prior art, under the condition that interval in interval bottom adjacent two pads between 131 and prior art between adjacent two pads is identical, be equivalent to increase in adjacent two pads 130, protrude from interval between the part (i.e. pad protuberance 132) of insulating barrier 120 upper surface, thus, in bonding process, reduce the possibility that adjacent two pads 130 connect, and then reduce the possibility of adjacent two pads 130 short circuit.
In the present embodiment, after pad 130 and the second pad 230 bonding, carry out annealing in process, the effect of this annealing in process is: allow the diffusion inside (inter-diffusion) between pad 130, second pad 230 interface, provides enough energy to complete the growth of pad 130 and the second pad 230 junction crystal grain.In a particular embodiment, annealing temperature is 300 to 400 DEG C, and the time is 30 to 90min.
Then, the three-dimension packaging structure of the present embodiment is described.As shown in Figure 8, this three-dimension packaging structure comprises:
100 to comprise at the bottom of 100, first bonding radical at the bottom of first bonding radical: wafer 110; Be positioned at the insulating barrier 120 on wafer 110 and multiple pad 130, adjacent two pads 130 are separated by insulating barrier 120, pad 130 comprises: bottom pad 131 and the pad protuberance 132 that to be positioned at bottom pad above in the of 131, bottom pad, the upper surface S1 of 131 is lower than the upper surface S3 of insulating barrier 120, the upper surface S2 of pad protuberance 132 is higher than the upper surface S3 of insulating barrier 120, the projection of pad protuberance 132 on wafer 110 surface, to be positioned at bottom pad 131 projections on wafer 110 surface;
200 to comprise at the bottom of 200, second bonding radical at the bottom of second bonding radical: the second wafer 210; Be positioned at the second insulating barrier 220 on the second wafer 210 and multiple second pad 230, adjacent two the second pads 230 are separated by the second insulating barrier 220, second pad 230, higher than the projection size of part on the second wafer 210 surface of the second insulating barrier 220, equals the projection size of part on the second wafer 210 surface that the second pad 230 is positioned at the second insulating barrier 220;
At the bottom of first bonding radical 100 pad 130 and the second pad 230 be fixed together by bonding method.
Second embodiment
Difference between second embodiment and the first embodiment is: in a second embodiment, as shown in Figure 9, the second pad 230 at the bottom of second bonding radical in 200 comprises: bottom the second pad 231, and the second pad protuberance 232 be positioned at bottom the second pad above in the of 231, bottom second pad, the upper surface S6 of 231 is lower than the upper surface S5 of the second insulating barrier 220, the upper surface S7 of the second pad protuberance 232 is higher than the upper surface S5 of the second insulating barrier 220, the upper surface making the second pad 230 is rugged, the projection of the second pad protuberance 232 on the second wafer 210 surface, to be positioned at bottom the second pad 231 projections on the second wafer 210 surface.In other words, the size that the size of the second pad protuberance 232 is less than bottom the second pad 231, and the sidewall of the second pad protuberance 232 does not protrude outside the sidewall of bottom the second pad 231.In addition, in a second embodiment, as shown in Figure 10, the projection size of pad 130 on wafer 110 surface, equals the projection size of the second pad 230 on the second wafer 210 surface.As the alternative of the second embodiment, the projection size of pad 130 on wafer 110 surface, also can be less than or greater than the projection size of the second pad 230 on the second wafer 210 surface.
In order to make in bonding technology, second pad 230 and pad 130 can be bonded together securely, as shown in Figure 9, need make have enough sections poor between the peak of the second pad 230 (i.e. the upper surface S7 of the second pad protuberance 232) and the upper surface S5 of the second insulating barrier 220.In the present embodiment, the section difference between the peak (i.e. the upper surface S7 of the second pad protuberance 232) of the second pad 230 and the upper surface S5 of the second insulating barrier 220 is 0 to 10000 dust (not comprising left end point).
In order to make in bonding technology, second pad 230 and pad 130 can be bonded together securely, and have enough intervals between adjacent two the second pad protuberances 232, couple together to prevent adjacent two the second pads 230, in the present embodiment, as shown in Figure 9, the width W of the second pad protuberance 232
3, account for the width W of bottom the second pad 231
450% to 90%.Described width dimensions refers to along the size in the second pad 230 orientation.
In the technical scheme of the present embodiment, in bonding process, reduce the possibility of the possibility of adjacent two pads 130 connection, adjacent two the second pads 230 connections simultaneously, and then reduce the possibility of adjacent two pads 130 short circuit, the possibility of adjacent two the second pad 230 short circuits simultaneously.
After bonding, as shown in Figure 10, the upper surface S2 of the pad protuberance 132 of pad 130, is fixed together with the upper surface S7 of the second pad protuberance 232 of the second pad 230.
In the present embodiment, at the bottom of the second bonding radical, the formation method of 200 with reference to the formation method in the first embodiment at the bottom of the first bonding radical, can not repeat them here.
3rd embodiment
Difference between 3rd embodiment and the first embodiment or the second embodiment is: in the third embodiment, as shown in figure 11, at the bottom of the first bonding radical 100 pad 130 in, the partial sidewall of pad protuberance 132 is alignd with 131 sidewalls bottom corresponding pad.
In the present embodiment, the width W of pad protuberance 132
1, account for the width W of bottom pad 131
250% to 95%.
4th embodiment
Difference between 4th embodiment and the second embodiment is: in the third embodiment, as shown in figure 12, and the partial sidewall of the second pad protuberance 232 is alignd with 231 sidewalls bottom the second corresponding pad.
In the present embodiment, the width W of the second pad protuberance 232
3, account for the width W of bottom the second pad 231
450% to 95%.
In other embodiments, the pad upper base surface of the pad at the bottom of the first bonding radical, also can with the upper surface flush of insulating barrier; In second pad, the upper surface bottom the second pad also can with the upper surface flush of the second insulating barrier.
In the present invention, each embodiment adopts laddering literary style, and emphasis describes the difference with previous embodiment, and the same section in each embodiment can with reference to previous embodiment.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. one kind is applied at the bottom of the bonding radical of three-dimension packaging, it is characterized in that, comprising:
Wafer;
Be positioned at the insulating barrier on described wafer and multiple pad, adjacent two described pads are separated by insulating barrier, described pad comprises: bottom pad and to be positioned at bottom described pad the pad protuberance of top, upper surface bottom described pad lower than or the upper surface that flushes in insulating barrier, the upper surface of described pad protuberance is higher than the upper surface of insulating barrier, the projection on the wafer surface of described pad protuberance, is positioned at projection on the wafer surface bottom described pad.
2. at the bottom of bonding radical according to claim 1, it is characterized in that all there is interval between sidewall bottom all sidewalls of described pad protuberance and corresponding pad.
3. at the bottom of bonding radical according to claim 2, it is characterized in that, described pad protuberance width accounts for 50% to 90% of pad bottom width.
4. at the bottom of bonding radical according to claim 1, it is characterized in that, the partial sidewall of described pad protuberance is alignd with sidewall bottom corresponding pad.
5. at the bottom of bonding radical according to claim 4, it is characterized in that, the width of described pad protuberance accounts for 50% to 95% of the width bottom pad.
6. at the bottom of the bonding radical according to any one of claim 1 to 5, it is characterized in that, the material of described pad is copper.
7. at the bottom of bonding radical according to claim 6, it is characterized in that, the section difference between described pad peak and insulating barrier upper surface is 0 to 10000 dust.
8. the formation method described in any one of claim 1 to 7 at the bottom of bonding radical, is characterized in that, comprising:
Wafer is provided;
Described wafer is formed the insulating barrier with multiple opening;
Formed and cover described insulating barrier and the bonding pad material layer of filling described opening;
Carry out planarization to described bonding pad material layer, to remove the bonding pad material layer on described insulating barrier, the upper surface of the remaining bonding pad material layer be filled in described opening is higher than the upper surface of insulating barrier;
Mask layer is formed above the described remaining bonding pad material layer be filled in opening;
With described mask layer for mask etches, to remove certain thickness bonding pad material layer, formed bottom described pad and pad protuberance;
Remove described mask layer.
9. a three-dimension packaging structure, is characterized in that, comprising:
At the bottom of first bonding radical, at the bottom of the bonding radical described in any one of claim 1 to 7 at the bottom of described first bonding radical;
At the bottom of second bonding radical, comprise at the bottom of described second bonding radical: the second wafer; Be positioned at the second insulating barrier on described second wafer and multiple second pad, the peak of described second pad is higher than the upper surface of the second insulating barrier;
Pad at the bottom of described first bonding radical and the second pad are fixed together by bonding method.
10. three-dimension packaging structure according to claim 9, is characterized in that, at the bottom of the bonding radical described in any one of claim 1 to 7 at the bottom of described second bonding radical.
11. three-dimension packaging structures according to claim 9, it is characterized in that, described second pad, higher than the projection size of part on the second crystal column surface of the second insulating barrier, equals the projection size of part on the second crystal column surface that described second pad is positioned at the second insulating barrier.
The formation method of 12. 1 kinds of three-dimension packaging structures according to claim 9, is characterized in that, comprising:
The method described in claim 8 is utilized to be formed at the bottom of the first bonding radical;
Formed at the bottom of described second bonding radical;
Pad alignment second pad at the bottom of described first bonding radical, line unit of going forward side by side are closed.
13. formation methods according to claim 12, is characterized in that, described bonding is low-temperature thermocompression bonding.
14. formation methods according to claim 12, is characterized in that, utilize the method described in claim 8 to form described second bonding radical.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104966676A (en) * | 2015-07-08 | 2015-10-07 | 上海新微技术研发中心有限公司 | Eutectic bonding method |
| CN107546174A (en) * | 2017-07-28 | 2018-01-05 | 中国科学院微电子研究所 | A kind of process of ic component |
| CN116741648A (en) * | 2023-08-11 | 2023-09-12 | 四川遂宁市利普芯微电子有限公司 | Flip chip packaging method and flip chip packaging structure |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5399765A (en) * | 1977-02-10 | 1978-08-31 | Hitachi Ltd | Semiconductor device having bonding pad |
| JPH0828389B2 (en) * | 1990-11-21 | 1996-03-21 | 三菱電機株式会社 | Semiconductor device |
| US6420255B1 (en) * | 1999-01-18 | 2002-07-16 | Nec Corporation | Mounting substrate with a solder resist layer and method of forming the same |
| JP4115832B2 (en) * | 2002-12-27 | 2008-07-09 | 東芝松下ディスプレイテクノロジー株式会社 | Semiconductor device and liquid crystal display panel |
| CN102254876A (en) * | 2010-05-21 | 2011-11-23 | 松下电器产业株式会社 | Semiconductor apparatus and semiconductor apparatus unit |
| JP2012054428A (en) * | 2010-09-01 | 2012-03-15 | Renesas Electronics Corp | Semiconductor device and semiconductor device manufacturing method |
| CN103094232A (en) * | 2011-11-02 | 2013-05-08 | 南茂科技股份有限公司 | Chip packaging structure |
-
2013
- 2013-09-30 CN CN201310463714.1A patent/CN104517921B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5399765A (en) * | 1977-02-10 | 1978-08-31 | Hitachi Ltd | Semiconductor device having bonding pad |
| JPH0828389B2 (en) * | 1990-11-21 | 1996-03-21 | 三菱電機株式会社 | Semiconductor device |
| US6420255B1 (en) * | 1999-01-18 | 2002-07-16 | Nec Corporation | Mounting substrate with a solder resist layer and method of forming the same |
| JP4115832B2 (en) * | 2002-12-27 | 2008-07-09 | 東芝松下ディスプレイテクノロジー株式会社 | Semiconductor device and liquid crystal display panel |
| CN102254876A (en) * | 2010-05-21 | 2011-11-23 | 松下电器产业株式会社 | Semiconductor apparatus and semiconductor apparatus unit |
| JP2012054428A (en) * | 2010-09-01 | 2012-03-15 | Renesas Electronics Corp | Semiconductor device and semiconductor device manufacturing method |
| CN103094232A (en) * | 2011-11-02 | 2013-05-08 | 南茂科技股份有限公司 | Chip packaging structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104966676A (en) * | 2015-07-08 | 2015-10-07 | 上海新微技术研发中心有限公司 | Eutectic bonding method |
| CN104966676B (en) * | 2015-07-08 | 2018-04-27 | 上海新微技术研发中心有限公司 | eutectic bonding method |
| CN107546174A (en) * | 2017-07-28 | 2018-01-05 | 中国科学院微电子研究所 | A kind of process of ic component |
| CN116741648A (en) * | 2023-08-11 | 2023-09-12 | 四川遂宁市利普芯微电子有限公司 | Flip chip packaging method and flip chip packaging structure |
| CN116741648B (en) * | 2023-08-11 | 2023-11-17 | 四川遂宁市利普芯微电子有限公司 | Flip chip packaging method and flip chip packaging structure |
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|---|---|
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