CN104505027A - 一种电源电路、阵列基板及显示装置 - Google Patents
一种电源电路、阵列基板及显示装置 Download PDFInfo
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Abstract
本发明提供一种电源电路、阵列基板及显示装置,解决了现有技术中由于不同行像素单元的电压降不同产生的mura现象,所述电源电路包括:至少两条电源线,每条电源线用于向与电源线连接的一行像素单元提供电源电压,至少两条电源线包括第一电源线和第二电源线,第一电源线和第二电源线之间设置有与门,以使第一电源线和第二电源线在同时输出高电平电压时互相电连接。本发明的电源电路通过在电源线之间增加与门,使电源线在同时输出高电平时互相电连接,因此,两行电源线之间连接点处的电压接近,降低不同行像素单元之间的电压差异,从而改善由于不同行像素单元的电压降不同产生的mura现象,结构简单,成本低。
Description
技术领域
本发明涉及有机发光显示领域,特别是指一种电源电路、阵列基板及显示装置。
背景技术
目前,OLED(organic light emitting diode,简称有机发光二极管)显示器成为国内外非常热门的新兴平面显示器产品,这是因为OLED显示器具有自发光、广视角、短反应时间、高发光效率、广色域、低工作电压、面板薄、可制作大尺寸与可挠曲的面板及制程简单等特性,而且它还具有低成本的潜力。
在大尺寸显示应用中,由于背板电源线存在一定电阻,且所有像素的驱动电流都由VDD提供,因此在背板中靠近电源供电位置区域的电源电压相比较离供电位置较远区域的电源电压要高,这种现象被称为IR Drop(压降),现有技术中,如图1所示(图1中的电阻符号表示的是各段电源线的等效电阻),对于由各行VDD单独驱动的AMOLED(有源矩阵有机发光二极管)器件,在发光二极管D1发光时,若发光二极管D2和D3不发光或流向D2和D3的电流极小,则流向发光二极管D4的电流增加,由此,在相邻行或多行之间也会导致亮度差异,即产生mura(显示器亮度不均匀,造成各种痕迹)现象,产生的mura现象如图2所示(注意,每个区域可以是多行像素),中间行的区域2接近电源供电位置区域,区域4远离电源供电位置,中间行有暗区3(即有类似图1的发光二极管D2和D3的情况),而标为区域1的上下两行无暗区。则区域1每行像素全亮,即由电源供电位置较近处至离电源供电位置较远处,渐渐变暗;而对于中间行,区域3处为暗区,则显示现象为区域2比区域1稍亮,但区域4比区域1亮很多,从而在显示时会产生不同行的像素单元之间发光亮度不均匀的现象。
发明内容
针对现有技术的不足,本发明提出一种电源电路、阵列基板及显示装置,可以改善由于不同行像素单元之间的电压降不同导致的mura现象。
第一方面,本发明提供一种电源电路,包括:
至少两条电源线,所述每条电源线用于向与所述电源线连接的一行像素单元提供电源电压,所述至少两条电源线包括第一电源线和第二电源线,所述第一电源线和第二电源线之间设置有与门,以使所述第一电源线和所述第二电源线在同时输出高电平电压时互相电连接。
优选地,所述与门包括第一晶体管和第二晶体管,所述第一晶体管的漏极连接所述第一电源线,所述第一晶体管的栅极连接第二电源线,所述第一晶体管的源极连接所述第二晶体管的漏极,所述第二晶体管的栅极连接所述第一电源线,所述第二晶体管的源极连接所述第二电源线。
优选地,在所述像素单元的发光阶段,所述电源线的电源电压可以在高电平和低电平之间切换。
优选地,所述第一电源线和第二电源线为相邻的电源线。
优选地,每两相邻所述的电源线之间均设置有与门。
优选地,所述与门与所述两条电源线的连接点位于所述两条电源线远离电源的端。
优选地,所述与门为多个,所述多个与门与所述两条电源线的连接点间隔地设置在所述两条电源线上。
第二方面,本发明提供一种阵列基板,包括:上述任一所述的电源电路。
第三方面,本发明一种显示装置,包括:上述所述的阵列基板。
本发明提供的一种电源电路、阵列基板及显示装置,通过在两条电源线中增加与门,以使两条电源线在同时输出高电平电压时互相电连接,因此,两条电源线之间连接点处的电压接近,降低不同行的像素单元之间的电压差异,从而改善由于不同行像素单元的电压降不同产生的mura现象,结构简单,成本低。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为现有技术中电源电路的结构示意图;
图2为现有技术中mura现象的示意图;
图3为本发明实施例提供的电源电路的结构示意图;
图4为图3中的电源线的供电电压的时序图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清除、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例,基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
除非另作定义,本文使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。同样,“一个”、“一”或者“该”等类似词语也不表示数量限制,而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“上”、“下”、等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。“连接”不限于具体的连接形式,可以是直接连接,也可以是通过其他部件间接连接,可以是不可拆卸的连接,也可以是可拆卸的连接,可以是电气或信号连接,也可以是机械或物理连接。
图3示出了本发明实施例提供的电源电路的结构示意图,如图3所示,本实施例的电源电路,包括:至少两条电源线,每条电源线用于向与电源线连接的一行像素单元提供电源电压,至少两条电源线包括第一电源线VDD(n)和第二电源线VDD(n+1),第一电源线VDD(n)和第二电源线VDD(n+1)之间设置有与门,以使第一电源线VDD(n)和第二电源线VDD(n+1)在同时输出高电平电压时互相电连接。
本实施例中,当第一电源线Vdd(n)和第二电源线Vdd(n+1)的输出电压均为高电平时,第一电源线VDD(n)和第二电源线VDD(n+1)互相电连接,即第一电源线VDD(n)和第二电源线VDD(n+1)在与门的两个连接点处的电压接近(由于构成与门的器件中存在电阻,难以完全相同),进而使得与第一电源线Vdd(n)连接的一行像素单元和与第二电源线VDD(n+1)连接的一行像素单元的驱动电压趋近,缓解了由于其中一行中某些像素单元电流小而使得不同行的像素单元之间的电压降差异较大的问题,从而改善不同行像素单元之间由于电压降差异产生的mura现象。
具体地,如图3所示,所述与门包括第一晶体管T1和第二晶体管T2,第一晶体管T1的漏极连接第一电源线VDD(n),第一晶体管T1的栅极连接第二电源线VDD(n+1),第一晶体管T1的源极连接第二晶体管T2的漏极,第二晶体管T2的栅极连接第一电源线VDD(n),第二晶体管T2的源极连接第二电源线VDD(n+1)。
进一步如图3所示,第一晶体管T1的栅极与第二晶体管T2的源极相交于第二电源线VDD(n+1)上的b点,第一晶体管T1漏极与第二晶体管T2的栅极连接到相交于第一电源线VDD(n)上a点,第一晶体管T1源极与第二晶体管T2的漏极相交于c点。
一般而言,第一晶体管T1和第二晶体管T2可选用噪声小、功耗小的薄膜晶体管TFT,因此,可与阵列基板上的其他薄膜晶体管一起在相同的工序中制作。
本实施例中,与门与两条电源线的连接点优选位于两条电源线远离电源的端,可以理解为,若供电位置位于电源线的首端,则与门与两条电源线的连接点a点和b点分别位于第一电源线VDD(n)和第二电源线VDD(n+1)远离供电位置的末端,从而使两条电源线的末端电压相同,如在背景技术中所分析的,越远离电源,则mura现象越严重,因此使两条电源线的末端电压接近,则能更好的改善不同行的像素单元之间的电压降不同产生的mura现象。
应说明的是,本实施例不对a点和b点的位置进行具体限定,可根据实际需要自行设定。
图4示出了图3中的电源线的供电电压的时序图,具体而言,示出了第一电源线VDD(n)和第二电源线VDD(n+1)的工作波形,如图4所示,第一电源线VDD(n)和第二电源线VDD(n+1)的供电电压包括三个阶段:P1阶段、P2阶段和P3阶段。
如图3和图4所示,本实施例的电源电路的工作原理为:
在P1阶段,第一电源线Vdd(n)的输出电压为低电平,第二电源线Vdd(n+1)的输出电压为高电平,因此,第一晶体管T1的栅极为高电平,第一晶体管T1的漏极为低电平,此时,第一晶体管T1处于导通状态,c点的电压Vc接近于a点电压Va,均为低电压;此外,第二晶体管T2的栅极为低电平,第二晶体管T2的源极为高电平,此时,第二晶体管T2处于截止状态,使第一电源线Vdd(n)与第二电源线Vdd(n+1)之间没有互联,第一电源线Vdd(n)完成补偿动作。
在P2阶段,第一电源线Vdd(n)的输出电压为高电平,第二电源线Vdd(n+1)的输出电压为低电平,因此,第一晶体管T1的栅极为低电平,第一晶体管T1的漏极为高电平,此时,第一晶体管T1处于截止状态,此外,第二晶体管T2的栅极为高电平,第二晶体管T2的源极为低电平,此时,第二晶体管T2处于导通状态,c点的电压Vc接近于b点电压Vb,均为低电压,第一电源线Vdd(n)与第二电源线Vdd(n+1)之间没有互联,第二电源线Vdd(n+1)完成补偿动作。
在P3阶段,第一电源线Vdd(n)和第二电源线Vdd(n+1)的输出电压均为高电平,此时,第一晶体管T1和第二晶体管T2都处于导通状态,c点电压Vc会接近于a,b两点之中的最高电压,从而使第一电源线Vdd(n)与第二电源线Vdd(n+1)之间形成互联,第一电源线VDD(n)和第二电源线VDD(n+1)在与门连接点处的电压彼此接近,从而改善不同行的像素单元之间由于电压降不同产生的mura现象。
在图示中,与门的个数为一个,但是,本实施例不对与门的个数进行限定,可以根据实际需要自行设定。在实际中,与门的个数可以为多个,多个与门与两条电源线的连接点间隔地设置在两条电源线上,从而使两条电源线在发光阶段在多处的电压两两彼此接近,从而使不同行的像素单元之间的发光二极管的驱动电压更为接近,因而显示更均匀。
本实施例中,在发光阶段,每条电源线的电源电压可以在高电平和低电平之间切换,如本领域技术人员应该知道的,切换到低电平一般是为了实现补偿等功能的需要。而在第一电源线Vdd(n)或第二电源线Vdd(n+1)的输出电压为低电平时,由于构成与门的晶体管均截止,使第一电源线Vdd(n)与第二电源线Vdd(n+1)之间没有电连接,由于第一电源线Vdd1和第二电源线Vdd2不进行电连接,第一电源线Vdd(n)或第二电源线Vdd(n+1)可以正常完成补偿动作,从而防止影响低电平时补偿等功能。
第一电源线Vdd(n)和第二电源线Vdd(n+1)优选为相邻的两条电源线,由于第一电源线Vdd(n)和第二电源线Vdd(n+1)在输出电压均为高电平时形成导通互联,从而防止相邻的两条电源线之间的串扰现象。
一般情况下,像素单元为多行,因此本实施例的电源线也需要为多条,上述的第一电源线和第二电源线是其中的示例,所以更优选的方案是,所有电源线中的每两条相邻电源线之间均设置有与门,从而使电源线形成网状VDD结构,避免不同行像素单元的电压降不同导致的mura现象,并解决了相邻电源线之间的串扰问题。
本发明实施例还提供一种阵列基板,所述阵列基板包括上述实施例中任一所述的电源电路,该电源电路的结构和原理在上面已经充分进行了说明,此处不再详述。
本实施例的阵列基板减轻了了不同行的像素单元之间发光亮度不均匀的问题,进而提高了发光器件的显示均匀性。
本发明实施例还提供一种显示装置,所述显示装置包括上述实施例中的阵列基板。显示装置可以为:电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。本发明虽然是以OLED显示器件为例进行说明,但本领域技术人员应该理解,对于存在由于IR Drop导致的不同行的像素单元之间的电压降不同而产生的mura现象的显示器件,本发明都能得到有效应用。
本实施例的显示装置减轻了不同行的像素单元之间的发光亮度不均匀的问题,进而提高了发光器件的显示均匀性。
显然,本领域的技术人员可以对半发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求以及等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (9)
1.一种电源电路,其特征在于,包括:
至少两条电源线,所述每条电源线用于向与所述电源线连接的一行像素单元提供电源电压,所述至少两条电源线包括第一电源线和第二电源线,所述第一电源线和第二电源线之间设置有与门,以使所述第一电源线和所述第二电源线在同时输出高电平电压时互相电连接。
2.如权利要求1所述的电源电路,其特征在于,所述与门包括第一晶体管和第二晶体管,所述第一晶体管的漏极连接所述第一电源线,所述第一晶体管的栅极连接第二电源线,所述第一晶体管的源极连接所述第二晶体管的漏极,所述第二晶体管的栅极连接所述第一电源线,所述第二晶体管的源极连接所述第二电源线。
3.如权利要求1所述的电源电路,其特征在于,在所述像素单元的发光阶段,所述电源线的电源电压可以在高电平和低电平之间切换。
4.如权利要求1所述的电源电路,其特征在于,所述第一电源线和第二电源线为相邻的电源线。
5.如权利要求1所述的电源电路,其特征在于,每两相邻所述的电源线之间均设置有与门。
6.如权利要求2所述的电源电路,其特征在于,所述与门与所述两条电源线的连接点位于所述两条电源线远离电源的端。
7.如权利要求2所述的电源电路,其特征在于,所述与门为多个,所述多个与门与所述两条电源线的连接点间隔地设置在所述两条电源线上。
8.一种阵列基板,其特征在于,包括:
如权利要求1-7任一项所述的电源电路。
9.一种显示装置,其特征在于,包括:
如权利要求8所述的阵列基板。
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