CN104484301B - A kind of IO bus units based on FPGA with self-recognition function - Google Patents

Abstract

The present invention has the IO bus units of self-recognition function based on FPGA, belongs to bussing technique field.The present invention includes CPU, FPGA, groove position plate, parallel bus, universal serial bus and fieldbus, and the CPU carries out data interaction by external bus and FPGA, and the FPGA is interacted by parallel bus or universal serial bus with groove position plate；CPU passes through fieldbus and groove position plate direct interaction；The FPGA provides plate address to CPU, and helps CPU to send and receive provided with state machine in data, the FPGA, and state machine, which can be circulated, chooses plate interface, reads plate information and data-signal.The present invention has the function of self-identifying plate information, enhances the reliability of data interaction.Communicated between plate more flexibly, facilitate apparatus platform update.FPGA is interacted by parallel bus as CPU and the bridge of external data with universal serial bus to plate data.

Description

A kind of IO bus units based on FPGA with self-recognition function

Technical field

The present invention relates to bussing technique field, more particularly to expansible electric equipment protection device.

Background technology

In traditional electric equipment protection device, host CPU plate and open, output, the connection between the plate such as analog quantity is adopted With dedicated bus, data interaction is directly set up between host CPU and various plates, and such a data transfer mode exists many intrinsic Defect.First, this transmission means fixes the position of each block of plate, i.e., each block plate can only be inserted in the fixed position of backboard, Line between backboard and host CPU plate has just been fixed at the beginning of design, and each groove position is unable to the other kinds of plate of grafting on backboard Part.Secondly, plate wrong plug may cause device to damage, and especially misplug wrong power panel or simulation template, it would be possible to cause host CPU Plate is damaged.3rd, there is no intelligent self-checking function and identification function because dedicated connection is various, and in protection device, in length In phase work, it may occur that aoxidized at plate connector, cause plate to be connected unreliable with backboard, input signal can not correctly be known Not, output signal may also malfunction.4th, the increase in demand with power equipment to protection device, CPU needs often more New to regenerate, traditional device generally requires significantly to change hardware and program.

The content of the invention

In order to solve above-mentioned problems of the prior art, self-identifying work(is had based on FPGA the invention provides one kind The IO bus units of energy.Various plate optional positions are realized to install, and host CPU has self-identifying plate function, so as to increase The strong reliability of electric equipment protection device.Meanwhile, by FPGA managing I/O buses, hardware platform upgrading is facilitated, CPU is more It is new to regenerate.

The technical solution adopted in the present invention is as follows.

A kind of IO bus units based on FPGA with self-recognition function, including it is CPU, FPGA, groove position plate, parallel total Line, universal serial bus and fieldbus, the CPU carry out data interaction by external bus and FPGA, and the FPGA passes through simultaneously Row bus or universal serial bus are interacted with groove position plate；CPU passes through fieldbus and groove position plate direct interaction；The FPGA is carried For plate address to CPU, and CPU is helped to send and receive data.State machine is provided with the FPGA, state machine can circulate choosing Middle plate interface, reads plate information and data-signal.

The parallel bus uses data wire, chip select line, write signal line, reading signal lines, and data wire is that each groove position is public, and And data transfer is two-way；Each plate interface all connects chip select line；Partly it is used to read plate information in reading signal lines.

The data wire is 8, and the route selection is 1, and the write signal line is 4, and the reading signal lines are 6, its In 2 reading signal lines be used as reading plate information, 4 are used as read functions data.

The plate information is made up of 28 data, includes 5 plate types, 3 hardware versions, 5 BOM versions, 3 Position fixed code.

The register that sends and receives of the FPGA uses FIFO data cached.

The fieldbus is CAN, and the universal serial bus is RS485 universal serial bus.

Based on FPGA there is the IO bus units of self-recognition function to be unified to parallel bus and universal serial bus by FPGA Management, FPGA as CPU and the main bridge of each plate data interaction.Parallel bus using 8 position datawires, 1 bit slice route selection, 4 write signal lines, 6 reading signal lines.Universal serial bus can be RS485 universal serial bus.FPGA is serial by parallel bus and RS485 Bus is connected with each plate.FPGA provides plate interface IP address to CPU, and helps CPU to send and receive data.Will for speed Higher data volume is asked to be communicated using CAN, CPU is directly communicated with each plate.

Parallel bus in FPGA controls, backboard each groove position to that should have respective CS chip select lines.8 data are all Groove position is public, and data wire is two-way, and FPGA can send data to each plate, can also read the data of each plate. WR write signal lines have 4, coordinate 8 position datawires, can send 32 data to the plate of each groove position, as control is outputed on plate Relay, veneer could support up 32 relays.Same reading signal lines have 6, wherein 2 are used as reading plate information, Remaining 4 are used as read functions data, and as read the intake opened into plate, single plate could support up 32 and open into signal. Each groove position is chosen in the circulation of use state machine in FPGA, and the plate information and data-signal for reading each groove position (are such as opened Enter amount), data are then written to corresponding plate (such as control relay).Self-recognition function is by reading plate information realization , plate information is made up of 28 data.Plate packet is containing 5 plate types, 3 hardware versions, 5 BOM versions, 3 Position fixed code (such as 010).Fixed code is used to judge whether plate inserts, and is easy to investigation to cause plate information errors because of welding error Phenomenon.

Universal serial bus is used for the deficiency for supplementing parallel bus, when host CPU plate needs to communicate with special plate, just using string Row bus transmit data.When being needed such as direct current sampling plate host CPU plate is issued in sampled data, direct current sampling plate passes through RS485 Communicated with host CPU plate.RS485 serial communication bus is also to realize that FPGA is by RS485 serial bus transmissions by FPGA simulations uart Data be supplied to cpu i/f.The FPGA register that sends and receives can be data cached using FIFO, so reduces CPU's Consumption.RS485 universal serial bus is left in each groove position on backboard, facilitates each groove position to be communicated with host CPU plate.CAN It is same design, only CPU and plate Direct Communication, are uniformly controlled without FPGA.

Parallel bus can not only work independently the different data of transmission from universal serial bus, can also cooperate, all use To transmit data of the same race.For critical data using parallel bus transfers to CPU, while also using serial bus transmission to CPU, So enhance the reliability of transmission data.

Beneficial effect：

The present invention has made improvement relative to traditional electric equipment protection device internal data bus.

First, bus to each groove position plate can self-identifying, can so read plate information, self-identifying plate Type, the information such as hardware version, is easy to program to handle, enhances the versatility of each plate.

Secondly, each groove position of design point machine loop control in FPGA, enhances the flexibility of plate position, each groove Position no longer fixation can only insert single plate, but each groove position can any plate of grafting.

3rd, data transfer both can also can also pass through two classes simultaneously by parallel bus by universal serial bus Bus transfer, enhances the reliability of data.And in FPGA the dithering process that disappears can be carried out to intake, enhance and open into number According to reliability.

4th, FPGA control parallel bus and universal serial bus, and program does not need uart drivings, convenient master for host CPU CPU is updated, it is only necessary to write the code with FPGA communication parts, it is possible to which control is outputed, reads and open into and exchange plate The functions such as data.

5th, operation when digital independent of the present invention and write-in between host CPU and FPGA can retain 32, this method The expense of host CPU is saved to a certain extent, the utilization rate of host CPU is reduced, and the intake simultaneously for reading can be with Do to disappear and tremble processing, do to disappear to tremble handling the expense that another step saves host CPU in FPGA.

6th, above-mentioned RS485 series bus controllers are used in FPGA, overall versatility is enhanced, host CPU is visited Ask that above address can just realize RS485 serial communications, save inquiry or the break period of host CPU.

7th, data can reach host CPU from different bus runs respectively, for the high signal of rate requirement, pass through CAN is directly connected with the CPU of mainboard, this ensure that the promptness of signal.For the relatively low signal of speed, it can pass through RS485 bus transfer datas.

8th, parallel bus can not only work independently the different data of transmission from universal serial bus, can also cooperate, All it is used for transmitting data of the same race.For critical data using parallel bus transfers to host CPU, while also using serial bus transmission To host CPU, the reliability of transmission data is so enhanced.

It is a feature of the present invention that whether can have plate insertion, self-identifying insertion plate for some groove position with self-identifying The information such as type, hardware version.And the warm connection function of plate can thus be realized with Dynamic Recognition.While plate The design of part is not limited to certain product, and different product can use veneer of the same race, the input and output plate especially largely used Part.

Brief description of the drawings

Fig. 1 is the overall structure block diagram of the present invention.

Fig. 2 is the circuit diagram that the present invention reads plate information.

Embodiment

As shown in figure 1, the present embodiment includes host CPU plate, the groove position of grafting plate is three kinds of bus parallel buses, serial total Line and fieldbus, host CPU plate include CPU module and FPGA module.Wherein these three buses are all connected with each groove position.Each Groove position can use these three buses to send data.Except CAN is directly to be connected by CPU and groove, remaining be all by FPGA is connected with groove position, unified management parallel bus and RS485 buses.

There are each different places each groove position, and each groove position has CS chip select lines to be connected with FPGA, and such FPGA just can be with Time-sharing multiplex parallel bus.

Parallel bus is made up of CS chip select lines, 2 RD_ID, 4 RD, 4 WR and 8 data lines, as shown in table 1.

The specific terminal of the bus of table 1 defines table

	A	B	C
				1		CS
2
				3	DATA1	DGND	DATA0
4	DATA3	DGND	DATA2
				5	DATA5	DGND	DATA4
6	DATA7	DGND	DATA6
				7	RD_1	DGND	RD_0
8	RD_3	DGND	RD_2
				9	RD_ID1	DGND	RD_ID0
10	WR_1	DGND	WR_0
				11	WR_3	DGND	WR_2
12	+3.3V	CAN_H	RS485+
				13	+3.3V	CAN_L	RS485-
14	+5V	+5V	+5V
				15	+24V	+24V	+24V
16	24GND	24GND	24GND

FPGA state machine is selected by piece, reading writing signal line is read and write-in data.Read 5 plate types and 3 hard The circuit of part version is as shown in Figure 2.When chip select line CS and RD_ID0 is simultaneously low level, BOARD_RD_ID0 signals are low electricity Flat, buffer will be transferred to the 5 type codes 0x07 and 3 hardware version numbers 0x0 of this plate on 8 position datawires, FPGA can just read type and the version number of the plate.Same method can read No. BOM of plate and for determining plate The fixed code whether part is plugged.16 plate information definitions are as shown in table 2.

2 16 plate information definition tables of table

When reading 32 data (such as intakes) from plate, using the method same with reading plate information, pass through 4 RD Signal wire reads 8 data respectively, and 32 data volumes are combined into FPGA, facilitates 32 bit CPUs (such as ARM) to access.To When plate writes 32 data (such as relays), chip select line CS and 4 WR lines coordinate, and are respectively written into 8 data.Now CPU with Operation between FPGA can also retain 32.This method saves CPU expense to a certain extent, reduces CPU's Utilization rate, the intake simultaneously for reading can also be done to disappear and tremble processing, do to disappear in FPGA and tremble the another step of processing and save CPU Expense.

As shown in table 1, do not only have parallel bus in bus, and leave two kinds of serial line interfaces of RS485 and CAN.For speed Rate requires high signal, is directly connected by CAN with the CPU of mainboard, this ensure that the promptness of signal.For speed Relatively low signal, can pass through RS485 bus transfer datas.RS485 buses are FPGA on mainboard and veneer connecting line, 2 FIFO are opened up in FPGA for cache bus data, while so ensureing that data do not lose transmission, CPU waits are reduced Time, and for CPU program do not need uart driving, facilitate CPU to update, it is only necessary to write and FPGA communicate Partial code, it is possible to control output, read open into power board number of packages according to etc. function.

The RS485 EBIs address such as following table of FPGA controls.

The RS485 EBI address tables of the FPGA of table 3 controls

0x3800_C000	RS485 control registers；Energy when 0bit is, 1bit is internal loopback, and 2bit is reset
		0x3800_C002	RS485 baud rate registers；Baud rate for calculating RS485
0x3800_C004	TX_FIFO usage amount registers；
		0x3800_C008	TX data registers；

0x3800_C00A	RX_FIFO usage amount registers；
		0x3800_C00E	RX data registers；

Above-mentioned RS485 series bus controllers are used in FPGA, are enhanced more than overall versatility, CPU access Address can just realize RS485 serial communications, save CPU inquiry or break period.

Claims (1)

1. a kind of IO bus units based on FPGA with self-recognition function, it is characterised in that including CPU, FPGA, groove position plate Part, parallel bus, universal serial bus and fieldbus, the CPU carry out data interaction by external bus and FPGA, described FPGA is interacted by parallel bus or universal serial bus with groove position plate；CPU passes through fieldbus and groove position plate direct interaction； The FPGA provides plate interface IP address to CPU, and helps CPU to send and receive in data, the FPGA provided with state machine, shape State machine, which can be circulated, chooses plate interface, reads plate information and data-signal；

The parallel bus uses data wire, chip select line, write signal line, reading signal lines, and data wire is that each groove position is public, and number It is two-way according to being transmitted as；Each plate interface all connects chip select line；Partly it is used to read plate information in reading signal lines；

The data wire is 8, and the route selection is 1, and the write signal line is 4, and the reading signal lines are 6, wherein 2 Reading signal lines are used as reading plate information, and 4 are used as read functions data；

The parallel bus in FPGA controls, backboard each groove position to that should have respective CS chip select lines；8 data are all Groove position is public, and data wire is two-way, and FPGA sends data to each plate, also reads the data of each plate；WR write signals Line has 4, coordinates 8 position datawires, and 32 data are sent to the plate of each groove position；Same reading signal lines have 6, wherein 2 Position is used as reading plate information, and remaining 4 are used as read functions data；Each groove is chosen in the circulation of use state machine in FPGA Position, and to reading the plate information and data-signal of each groove position, data are then written to corresponding plate；Self-recognition function is logical Cross and read plate information realization, the plate information is made up of 28 data, include 5 plate types, 3 hardware versions Originally, 5 BOM versions, 3 fixed codes；

The register that sends and receives of the FPGA uses FIFO data cached；

The fieldbus is CAN, and the universal serial bus is RS485 universal serial bus.