CN104484128A - Read-once and write-once storage based read-more and write more storage and implementation method thereof - Google Patents
Read-once and write-once storage based read-more and write more storage and implementation method thereof Download PDFInfo
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- CN104484128A CN104484128A CN201410707938.7A CN201410707938A CN104484128A CN 104484128 A CN104484128 A CN 104484128A CN 201410707938 A CN201410707938 A CN 201410707938A CN 104484128 A CN104484128 A CN 104484128A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0625—Power saving in storage systems
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Abstract
The invention discloses a read-once and write-once storage based read-more and write more storage and an implementation method thereof. The read-more and write more storage comprises n read-once write-m storage units, a state storing unit, a control logic, m writing ports and n reading ports, wherein n and m are both integer not less than 0; each read-once write-m storing unit is equipped with m read-once write-once storages; when writing through the write ports, data are synchronously written into one read-once and write-once storage of each read-once and write-m storage unit; the state storing unit is used for recording the storage state of data in each read-once and write-once storage; the control logic is used for controlling mode of the reading ports to reading data from each read-once and write-once storage according to a read address. Compared with the small-capacity nRmW storage based large-capacity nRmW storage, the read-once and write-once storage based read-more and write more storage has the advantages that the area of a chip can be greatly reduced, the power consumption of the chip is decreased, the time sequence of the chip is improved, and therefore, the overall performances are improved.
Description
Technical field
The present invention relates to the technical field of memory in exchange chip design, especially relate to a kind of read that a memory write realizes based on high density, jumbo jumbo read many memory writes and its implementation more.
Background technology
Usually to use in high-performance exchange chip jumbo read many memory writes (nRmWMemory, n read m memory write, n, m be more than or equal to 0 integer), as two read two memory write 2R2W memory.
The scheme realizing jumbo 2R2W memory at present is mainly spliced based on low capacity 2R2Wmemory.It is little that 2R2W memory unit has density, and capacity is little, the feature that power consumption is large, and its max cap. is very limited, and realize jumbo 2R2W memory then needs to be spliced by the 2R2W of multiple low capacity.This Large Copacity 2R2W memory be spliced based on low capacity 2R2W memory, its power consumption and area along with memory depth and width increase and linearly increase, and cablings a large amount of between 2R2W memory also causes the deterioration of sequential.
Therefore, adopt the nRmW Memory of low capacity to build jumbo nRmW Memory simple, but it is large to there is area, the problems such as power consumption height and difference of injection time, can not meet the requirement of high-performance exchange chip.
Summary of the invention
The object of the invention is to the defect overcoming prior art, there is provided a kind of based on one read a memory write read many memory writes more, adopt high density, jumbo to read a memory write to realize jumboly reading many memory writes more, with reduce exchange chip area, reduce the power consumption of chip and improve the sequential of chip.
For achieving the above object, the present invention proposes following technical scheme: a kind of based on one read a memory write read many memory writes more, comprise n individual and read m memory write unit, state storage unit and steering logic, n and m is the integer being more than or equal to 0, each described one reads have m individual to read a memory write in m memory write unit, read many memory write outside described more and there is m write port and n read port, when described write port has a write operation, it is write data and to write described in each described one one of them reading in m memory write unit one simultaneously and read in a memory write; Described state storage unit is for recording the store status that each described reads data in a memory write; Described steering logic for controlling described read port from the described mode reading to read in many memory writes data more.
Preferably, [log is used in described state storage unit
2m () rounds+1] individual bit represents the state data memory read corresponding to address of read port described in any one, if log
2m () is integer, then use log
2m () individual bit represents the state data memory read corresponding to address of read port described in any one.
Preferably, described write port write data to described one read a memory write while, upgrade state data memory corresponding in described state storage unit.
Preferably, same described one to read the data that each described one in m memory write unit read to store in a memory write be different, different described one reads described one of corresponding same write port in m memory write unit reads a memory write (as 11,21 ... n1 storer) data that store are identical.
Preferably, each described read port is read address according to it and is read to read data in a memory write from described one of correspondence.
Preferably, the mode that described read port reads data is: first from described state storage unit, read it reads data storage information corresponding to address to described read port, select to store one of data according to the described storage information read and read a memory write, finally read to read out data in a memory write from select described one.
Preferably, the mode that described read port reads data to read described in n × m block one for: described read port simultaneously read a memory write and state storage unit according to reading address, selects corresponding data to send out according to the state data memory read from described state storage unit.
Another object of the present invention is also to provide a kind of implementation method reading many memory writes reading a memory write based on more: adopt n × m block one to read a memory write and form described n and read m memory write, n and m is the integer being more than or equal to 0.
The invention has the beneficial effects as follows: the present invention realizes jumboly reading many memory writes nRmW memory by using high density, jumbo to read a memory write 1R1W memory more, compare and realize Large Copacity nRmW memory based on low capacity nRmW memory, greatly can reduce the area of chip, reduce the power consumption of chip, improve the sequential of chip, and then improve its overall performance.
Accompanying drawing explanation
Fig. 1 the present invention is based on the structural representation reading many memory writes that reads a memory write more;
Fig. 2 is that the embodiment of the present invention reads based on one the structural representation that two of a memory write reads two memory writes;
Fig. 3 is the read-write schematic flow sheet that the embodiment of the present invention two reads two memory writes;
Fig. 4 is that the embodiment of the present invention reads based on one the another kind of structural representation that two of a memory write reads two memory writes;
Fig. 5 is the area comparison diagram of storer that width that existing scheme and the present invention program generate is fixed as 32nm, different depth;
Fig. 6 is the power consumption comparison diagram of storer that width that existing scheme and the present invention program generate is fixed as 32nm, different depth;
Fig. 7 is that the embodiment of the present invention is read based on one or a structural representation reading a memory write of a memory write.
Embodiment
Below in conjunction with accompanying drawing of the present invention, clear, complete description is carried out to the technical scheme of the embodiment of the present invention.
Disclosed a kind of based on one read a memory write read many memory writes, in the reservoir designs for high-performance exchange chip more.The present invention is based on high density, a memory write (1R1W storer is read in one of low-power consumption, support that a read operation and one write action) simultaneously, add certain steering logic and state storage unit realizes reading many memory writes more, be expressed as nRmW storer, namely support that n read operation and m are individual simultaneously and write action, wherein n and m is the integer being more than or equal to 0, it is little that the nRmW storer realized has area, low in energy consumption, the feature that sequential is good, solve and adopt the nRmW storer of low capacity large to the area building the existence of jumbo nRmW storer, the problems such as power consumption height and difference of injection time.
As shown in Figure 1, disclosed a kind of based on one read a memory write read many memory writes more, realize based on n × m block 1R1W storer, also comprise a state storage unit, steering logic, a m outside write port and n outside read port, n, m are the integer being more than or equal to 0, n × m 1R1W storer are divided into a n 1RmW memory cell, namely divide into n group, each 1RmW memory cell (often group) is read a memory write by m individual and is formed.
Convenient in order to describe below, n 1RmW memory cell is defined as unit 1, unit 2 respectively ... unit n, in each memory cell one reads a memory write is then defined as storer n1, storer n2 respectively ... storer nm, storer 11, storer 12 is respectively as in unit 1 reads a memory write ... storer 1m, in unit 2 one reads a memory write is respectively storer 21, storer 22 ... storer 2m, m write port is defined as W1, W2 respectively ... Wm, n read port is defined as R1, R2 respectively ... Rn.
There is n number certificate, for writing data in each 1R1W memory cell in each write port.When write port has write operation, its by n number according in one of them the 1R1W storer write in each 1RmW memory cell simultaneously, as in Fig. 1, write port W1 writes data to storer 11, storer 21 simultaneously ... in storer n1, the 1R1W storer of the same write port of correspondence in each 1RmW memory cell is (as storer 11,21 ... n1) data stored are all identical.
State storage unit is for recording the store status of each 1R1W storer store data inside.The state data memory of state storage unit also will be upgraded while data are write n × m block 1R1W storer by write port, as when write port W1 carries out write operation, simultaneously by storer 11, storer 21 ... the address date of the write port W1 of storer n1 is labeled as effectively.[log is at the most used in state storage unit
2m () rounds+1] individual bit reads state data memory corresponding to address, if log to what represent certain read port
2m () is integer, then use log
2m () individual bit represents.
Steering logic for controlling read port from the mode reading to read in many memory writes data more, in the present invention, read port comprises two kinds from the mode reading to read in many memory writes data more, be any the block 1R1W storer first judging to read in which 1RmW memory cell, then go to perform read operation.Particularly, first from state storage unit, read it reads data storage information corresponding to address to certain read port, judges to go which block 1R1W storer to read, and then perform read operation according to the storage information read.
Simultaneously another kind reads n × m block 1R1W storer and state storage unit, selects effective data to send out according to the state data memory that state storage unit is read.
The first data reading mode, can save chip power-consumption, but adds the time delay of chip, and this reading manner may be defined as low-power consumption mode; Another kind decreases time delay, improves performance, but the power consumption of chip has become greatly, and this reading manner may be defined as high performance mode.Concrete selection which kind of mode above-mentioned reads data depending on applicable cases, if any the applicable cases performance that needs storer to read high, time delay is little, then need the storer with above-mentioned high performance mode; If some applicable cases need the low in energy consumption of chip, requirement is not had to time delay, then with the storer of above-mentioned low-power consumption mode.
The embodiment of the present invention illustrates technical scheme of the present invention to realize 2R2W storer based on 1R1W storer.As shown in Figure 2, the 2R2W storer that the embodiment of the present invention realizes is based on the 1R1W storer of 4 target capacities, be respectively storer 0, storer 1, storer 2 and storer 3, and state storage unit, steering logic, two outside write port WA and WB, two outside read port RA and RB, the write address of write port WA and WB is defined as WAAddr and WBAddr respectively, and the address of reading of read port RA and RB is defined as RAAddr and RBAddr respectively.
These four 1R1W storeies are divided into two groups, and storer 0 and storer 1 are first group, and storer 2 and storer 3 are second group.Storer 2 in storer 0 in corresponding first group of write port WA and second group, storer 3 in storer 1 in corresponding first group of write port WB and second group, like this when write port WA has write operation, data are write in storer 0 and storer 2 by it simultaneously, as shown in the step 1 in Fig. 3, in like manner, when write port #WB has a write operation, it is write data and writes in storer 1 and storer 3, simultaneously as shown in the step 2 in Fig. 3.
State storage unit in the embodiment of the present invention 1 bit represents state data memory in each storer, namely represents that valid data poke is in storer 0 or storer 2 with " 0 ", and " 1 " represents that valid data are stored in storer 1 or storer 3.Upgrade the state data memory in state storage unit while data are write 4 pieces of 1R1W storeies by write port WA and WB, the WAAddr data markers by storer 0 and storer 2 is effectively, is also designated as effectively by the WBAddr data mark of storage 1 and storage 3.
Steering logic for controlling read port RA or read port RB from the mode reading to read in many memory writes data more.In the embodiment of the present invention, the reading manner of read port RA or read port RB is divided into two kinds, one as shown in Figure 2, steering logic is made up of multiple register and selector switch, control read port and read 4 pieces of 1R1W storeies and state storage unit simultaneously, select effective data to send out according to the result that state storage unit is read.Particularly, when read port RA reads data, data can be read from storer 0 and storer 1 simultaneously, and differentiate that the data in storer 0 or storer 1 are effective according to the state data memory in state storage unit, therefrom selecting valid data, if read port RA is " 0 " according to reading the data that address RAAddr reads in state storage unit, then reading the data in storer 0, otherwise select the data in storer 1, as the step 3 of Fig. 3; In like manner, if read port RB is " 0 " according to reading the data that address RBAddr reads in state storage unit, then the read data of selector switch selection memory 2 is sent out, otherwise selects the data of storer 3, as the step 4 of Fig. 3.
Another kind as shown in Figure 4, steering logic is made up of multiple register and moderator, control read port and first from state storage unit, read the corresponding data storage information reading address, any judge specifically to go block storage to go to read according to the storage information read, and then perform read operation, namely control read port and first judge to read any block storage, then go to perform read operation.Particularly, if according to read port RA to read the data that address RAAddr reads in state storage unit be " 0 ", namely represent and read valid data corresponding to address RAAddr in storer 0, if according to read port RB to read the data that address RBAddr reads in state storage unit be " 1 ", namely represent and read valid data corresponding to address RBAddr in storer 3, then according to reading address RAAddr memory read 0, read address RBAddr memory read 3.If the data that read port RA and RB reads in state storage unit are " 0 ", namely read valid data corresponding to address RAAddr and RBAddr all in storer 0, from aforementioned,
Storer 0 is the same with the data in storer 2, so read address RAAddr from storer 0, reads address RBAddr and can obtain corresponding read data from storer 2.
If two read ports want read data simultaneously, and two write ports will write data simultaneously, then the step 1 in Fig. 3 is to step 4 executed in parallel simultaneously.
Following table 1 is area and the power consumption contrast of existing scheme and technical scheme of the present invention under the storage chip 32nm technique of IBM, wherein existing scheme is the scheme adopting low capacity 2R2W storer to be assemblied into jumbo 2R2W storage, and new departure is the scheme based on Large Copacity 1R1W memory.
Table 1
In addition, Fig. 5 and Fig. 6 adopts existing scheme and the present invention program to generate width to be fixed as 32nm, the area comparison diagram of storer of different depth and power consumption comparison diagram respectively under the storage chip 32nm technique of IBM, as can be seen from table 1 composition graphs 5 and Fig. 6, compare the area that existing scheme substantially reduces chip when generating Large Copacity 2R2W storer according to the present invention, reduce power consumption.
Therefore, based on this, the design of polytype storage chip can be realized by technical scheme of the present invention, as read based on one or a memory write realizes 1R1W storer, realize 3R2W storer based on 1R1W storer, 3R3W storer or 4R4W storer etc., it is a kind of highly versatile, simple and practical memory construction, as shown in Figure 7, for realizing the structural representation of 1R1W storer based on 1RW storer.
Technology contents of the present invention and technical characteristic have disclosed as above; but those of ordinary skill in the art still may do all replacement and the modification that do not deviate from spirit of the present invention based on teaching of the present invention and announcement; therefore; scope should be not limited to the content that embodiment discloses; and various do not deviate from replacement of the present invention and modification should be comprised, and contained by present patent application claim.
Claims (8)
1. one kind based on one read a memory write read many memory writes more, it is characterized in that: comprise n individual and read m memory write unit, state storage unit and steering logic, n and m is the integer being more than or equal to 0, each described one reads have m individual to read a memory write in m memory write unit, read many memory write outside described more and there is m write port and n read port, when described write port has a write operation, it is write data and to write described in each described one one of them reading in m memory write unit one simultaneously and read in a memory write; Described state storage unit is for recording the store status that each described reads data in a memory write; Described steering logic for controlling described read port from the described mode reading to read in many memory writes data more.
2. according to claim 1 based on one read a memory write read many memory writes more, it is characterized in that, with being less than or equal to [log in described state storage unit
2m () rounds+1] individual bit represents the state data memory read corresponding to address of read port described in any one, if log
2m () is integer, then use log
2m () individual bit represents the state data memory read corresponding to address of read port described in any one.
3. according to claim 1 based on one read a memory write read many memory writes more, it is characterized in that, described write port write data to described one read a memory write while, upgrade state data memory corresponding in described state storage unit.
4. according to claim 1 based on one read a memory write read many memory writes more, it is characterized in that, same described one to read the data that each described one in m memory write unit read to store in a memory write be different, different described one reads described one of corresponding same write port in m memory write unit reads a memory write (as 11,21 ... n1 storer) data that store are identical.
5. according to claim 1 based on one read a memory write read many memory writes more, it is characterized in that, each described read port is read address according to it and is read to read data in a memory write from described one of correspondence.
6. according to claim 1 or 5 based on one read a memory write read many memory writes more, it is characterized in that, the mode that described read port reads data is: first from described state storage unit, read it reads data storage information corresponding to address to described read port, select to store one of data according to the described storage information read and read a memory write, finally read to read out data in a memory write from select described one.
7. according to claim 1 or 5 based on one read a memory write read many memory writes more, it is characterized in that, the mode that described read port reads data to read described in n × m block one for: described read port simultaneously read a memory write and state storage unit according to reading address, selects corresponding data to send out according to the state data memory read from described state storage unit.
8. realize the method reading many memory writes according to claim 1 more, it is characterized in that: adopt n × m block one to read a memory write and form described n and read m memory write, n and m is the integer being more than or equal to 0.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106302260A (en) * | 2016-07-28 | 2017-01-04 | 盛科网络（苏州）有限公司 | 4R4W shares data buffer storage processing method and the data handling system of message entirely |
| CN106297861A (en) * | 2016-07-28 | 2017-01-04 | 盛科网络（苏州）有限公司 | The data processing method of extendible multiport memory and data handling system |
| CN106445831A (en) * | 2015-08-11 | 2017-02-22 | 深圳市中兴微电子技术有限公司 | Storage unit and processing system |
| WO2019183849A1 (en) * | 2018-03-28 | 2019-10-03 | 深圳市大疆创新科技有限公司 | Data processing method and device |
| CN110704369A (en) * | 2019-10-09 | 2020-01-17 | 盛科网络（苏州）有限公司 | Memory and control method thereof |
| CN111143079A (en) * | 2019-12-24 | 2020-05-12 | 浪潮软件股份有限公司 | Method for realizing multi-read multi-write lock-free queue |
| CN114519023A (en) * | 2022-02-18 | 2022-05-20 | 芯河半导体科技(无锡)有限公司 | Method for realizing multiport Ram |
| CN114968861A (en) * | 2022-05-25 | 2022-08-30 | 中国科学院计算技术研究所 | Two-write two-read data transmission structure and on-chip multi-channel interactive network |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102436427A (en) * | 2011-11-07 | 2012-05-02 | 华为技术有限公司 | Data read-write method and storage device |
| CN103309626A (en) * | 2013-07-03 | 2013-09-18 | 盛科网络（苏州）有限公司 | Method for realizing multi-read-write port memorizer of network chip and corresponding memorizer |
| US20140321471A1 (en) * | 2013-04-26 | 2014-10-30 | Mediatek Inc. | Switching fabric of network device that uses multiple store units and multiple fetch units operated at reduced clock speeds and related method thereof |
-
2014
- 2014-11-27 CN CN201410707938.7A patent/CN104484128A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102436427A (en) * | 2011-11-07 | 2012-05-02 | 华为技术有限公司 | Data read-write method and storage device |
| US20140321471A1 (en) * | 2013-04-26 | 2014-10-30 | Mediatek Inc. | Switching fabric of network device that uses multiple store units and multiple fetch units operated at reduced clock speeds and related method thereof |
| CN103309626A (en) * | 2013-07-03 | 2013-09-18 | 盛科网络（苏州）有限公司 | Method for realizing multi-read-write port memorizer of network chip and corresponding memorizer |
Cited By (17)
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|---|---|---|---|---|
| CN106445831A (en) * | 2015-08-11 | 2017-02-22 | 深圳市中兴微电子技术有限公司 | Storage unit and processing system |
| CN106297861A (en) * | 2016-07-28 | 2017-01-04 | 盛科网络（苏州）有限公司 | The data processing method of extendible multiport memory and data handling system |
| CN106297861B (en) * | 2016-07-28 | 2019-02-22 | 盛科网络（苏州）有限公司 | The data processing method and data processing system of expansible multiport memory |
| CN106302260B (en) * | 2016-07-28 | 2019-08-02 | 盛科网络（苏州）有限公司 | 4 read ports, 4 write ports share the data buffer storage processing method and data processing system of message entirely |
| CN106302260A (en) * | 2016-07-28 | 2017-01-04 | 盛科网络（苏州）有限公司 | 4R4W shares data buffer storage processing method and the data handling system of message entirely |
| US10818325B2 (en) | 2016-07-28 | 2020-10-27 | Centec Networks (Su Zhou) Co., Ltd. | Data processing method and data processing system for scalable multi-port memory |
| WO2019183849A1 (en) * | 2018-03-28 | 2019-10-03 | 深圳市大疆创新科技有限公司 | Data processing method and device |
| CN110337637A (en) * | 2018-03-28 | 2019-10-15 | 深圳市大疆创新科技有限公司 | Data processing method and equipment |
| CN110337637B (en) * | 2018-03-28 | 2021-07-30 | 深圳市大疆创新科技有限公司 | Data processing method and device |
| CN110704369B (en) * | 2019-10-09 | 2023-06-06 | 苏州盛科通信股份有限公司 | Memory and control method thereof |
| CN110704369A (en) * | 2019-10-09 | 2020-01-17 | 盛科网络（苏州）有限公司 | Memory and control method thereof |
| CN111143079A (en) * | 2019-12-24 | 2020-05-12 | 浪潮软件股份有限公司 | Method for realizing multi-read multi-write lock-free queue |
| CN111143079B (en) * | 2019-12-24 | 2024-04-16 | 浪潮软件股份有限公司 | Multi-read multi-write lock-free queue implementation method |
| CN114519023A (en) * | 2022-02-18 | 2022-05-20 | 芯河半导体科技(无锡)有限公司 | Method for realizing multiport Ram |
| CN114519023B (en) * | 2022-02-18 | 2024-04-19 | 芯河半导体科技(无锡)有限公司 | Method for realizing multi-port Ram |
| CN114968861A (en) * | 2022-05-25 | 2022-08-30 | 中国科学院计算技术研究所 | Two-write two-read data transmission structure and on-chip multi-channel interactive network |
| CN114968861B (en) * | 2022-05-25 | 2024-03-08 | 中国科学院计算技术研究所 | Two-write two-read data transmission structure and on-chip multichannel interaction network |
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