CN104465571A - Wafer packaging structure - Google Patents
Wafer packaging structure Download PDFInfo
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- CN104465571A CN104465571A CN201410782466.1A CN201410782466A CN104465571A CN 104465571 A CN104465571 A CN 104465571A CN 201410782466 A CN201410782466 A CN 201410782466A CN 104465571 A CN104465571 A CN 104465571A
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- metal layer
- ball lower
- substrate
- wafer packaging
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05007—Structure comprising a core and a coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a wafer packaging structure which comprises a substrate, a metal kernel, an under bump metal layer and a bump point structure. A conductive metal mat is arranged on the surface of the substrate, the metal kernel is arranged on the substrate and protrudes out of the surface of the substrate, the under bump metal layer wraps the top face and the side face of the metal kernel, and the bump point structure is formed on the surface of the under bump metal layer. The wafer packaging structure has the advantages that the contact face between the bump point structure and the under bump metal layer is added, a part of the metal kernel wrapped by the under bump metal layer extends into the bump point structure, so that combination strength of the bump point structure and the under bump metal layer is improved, the bump point structure and the under bump metal layer are more stable in structure and not prone to falling off, the mechanical stabilization degree of the wafer packaging structure is improved, and heat conductivity and electric conductivity of the wafer packaging structure are enhanced.
Description
Technical field
The present invention relates to field of semiconductor package, be specifically related to a kind of wafer packaging structure.
Background technology
On conventional art, the connection of IC chip and external circuit is realized by the mode of metal lead wire bonding (WireBonding).Along with the expansion with footprint of reducing of IC chip feature sizes, Wire Bonding Technology is no longer applicable.Crystal wafer chip dimension encapsulation (Wafer Level Chip ScalePackaging, WLCSP) technology is that after carrying out packaging and testing to full wafer wafer, cutting obtains the technology of single finished product chip again, the chip size after encapsulation and nude film completely the same.Crystal wafer chip dimension encapsulation technology has thoroughly overturned the pattern of conventional package as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier), organic leadless chip carrier (Organic Leadless Chip Carrier), has complied with that market is day by day light, little, short to microelectronic product, thinning and low priceization requirement.Chip size after the encapsulation of crystal wafer chip dimension encapsulation technology reaches highly microminiaturized, and chip cost significantly reduces along with the reduction of chip size and the increase of wafer size.Crystal wafer chip dimension encapsulation technology be IC can be designed, wafer manufacture, packaging and testing, the technology that integrates, be the focus in current encapsulation field and the trend of future development.
With reference to the structural representation that figure 1 is the wafer packaging structure of crystal wafer chip dimension of the prior art, comprising: Semiconductor substrate 1; Be positioned at the conducting metal pad 11 in described Semiconductor substrate 1, be positioned at the ball lower metal layer 3 on described conducting metal pad 11, be positioned at the bump structure 2 on described ball lower metal layer 3.
But the bump structure 2 of this structure is little with the contact area of ball lower metal layer 3, and the bond strength of whole like this wafer packaging structure is lower, and this can cause the mechanical stability of wafer packaging structure to reduce.Such as, there is bump structure 2 sometimes and depart from situation about even coming off with ball lower metal layer 3 part, while the conductivity performance of whole wafer packaging structure and heat-conductive characteristic also can be affected.
Therefore, how to improve the bond strength between bump structure and ball lower metal layer further, become the technical problem that those skilled in the art are urgently to be resolved hurrily.
Summary of the invention
The problem that the present invention solves is to provide a kind of wafer packaging structure, to improve the bond strength between bump structure and ball lower metal layer as far as possible.
For solving the problem, the invention provides a kind of wafer packaging structure, comprising:
Substrate, described substrate surface has conducting metal pad;
Be positioned at the metal core on conducting metal pad, described metal core protrudes from the surface of described substrate;
Be coated on the end face of described metal core and the ball lower metal layer of side;
Be formed at the bump structure on described ball lower metal layer surface.
Optionally, described substrate surface has passivation layer, and described conducting metal pad exposes from described passivation layer.
Optionally, the material of described passivation layer is silicon nitride, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass.
Optionally, described passivation layer is formed with protective layer, described conducting metal pad exposes from described protective layer.
Optionally, the material of described protective layer is polyimides.
Optionally, described metal core is formed at described conducting metal pad surface, has gap between the sidewall of metal core and described passivation layer and protective layer; Described ball lower metal layer is filled in described gap.
Optionally, the material of described metal core is copper, gold, silver, tin or nickel;
The material of described ball lower metal layer is copper, gold, silver, tin or nickel;
The material of described bump structure is copper, gold, silver, tin or nickel.
Optionally, the material of described metal core is not identical with the material of ball lower metal layer.
Optionally, the material of described ball lower metal layer is not identical with the material of bump structure.
Compared with prior art, technical scheme of the present invention has the following advantages:
Because metal core protrudes from substrate surface, ball lower metal layer is coated on end face and the side of metal core, that is, the metal core being coated with ball lower metal layer also protrudes from the surface of described substrate, which increase the contact-making surface between bump structure and ball lower metal layer, and the part being coated with the metal core of ball lower metal layer stretches into bump structure, which increase the bond strength between bump structure and ball lower metal layer, the structure of bump structure and ball lower metal layer is more stable, not easily come off, and then improve the mechanically stable degree of wafer packaging structure, and enhance heat conductivity and the electrical conductivity of wafer packaging structure.
Accompanying drawing explanation
Fig. 1 is the structural representation of the wafer packaging structure of existing crystal wafer chip dimension;
Fig. 2 is the structural representation of wafer packaging structure one embodiment of the present invention;
The structural representation of each step in Fig. 3 to Fig. 7 wafer packaging structure of the present invention formation method one embodiment.
Embodiment
Inadequate with bond strength between the wafer packaging structure bumps structure of existing crystal wafer chip dimension and ball lower metal layer, this can cause the mechanical stability of whole wafer packaging structure to reduce, such as, cause bump structure to depart from from ball lower metal layer part even to come off.Meanwhile, the conductivity performance of wafer packaging structure and heat-conductive characteristic also can be affected.
Therefore, the invention provides a kind of wafer packaging structure, is the structural representation of wafer packaging structure one embodiment of the present invention with reference to figure 2.In the present embodiment, described wafer packaging structure comprises following structure:
Substrate 101`, described substrate 101` surface has conducting metal pad 102`; Described conducting metal pad 102` is used for the circuit characteristic in substrate 101` being led to substrate 101` surface so that encapsulation.
In the present embodiment, described substrate 101` surface has passivation layer 103`, and described passivation layer 103` is for the protection of substrate 101` surface.
Described conducting metal pad 102` exposes from described passivation layer 103`, passivation layer 103` can be avoided so as far as possible to affect conducting metal pad 102` and be electrically connected with the bump structure 107` of follow-up encapsulation.
Concrete, the material of the passivation layer 103` in the present embodiment can be silicon nitride, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass material.But the material of passivation layer 103` is prior art, and the present invention is not limited in any way this.
In the present embodiment, the thickness of described passivation layer 103` is in the scope of 1 ~ 2 micron.But this is only an example, the thickness of the present invention to described passivation layer 103` is not construed as limiting, but should determine according to actual conditions.
In the present embodiment; described passivation layer 103` is also formed with protective layer 104`; described protective layer 104` can protect the passivation layer 103` on substrate 101` and substrate 101` further; because under normal circumstances; the quality of passivation layer 103` is more crisp (such as; the passivation layer 103` of silicon nitride, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass material in the present embodiment); easy generation is damaged, is conducive to protecting substrate 101` and passivation layer 103` so form layer protective layer 104` on passivation layer 103` again.
Meanwhile, described protective layer 104` can also play the effect on planarization passivation layer 103` surface.Because generally, the thickness of passivation layer 103` is less, and the surface of substrate 101` have sometimes more concavo-convex (such as, some semiconductor device that substrate 101` surface is formed), that is, after covering passivation layer 103`, substrate 101` surface still may be uneven, and this is unfavorable for the formation of ball lower metal layer 106` and bump structure 107`.Therefore, forming protective layer 104` can the surface of planarized substrate 101`, and then facilitates follow-up ball lower metal layer 106` and the formation of bump structure 107`.
Meanwhile, described conducting metal pad 102` is exposed from described protective layer 104`, affect conducting metal pad 102` to avoid protective layer 104` as far as possible and be electrically connected with the bump structure 107` of follow-up encapsulation.
In the present embodiment, the protective layer 104` of polyimide material is formed.This material has good elasticity, and quality is comparatively hard, is conducive to further protecting substrate 101` and passivation layer 103`.
In the present embodiment, the thickness of protective layer 104`, in the scope of 4 ~ 6 microns, is conducive to filling and leading up the substrate 101` surface being coated with passivation layer 103` in this thickness range, is simultaneously unlikely to again blocked up and excessively increases the volume of whole wafer packaging structure.
Wafer packaging structure of the present invention also comprises and is positioned at the surface that metal core 105` on substrate 101` and ball lower metal layer 106`, described metal core 105` protrude from described substrate 101`, described metal core 105` is for increasing the bond strength between bump structure 107` and ball lower metal layer 106`, because described metal core 105` protrudes from substrate 101` surface, the ball lower metal layer 106` of follow-up formation is simultaneously coated on described metal core 105` surface, therefore the contact-making surface between ball lower metal layer 106` and bump structure 107` increases, and ball lower metal layer 106` stretches into bump structure 107` inside, which increase the bond strength between bump structure 107` and ball lower metal layer 106`, the structure of bump structure 107` and ball lower metal layer 106` is more stable, not easily come off, and then improve the mechanically stable degree of wafer packaging structure, and enhance heat conductivity and the electrical conductivity of wafer packaging structure.
Because the 101` of substrate described in the present embodiment surface is formed with protective layer 104`; therefore the surface of described metal core 105` is not less than the surface of described protective layer 104`; the various piece on the ball lower metal layer 106` surface of follow-up like this formation is all unlikely to lower than the surface of protective layer 104` or flushes with the surface of protective layer 104`; but the surface of protective layer 104` can be protruded from, and then reach the above-mentioned ball lower metal layer 106` that makes and stretch into the object of bump structure 107` inside.
In the present embodiment, described metal core 105` is formed at described conducting metal pad 102` surface, has gap between the sidewall of metal core 105` and described passivation layer 103` and protective layer 104`; Described ball lower metal layer 106` is filled in described gap.
In the present embodiment, the material of metal core 105` can be copper, gold, silver, tin or nickel.
Described ball lower metal layer 106` is for defining the position of bump structure 107`.
As mentioned before, ball lower metal layer 106` is coated on end face and the side of metal core 105`, that is, the metal core 105` being coated with ball lower metal layer 106` also protrudes from the surface of described protective layer 104`, which increase the contact-making surface between the bump structure 107` of follow-up formation and ball lower metal layer 106`, and the part being coated with the metal core 105` of ball lower metal layer 106` stretches into bump structure 107`, which increase the bond strength between bump structure 107` and ball lower metal layer 106`, the structure of bump structure 107` and ball lower metal layer 106` is more stable, not easily come off, and then improve the mechanically stable degree of wafer packaging structure, and enhance heat conductivity and the electrical conductivity of wafer packaging structure.
In the present embodiment, the material of ball lower metal layer 106` can be copper, gold, silver, tin or nickel.
In the present embodiment, the material of described ball lower metal layer 106` is different from the material of described metal core 105`, such benefit is, different metal materials contacts, the atom meeting phase counterdiffusion of two kinds of metal materials, and then interface alloy compound layer (IntermetallicCompound altogether can be formed at the contact-making surface of two kinds of metal materials, IMC), be conducive to the bond strength between increase by two kinds of metals Friday further, namely increase the bond strength of ball lower metal layer 106` and metal core 105` further.
Bump structure 107` of the present invention is positioned at described ball lower metal layer 106` surface.
In the present embodiment, described bump structure 107` is spherical male dot structure (namely soldered ball).But the present invention is not construed as limiting this, described bump structure 107` can also be other structures, such as column construction.
In the present embodiment, the material of bump structure 107` is copper, gold, silver, tin or nickel.
Further, in the present embodiment, the material of described ball lower metal layer 106` is not identical with the material of bump structure 107`.The reason different with metal core 105` material from ball lower metal layer 106` is above identical, the material of ball lower metal layer 106` is different from the material of bump structure 107` can form interface alloy compound layer altogether at both contact-making surfaces, and then increases bond strength between the two further.
In addition, the present invention also provides a kind of formation method of wafer packaging structure, in the present embodiment, comprises the following steps:
There is provided substrate, described substrate surface has conducting metal pad; Described conducting metal pad is formed the metal core protruding from substrate surface; At end face and the side coated ball lower metal layer of described metal core; Bump structure is formed on described ball lower metal layer surface.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
With reference to the structural representation of each step in figure 3 to Fig. 7 wafer packaging structure one of the present invention embodiment.
First with reference to figure 3, substrate 101 is provided.Described substrate 101 is in the present embodiment for being formed with the wafer of the semiconductor device such as transistor.
Described substrate 101 surface has conducting metal pad 102, and described conducting metal pad 102 is surperficial for the circuit characteristic in substrate 101 being led to substrate 101, so that follow-up encapsulation.
In the present embodiment, provide the step of substrate 101 to be also included in described substrate 101 surface and be also formed with passivation layer 103, described passivation layer 103 is for the protection of substrate 101 surface.
Described conducting metal pad 102 exposes from described passivation layer 103, passivation layer 103 can be avoided so as far as possible to affect conducting metal pad 102 and be electrically connected with the bump structure of follow-up encapsulation.
Concrete, the material of the passivation layer 103 in the present embodiment can be silicon nitride, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass material.But the material of passivation layer 103 is prior art, and the present invention is not limited in any way this.
In the present embodiment, the thickness of described passivation layer 103 is in the scope of 1 ~ 2 micron.But this is only an example, the thickness of the present invention to described passivation layer 103 is not construed as limiting, but should determine according to actual conditions.
In conjunction with reference to figure 4, in the present embodiment, provide the step of substrate 101 to be also included on described passivation layer 103 and form protective layer 104.Described protective layer 104 can be protected the passivation layer 103 on substrate 101 and substrate 101 further; because under normal circumstances; the quality of passivation layer 103 is more crisp (such as; the passivation layer 103 of silicon nitride, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass material in the present embodiment); easy generation is damaged, so form layer protective layer 104 to be again conducive to protection substrate 101 and passivation layer 103 on passivation layer 103.
Meanwhile, described protective layer 104 can also play the effect on planarization passivation layer 103 surface.Because generally, the thickness of passivation layer 103 is less, and the surface of substrate 101 have sometimes more concavo-convex (such as, some semiconductor device that substrate 101 surface is formed), that is, after covering passivation layer 103, substrate 101 surface still may be uneven, and this is unfavorable for the formation of follow-up ball lower metal layer and bump structure.Therefore, forming protective layer 104 can the surface of planarized substrate 101, and then facilitates follow-up ball lower metal layer and the formation of bump structure.
Meanwhile, described conducting metal pad 102 is exposed from described protective layer 104, affect conducting metal pad 102 to avoid protective layer 104 as far as possible and be electrically connected with the bump structure of follow-up encapsulation.
In the present embodiment, the protective layer 104 of polyimide material is formed.This material has good elasticity, and quality is comparatively hard, is conducive to protection substrate 101 and passivation layer 103 further.
In the present embodiment, forming thickness is the protective layer 104 of 4 ~ 6 microns, is conducive to filling and leading up substrate 101 surface being coated with passivation layer 103 in this thickness range, is unlikely to again blocked up simultaneously and excessively increases the volume of whole wafer packaging structure.
After this, with reference to figure 5, described conducting metal pad 102 forms the metal core 105 protruding from substrate 101 surface, described metal core 105 is for increasing the bond strength between the bump structure of follow-up formation and ball lower metal layer, because described metal core 105 protrudes from substrate 101 surface, the ball lower metal layer of follow-up formation is simultaneously coated on described metal core 105 surface, therefore the contact-making surface between ball lower metal layer and bump structure increases, and ball lower metal layer stretches into bump structure inside, which increase the bond strength between bump structure and ball lower metal layer, the structure of bump structure and ball lower metal layer is more stable, not easily come off, and then improve the mechanically stable degree of wafer packaging structure, and enhance heat conductivity and the electrical conductivity of wafer packaging structure.
Due in the present embodiment; protective layer 104 is formed on described substrate 101 surface; so in the present embodiment; the surface of described metal core 105 should be made to be not less than the surface of described protective layer 104; the various piece on the ball lower metal layer surface of follow-up like this formation is all unlikely to lower than the surface of protective layer 104 or flushes with the surface of protective layer 104; but the surface of protective layer 104 can be protruded from, and then reach the above-mentioned ball lower metal layer that makes and stretch into the object of bump structure inside.
Concrete, in the present embodiment, form described metal core 105 in the following ways:
Described substrate 101 forms plating seed layer; Concrete, the mode of sputtering sedimentation can be adopted to form described plating seed layer, but the present invention is not construed as limiting to this.
Described plating seed layer forms photoresist layer; Described photoresist layer is used for blocking corresponding to the plating inculating crystal layer not needing to be formed metal core 105 part.
Removal unit divides photoresist to expose the plating seed layer corresponding to conducting metal pad 102 position;
Substrate 101 surface is electroplated, to form described metal core 105 on the described plating seed layer corresponding to conducting metal pad 102 position;
After this, photoresist layer is removed.
In the present embodiment, the metal core 105 of copper, gold, silver, tin or nickel material can be formed.
With reference to figure 6, after the described metal core 105 of formation, at end face and the side coated ball lower metal layer 106 of described metal core 105; Described ball lower metal layer 106 is for defining the position of the bump structure of follow-up formation.
As mentioned before, ball lower metal layer 106 is coated on end face and the side of metal core 105, that is, the metal core 105 being coated with ball lower metal layer 106 also protrudes from the surface of described protective layer 104, which increase the contact-making surface between the bump structure of follow-up formation and ball lower metal layer 106, and the part being coated with the metal core 105 of ball lower metal layer 106 stretches into bump structure, which increase the bond strength between bump structure and ball lower metal layer 106, the structure of bump structure and ball lower metal layer 106 is more stable, not easily come off, and then improve the mechanically stable degree of wafer packaging structure, and enhance heat conductivity and the electrical conductivity of wafer packaging structure.
In the present embodiment, described ball lower metal layer 106 can be formed by the mode of plating.
In the present embodiment, the ball lower metal layer 106 of copper, gold, silver, tin or nickel material is formed.
Further, in the present embodiment, make the material of the ball lower metal layer 106 of formation different from the material of described metal core 105, such benefit is, different metal materials contacts, the atom meeting phase counterdiffusion of two kinds of metal materials, and then interface alloy compound layer (Intermetallic Compound altogether can be formed at the contact-making surface of two kinds of metal materials, IMC), be conducive to the bond strength between increase by two kinds of metals Friday further, namely increase the bond strength of ball lower metal layer 106 and metal core 105 further.
With reference to figure 7, after formation ball lower metal layer 106, form bump structure 107 on described ball lower metal layer 106 surface.
In the present embodiment, described bump structure 107 is spherical male dot structure (namely soldered ball).But the present invention is not construed as limiting this, described bump structure 107 can also be other structures, such as column construction.
In the present embodiment, the bump structure 107 of copper, gold, silver, tin or nickel material is formed.
Make the material of ball lower metal layer 106 not identical with the material of bump structure 107 in the present embodiment.The reason different with metal core 105 material from ball lower metal layer 106 is above identical, the material of ball lower metal layer 106 is different from the material of bump structure 107 can form interface alloy compound layer altogether at both contact-making surfaces, and then increases bond strength between the two further.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (9)
1. a wafer packaging structure, is characterized in that, comprising:
Substrate, described substrate surface has conducting metal pad;
Be positioned at the metal core on conducting metal pad, described metal core protrudes from the surface of described substrate;
Be coated on the end face of described metal core and the ball lower metal layer of side;
Be formed at the bump structure on described ball lower metal layer surface.
2. wafer packaging structure as claimed in claim 1, it is characterized in that, described substrate surface has passivation layer, and described conducting metal pad exposes from described passivation layer.
3. wafer packaging structure as claimed in claim 2, it is characterized in that, the material of described passivation layer is silicon nitride, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass.
4. wafer packaging structure as claimed in claim 2, it is characterized in that, described passivation layer is formed with protective layer, described conducting metal pad exposes from described protective layer.
5. wafer packaging structure as claimed in claim 4, it is characterized in that, the material of described protective layer is polyimides.
6. wafer packaging structure as claimed in claim 4, is characterized in that, described metal core is formed at described conducting metal pad surface, has gap between the sidewall of metal core and described passivation layer and protective layer; Described ball lower metal layer is filled in described gap.
7. wafer packaging structure as claimed in claim 1, it is characterized in that, the material of described metal core is copper, gold, silver, tin or nickel;
The material of described ball lower metal layer is copper, gold, silver, tin or nickel;
The material of described bump structure is copper, gold, silver, tin or nickel.
8. the wafer packaging structure as described in claim 1 or 7, is characterized in that, the material of described metal core is not identical with the material of ball lower metal layer.
9. the wafer packaging structure as described in claim 1 or 7, is characterized in that, the material of described ball lower metal layer is not identical with the material of bump structure.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410782466.1A CN104465571A (en) | 2014-12-16 | 2014-12-16 | Wafer packaging structure |
| US14/971,495 US9666550B2 (en) | 2014-12-16 | 2015-12-16 | Method and structure for wafer-level packaging |
| US15/456,350 US9922950B2 (en) | 2014-12-16 | 2017-03-10 | Method and structure for wafer-level packaging |
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| CN201410782466.1A CN104465571A (en) | 2014-12-16 | 2014-12-16 | Wafer packaging structure |
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| CN104465571A true CN104465571A (en) | 2015-03-25 |
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| CN201681828U (en) * | 2010-05-17 | 2010-12-22 | 茂邦电子有限公司 | Wafer bump structure |
| CN102915978A (en) * | 2012-11-08 | 2013-02-06 | 南通富士通微电子股份有限公司 | Semiconductor packaging structure |
| CN102915986A (en) * | 2012-11-08 | 2013-02-06 | 南通富士通微电子股份有限公司 | Chip packaging structure |
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| CN202917474U (en) * | 2012-11-08 | 2013-05-01 | 南通富士通微电子股份有限公司 | Semiconductor package structure |
| CN103474402A (en) * | 2013-09-29 | 2013-12-25 | 南通富士通微电子股份有限公司 | Semiconductor package structure |
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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
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