CN102931164A - Packaging element of semiconductor device - Google Patents
Packaging element of semiconductor device Download PDFInfo
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- CN102931164A CN102931164A CN2012104455628A CN201210445562A CN102931164A CN 102931164 A CN102931164 A CN 102931164A CN 2012104455628 A CN2012104455628 A CN 2012104455628A CN 201210445562 A CN201210445562 A CN 201210445562A CN 102931164 A CN102931164 A CN 102931164A
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- salient point
- semiconductor device
- soldered ball
- pad
- barrier layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Discloses is a packaging element of a semiconductor device. The packaging element comprises a chip, a passivation layer, salient points and solder balls. Pads and integrated circuits are arranged on the surface of the chip and electrically connected; the passivation layer is placed on the surface of the chip and provided with openings which expose part of the pads; the salient points are arranged on the surfaces of the pads, and the sizes of the salient points are smaller than those of the openings; and the solder balls cover the tops and side walls of the salient points and the bottoms of the openings. The packaging element of the semiconductor device is not easy to short circuit, high in bonding strength between the solder balls and the salient points and stable in performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of packaging part of semiconductor device.
Background technology
Encapsulation refers to pack into the technical process of protecting sheathing of device or circuit.Encapsulation is vital for semiconductor chip, because semiconductor chip must be isolated from the outside, to prevent that airborne impurity to the circuit corrosion of semiconductor chip, causing electric property to descend.And the semiconductor chip after the encapsulation also is beneficial to be installed and transports.
The method for packing of the semiconductor device of prior art comprises:
Please refer to Fig. 1, chip 100 is provided, described chip 100 surfaces are formed with integrated circuit and are electrically connected the pad 101 of integrated circuit;
Please refer to Fig. 2, form the passivation layer 103 that is positioned at described chip 100 surfaces, described passivation layer 103 has the opening 105 that exposes pad 101;
Please refer to Fig. 3, shown in Figure 2 by described opening 105() soldered ball 107 formed on pad 101 surfaces.
Yet short circuit phenomenon easily appears in the unstable properties of the packaging part of the semiconductor device that prior art forms.
More method for packing about semiconductor device please refer to publication number and are the Chinese patent of " CN101154640A ".
Summary of the invention
The problem that the present invention solves provides a kind of packaging part of semiconductor device, and the packaging part stable performance of described semiconductor device is difficult for short circuit.
For addressing the above problem, the invention provides a kind of packaging part of semiconductor device, comprising:
Chip, described chip surface has pad;
Be positioned at the passivation layer of described chip surface, described passivation layer has opening, and described opening exposes the part pad;
Be positioned at the salient point of described bond pad surface, the size of described salient point is less than the size of described opening;
Cover the soldered ball of described bump surface and covering open bottom bond pad surface.
Compared with prior art, technical scheme of the present invention has the following advantages:
On the one hand, described soldered ball is formed on the salient point, is subjected to gravity, infiltration power and capillary the impact, and the gap between adjacent solder balls increases, and the packaging part of semiconductor device is not prone to short circuit phenomenon, and device performance is stable; On the other hand, because the size of salient point is less than the size of opening, described soldered ball not only covers the top of salient point, also covers the sidewall of salient point, and open bottom.The structure of train of dress shape is formed on the bottom of described soldered ball, has effectively increased the contact area between soldered ball and salient point, thereby has increased both adhesions, so that the bond strength of soldered ball increases, has improved packaging part performance and the yield of semiconductor device.
Further, also comprise: cover the barrier layer of top, sidewall and the open bottom of described salient point, and the soakage layer that covers described barrier layer.Described barrier layer has effectively stoped the altogether generation of compound of interface alloy, and described soakage layer has effectively stoped the oxidation of barrier layer, and has improved the bond strength between soldered ball and barrier layer, has further improved performance and the yield of the packaging part of semiconductor device.
Description of drawings
Fig. 1-Fig. 3 is the cross-sectional view of encapsulation process of the semiconductor device of prior art;
Fig. 4 is the schematic flow sheet of method for packing of the semiconductor device of first embodiment of the invention;
Fig. 5-Fig. 7 is the cross-sectional view of encapsulation process of the semiconductor device of first embodiment of the invention;
Fig. 8 is the schematic flow sheet of method for packing of the semiconductor device of second embodiment of the invention;
Fig. 9-Figure 12 is the cross-sectional view of encapsulation process of the semiconductor device of second embodiment of the invention;
Figure 13 is the schematic flow sheet of method for packing of the semiconductor device of third embodiment of the invention;
Figure 14-Figure 16 is the cross-sectional view of encapsulation process of the semiconductor device of third embodiment of the invention;
Figure 17 is the schematic flow sheet of method for packing of the semiconductor device of fourth embodiment of the invention;
Figure 18-Figure 20 is the cross-sectional view of encapsulation process of the semiconductor device of fourth embodiment of the invention.
Embodiment
Just as stated in the Background Art, the phenomenon of short circuit easily appears in the unstable properties of the packaging part of the semiconductor device that prior art forms.
Through research, the inventor finds, prior art directly forms soldered ball in bond pad surface, usually the soldered ball that forms is hemisphere, the diameter of described soldered ball is larger, cause the gap between the adjacent solder balls less, short circuit very easily occurs between the less soldered ball in described gap, affect the stability of the packaging part of semiconductor device.
After further research, the inventor finds, at first form salient point in described bond pad surface, then when described bump surface forms soldered ball, be subject to gravity, infiltration power and capillary impact, the tin that forms soldered ball flows downward along the salient point sidewall, described soldered ball by hemisphere to spherical transition, the diameter of the soldered ball that the scolding tin of equal in quality forms is little than prior art, helps to increase the gap between the adjacent solder balls.Yet if described soldered ball only covers the top of described salient point, both adhesions may be not, and soldered ball very easily is kicked off when testing follow-up playing football, and affects the yield of the packaging part of semiconductor device.
Further, the inventor finds, covers top and the sidewall of salient point when described soldered ball, and during the pad of cover part, the contact area between soldered ball and salient point increases, and both adhesions increase; And also have soldered ball cover part pad, further increased the adhesion between soldered ball and salient point, pad, the yield of packaging part that can the Effective Raise semiconductor device.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing each embodiment of the present invention is described in detail.
The first embodiment
Please refer to Fig. 4, the method for packing of the semiconductor device of first embodiment of the invention comprises:
Step S201, the chip that provides the surface to have pad, described chip surface is formed with passivation layer, and described passivation layer has the opening that exposes the part bond pad surface;
Step S202 forms the salient point that is positioned at bond pad surface in described opening, the size of described salient point is less than the size of described opening;
Step S203 forms the soldered ball that covers described bump surface and cover the open bottom bond pad surface.
Concrete, please refer to Fig. 5-Fig. 8, Fig. 5-Fig. 8 shows the cross-sectional view of encapsulation process of the semiconductor device of first embodiment of the invention.
Please refer to Fig. 5, the chip 300 that provides the surface to have pad 301, described chip 300 surfaces are formed with passivation layer 303, and described passivation layer 303 has the opening 305 that exposes part pad 301.
Described chip 300 is used to follow-up packaging technology that workbench is provided.Described chip 300 surfaces also have the integrated circuit that is electrically connected with pad 301, and described integrated circuit designs for satisfying different functional requirements, and described integrated circuit is extremely extraneous with electric signal transmission by the pad 301 that is electrically connected with it.Described integrated circuit and pad 301 form after by the interconnection metal layer etching that is deposited on chip 300 surfaces.In an embodiment of the present invention, described integrated circuit and pad 301 form in same processing step, and the material of described integrated circuit and pad 301 is the metal materials such as gold, silver, copper.Be well known to those skilled in the art owing to forming the technique of integrated circuit and pad 301, do not repeat them here.
Need to prove, in an embodiment of the present invention, the wettability of these three kinds of materials of gold, silver and copper and tin or ashbury metal spare is better, when the material of described pad 301 is gold, silver or copper, soldered ball more easily covers pad 301 surfaces in the subsequent technique, and the infiltration binding ability of soldered ball is better.
The material of described passivation layer 303 is silica, silicon nitride etc., be used for the isolation integrated circuit, and protection pad 301 is impaired or oxidized in subsequent technique.The formation technique of described passivation layer 303 is depositing operation, for example chemical vapor deposition method.Be well known to those skilled in the art owing to forming the technique of passivation layer 303, do not repeat them here.
Have opening 305 in the described passivation layer 303, described opening 305 exposes pad 301 surfaces, is used to follow-uply to form salient points on pad 301 surface process window is provided.The formation technique of described opening 305 is etching technics, for example anisotropic dry etch process.In an embodiment of the present invention, the size of described pad 301 is greater than the size of described opening 305.
Please refer to Fig. 6, form the salient point 307 that is positioned at described pad 301 surfaces by described opening 305, the size of described salient point 307 is less than the size of described opening 305.
The inventor finds, prior art is directly shown in Figure 3 at pad 101() 107(is shown in Figure 3 for surface formation soldered ball), the diameter of the soldered ball 107 that usually forms is larger, cause the gap between the adjacent solder balls 107 less, short circuit very easily occurs between the less soldered ball 107 in described gap, affect the stability of semiconductor device.
After further research, the inventor finds, at first forms salient point 307 on described pad 301 surfaces, when then forming soldered ball on described salient point 307 surfaces, is positioned at the small volume of the soldered ball on described salient point 307 surfaces, helps to increase the gap between the adjacent solder balls.
The material of described salient point 307 is copper, gold, silver, copper alloy, silver alloy or the billon etc. of good heat conductivity, and follow-up described salient point 307 surfaces are used to form the less soldered ball of diameter.In an embodiment of the present invention, the material of described salient point 307 is copper, and cost is lower, and conductivity is better, the better quality of the salient point 307 of formation.
The formation technique of described salient point 307 is lead key closing process, for example thermocompression bonding, supersonic bonding or hot ultrasonic bonding.Because the original interface place that the salient point 307 that lead key closing process forms and pad are 301 is almost near atomic scope, two kinds of metallic atoms spread, both combinations more firm.In the embodiments of the invention, adopt the technique of hot ultrasonic bonding to form salient point 307, strengthened active force between the phase counterdiffusion of the original interface of intermetallic and molecule (atom), being diffused on the whole interface of metal carried out, realize the high-quality welding of salient point 307, the salient point 307 that forms is more firm with pad 301 combinations, and it is simple to form technique.And, oxidized in lead key closing process for preventing as the copper wire that forms salient point 307, during described lead key closing process, also comprise: pass into volume fraction and be 95% nitrogen and volume fraction and be 5% hydrogen.
The chopper that adopts in the described lead key closing process is wedge shape or sphere.The salient point 307 of considering formation is column, and in an embodiment of the present invention, described chopper is spherical, is more conducive to the pillared salient point 307 of shape.
Need to prove, of the present invention and in other examples, described salient point 307 can also adopt electroplating technology, perhaps adopt depositing operation and etching technics to form, to form accurate in size salient point 307, do not repeat them here.
The size W of described salient point 307
1Size W less than described opening 305
2, be used for top and sidewall that follow-up formation covers described salient point 307, and the soldered ball of opening 305 bottom land 301, to increase the adhesion of soldered ball and salient point 307, pad 301, improve the intensity of soldered ball.
Need to prove, the cross sectional shape along the chip surface direction of described salient point 307 is circular, oval, square or triangle, the size W of said salient point 307 in the present embodiment
1And the size W of opening 305
2, refer to the length that is parallel to chip 300 surface direction shown in Fig. 7.
Please refer to Fig. 7, form the soldered ball 311 that covers described salient point 307 surfaces and cover opening 305 bottom land 301 surfaces.
The material of described soldered ball 311 is tin or ashbury metal.The formation technique of described soldered ball 311 perhaps is typography and solder reflow process for planting ball technique and solder reflow process.Because the size W of salient point 307
1Size W less than opening 305
2, during reflux technique, the tin of melting is subjected to capillary effect, is shrunk to chondritic, and is distributed in metal material surface, namely covers the pad 301 of opening 305 bottoms, forms skirt structure (ankor shape) in described opening 305 bottoms.
In the embodiments of the invention, described soldered ball 311 covers salient point 307 surfaces (comprising top surface and side surface) and covers pad 301 surfaces of opening 305 bottoms, soldered ball 311 increases with the contact-making surface of salient point 307, opening 305 bottom land 301, its horizontal and vertical stretching resistance is larger, has increased the bond strength of soldered ball 311.The diameter of the soldered ball 311 that forms further reduces, and has increased the gap between the adjacent solder balls 311, has further improved the stability of the packaging part of semiconductor device.
In the first embodiment of the present invention, adopt lead key closing process to form salient point 307, form technique simple, and combination more firm between salient point 307 and the pad 301.And, because the size W of salient point 307
1Size W less than opening 305
2During follow-up formation soldered ball 311, be subjected to gravity and capillary effect, described soldered ball 311 covers the pad 301 of top, sidewall and opening 305 bottoms of salient point 307, and soldered ball 311 increases with the contact-making surface of salient point 307, pad 301, has increased the bond strength of soldered ball 311, and, the diameter of the soldered ball 311 that forms is little, increased the gap of 311 of adjacent solder balls, further improved the stability of the packaging part of semiconductor device.
Accordingly, please continue with reference to figure 7, the packaging part of the semiconductor device that forms in the first embodiment of the invention comprises: chip 300, and described chip surface has pad 301; Be positioned at the passivation layer 303 of described chip surface, described passivation layer 303 has opening 305, and described opening 305 exposes part pad 301; Be positioned at the salient point 307 on described pad 301 surfaces, the size of described salient point 307 is less than the size of described opening 305; Cover soldered ball 311 surfaces of described salient point 307 surfaces and covering opening 305 bottoms.
Wherein, the size of described pad 301 is greater than the size of described opening 305, and the material of described pad 301 is gold, silver or copper etc.; The material of described salient point 307 is copper, gold, silver, copper alloy, billon or the silver alloy etc. of good heat conductivity, and in the embodiments of the invention, the material of described salient point 307 is copper, and cost is low, and quality is good; The material of described soldered ball 311 is tin or ashbury metal, and the gap that adjacent solder balls is 311 is little.
In the first embodiment of the invention, the material of described salient point 307 is copper, and cost is low, and the conductivity of copper is better, and the quality that salient point is 307 layers is good.Described soldered ball 311 not only covers the surface at the top of salient point 307, also covers side surface and opening 305 bottom land 301 surfaces of salient point 307, the diameter of soldered ball 311 is little, has increased the gap of 311 of adjacent solder balls.And the contact area of soldered ball 311 is larger, and its horizontal and vertical stretching resistance is larger, has improved the bond strength of soldered ball 311, and soldered ball 311 is incrust, has further increased the stability of the packaging part of semiconductor device.
The second embodiment
Different from the first embodiment of the present invention, in the second embodiment of the present invention, the top surface of described salient point and side surface also are formed with barrier layer, to prevent the mutually counterdiffusion of tin atom generation in copper atom and the soldered ball in the salient point, affect the bond strength of soldered ball.And described barrier layer surface also is coated with soakage layer, to improve the adhesion between barrier layer and soldered ball.
Please refer to Fig. 8, in the second embodiment of the invention, the method for packing of described semiconductor device comprises:
Step S401 provides the surface to have the pad chip, and described chip surface is formed with passivation layer, and described passivation layer has the opening that exposes the part bond pad surface;
Step S402 forms the salient point that is positioned at bond pad surface in described opening, the size of described salient point is less than the size of described opening;
Step S403 forms the barrier layer that covers described bump surface;
Step S404 forms the soakage layer that covers described barrier layer;
Step S405 forms the soldered ball that covers described soakage layer and cover described open bottom bond pad surface.
Concrete, please refer to Fig. 9-Figure 12, Fig. 9-Figure 12 shows the cross-sectional view of encapsulation process of the semiconductor device of second embodiment of the invention.
Please refer to Fig. 9, the chip 500 that provides the surface to have pad 501, described chip 500 surfaces are formed with passivation layer 503, and described passivation layer 503 has the opening 505 that exposes part pad 501 surfaces; Be positioned at the salient point 507 on pad 501 surfaces in described opening 505 interior formation, the size of described salient point 507 is less than the size of described opening 505.
Wherein, the material of described salient point 507 is copper, to reduce cost, improves the quality of salient point 507.
Please refer to Figure 10, form the top that covers described salient point 507, the barrier layer 513 of sidewall.
The inventor finds, when the material of described salient point 507 is copper, when the material of described soldered ball is tin or ashbury metal, if directly form soldered ball on salient point 507 surfaces, easily spread between copper atom in the salient point 507 and the tin atom in the soldered ball, form tin copper interface alloy altogether compound and cavity, described tin copper interface alloy altogether compound enbrittles, and has reduced the bond strength between soldered ball and the salient point 507.Therefore, in the embodiments of the invention, also comprise: form the top of the described salient point 507 of covering and the barrier layer 513 of sidewall, be used for stoping the mutually counterdiffusion of copper atom and tin atom.
The material of described barrier layer 513 is nickel, the mutually counterdiffusion of tin atom generation in the copper atom that is used for preventing salient point 507 and the soldered ball.And for effectively stoping the mutually counterdiffusion of tin atom generation in copper atom and the soldered ball in the salient point 507, the thickness of described barrier layer 513 is 0.05 micron-10 microns, preferably, is 0.5 micron-5 microns.In an embodiment of the present invention, the material of described barrier layer 513 is nickel tin, and the thickness of described barrier layer 513 is 1 micron-3 microns, for example 3 microns, both prevented preferably the mutually counterdiffusion of copper atom and tin atom, and satisfy again the requirement of Highgrade integration.
In the embodiments of the invention, the formation step of described barrier layer 513 comprises: form the top of covering described passivation layer 503, pad 501 and salient point 507 and the non-proliferation film (not shown) of sidewall; Form the first mask layer (not shown), described the first mask layer only covers the top of salient point 507 and the non-proliferation film of sidewall; Take described the first mask layer as mask, the described non-proliferation film of etching is until expose pad 501 and passivation layer 503; Behind the described non-proliferation film of etching, remove described the first mask layer.
Need to prove, in other examples of the present invention, can also adopt other deposition, etching technics to form barrier layer 513, as long as can reach top and sidewall that barrier layer 513 covers salient point 507, do not repeat them here.
Please refer to Figure 11, form the soakage layer 515 that covers described barrier layer 513.
Inventor's discovery, the nickel in the above-mentioned barrier layer 513 is very easily oxidized, and the adhesion between barrier layer 513 and the soldered ball is comparatively limited, and the intensity of the soldered ball of follow-up formation is also comparatively limited, is difficult for the detection by the experiment of playing football.Therefore, the inventor finds, can by the associativity of described barrier layer 513 surface coverage and barrier layer 513 and soldered ball all preferably soakage layer 515 effectively increased the binding ability of 507 of soldered ball and salient points as transition.And, after forming barrier layer 513, form immediately described soakage layer 515, form the 513 rear time intervals between formation soakage layer 515 of barrier layer less than 3 minutes, can also more effectively prevent the oxidation of barrier layer 513, further improve the performance of the packaging part of semiconductor device.
At least comprise tin element, gold element or silver element in the material of described soakage layer 515, the thickness of described soakage layer 515 is 0.05 micron-3 microns, to improve the adhesion of itself and barrier layer 513, soldered ball.In an embodiment of the present invention, the material of described soakage layer 515 is tin, and its thickness is 1 micron, and described soakage layer 515 is follow-up and with can be better in conjunction with infiltrating between the soldered ball of material.
The formation step of described soakage layer 515 comprises: form the seed thin film (not shown) that covers described barrier layer 513, passivation layer 503 and pad 501; Form the second mask layer (not shown), described the second mask layer only covers the seed thin film on barrier layer 513 surfaces; Take described the second mask layer as mask, the described seed thin film of etching is until expose pad 501 and passivation layer 503; After the described seed thin film of etching, remove described the second mask layer.
In an embodiment of the present invention, described the first mask layer and the second mask are same mask layer, and the described non-proliferation film of etching and seed thin film form in same processing step, have effectively saved processing step.
Need to prove, in other examples of the present invention, can also adopt other deposition, etching technics to form soakage layer 515, cover barrier layer 513 as long as can reach soakage layer 515, do not repeat them here.
Need to prove, in other embodiments of the invention, can also not form soakage layer 515, directly form soldered ball on barrier layer 513 surfaces and opening 505 bottoms, do not repeat them here.
Please refer to Figure 12, form the soldered ball 511 that covers described soakage layer 515 and cover described opening 505 bottoms.
In the second embodiment of the present invention, described soldered ball 511 covers salient point 507 surfaces and covers pad 501 surfaces, and forming the bottom is the structure of train of dress shape.Described soldered ball 511 contacts with pad 501, and soldered ball 511 increases with the contact area of salient point 507, pad 501, and the adhesion grow that soldered ball 511 and pad are 501 is conducive to improve the intensity of soldered ball 511.
The formation technique of described soldered ball 511 please refer to the associated description of first embodiment of the invention, does not repeat them here.
After above-mentioned steps is finished, the completing of the semiconductor device of second embodiment of the invention.The advantage in having first embodiment of the invention, because before forming soldered ball 511, form barrier layer 513 and soakage layer 515 on described salient point 507 surfaces, effectively prevented the mutually counterdiffusion of copper in tin and the salient point 507 in the soldered ball 511, improved the intensity of soldered ball 511, the stability of the packaging part of the semiconductor device of formation is further enhanced.
Accordingly, please continue with reference to Figure 12, the inventor also provides a kind of packaging part of semiconductor device, comprising: chip 500, and described chip surface has pad 501; Be positioned at the passivation layer 503 on described chip 500 surfaces, described passivation layer 503 has opening 505, and described opening 505 exposes part pad 501; Be positioned at the salient point 507 on described pad 501 surfaces, the size of described salient point 507 is less than the size of described opening 505; Cover the barrier layer 513 on described salient point 507 surfaces; Cover the soakage layer 515 of described barrier layer 513; Cover the soldered ball 511 of described soakage layer 515 and opening 505 bottoms.
Wherein, the material of described barrier layer 513 is nickel, the mutually counterdiffusion of tin atom generation in the copper atom that is used for preventing salient point 507 and the soldered ball; The thickness of described barrier layer 513 is 0.05 micron-10 microns, and is better, is 0.5 micron-5 microns.In the second embodiment of the invention, the material of described barrier layer 513 is nickel, and its thickness is 1 micron-3 microns.
At least comprise tin element, gold element or silver element in the material of described soakage layer 515, be used for preventing the oxidation of barrier layer 513, and improve the adhesion of itself and barrier layer 513, soldered ball.The thickness of described soakage layer 515 is 0.05 micron-3 microns.In the second embodiment of the present invention, the material of described soakage layer 515 is tin, and the thickness of described soakage layer 515 is 1 micron.
The associated description of more packaging parts about semiconductor device in the second embodiment of the invention please refer to the description of method part among first embodiment of the invention and the second embodiment, does not repeat them here.
The 3rd embodiment
Slightly different from the second embodiment of the present invention, barrier layer not only covers the surface of salient point, also covers the bond pad surface in the opening, forms skirt structure, so that soldered ball more easily covers bond pad surface when forming soldered ball, with the intensity of further raising soldered ball.
Please refer to Figure 13, the method for packing of the semiconductor device of third embodiment of the invention comprises:
Step S601, the chip that provides the surface to have pad, described chip surface is formed with passivation layer, and described passivation layer has the opening that exposes the part bond pad surface;
Step S602 forms the salient point that is positioned at bond pad surface in described opening, the size of described salient point is less than the size of described opening;
Step S603 forms the barrier layer that covers described bump surface and cover the open bottom bond pad surface;
Step S604 forms the soakage layer that covers described barrier layer;
Step S605 forms the soldered ball that covers described soakage layer.
Concrete, please refer to Figure 14-Figure 16, Figure 14-Figure 16 shows the cross-sectional view of encapsulation process of the semiconductor device of third embodiment of the invention.
Please refer to Figure 14, the chip 700 that provides the surface to have pad 701, described chip 700 surfaces are formed with passivation layer 703, and described passivation layer 703 has the opening 705 that exposes part pad 701 surfaces; Be positioned at the salient point 707 on described pad 701 surfaces in described opening 705 interior formation, the size of described salient point 707 is less than the size of described opening 705.
The material of described pad 701 is aluminium, gold, silver or copper, and the infiltration associativity between these several metals and the nickel alloy is better, and during the barrier layer 713 of follow-up formation nickel alloy, described barrier layer 713 more easily covers whole pad 701 surfaces.
Please continue with reference to Figure 14, form the barrier layer 713 that covers described salient point 707 surfaces and cover opening 705 bottom land 701 surfaces.
Inventor's discovery, also there are diffusion phenomena in the metallic atom that the tin in the follow-up soldered ball and pad are 701.Therefore, different from the second embodiment, described barrier layer 713 also covers pad 701 surfaces except the top and sidewall that cover salient point 707, to prevent tin and the diffusion of the metallic atom in the pad 701 in the soldered ball, forms altogether compound of interface alloy.Further improved the intensity of soldered ball.
Described barrier layer 713 materials are nickel, what its formation technique was better is that chemical plating process is (when chemical plating forms barrier layer 713, the nickel film is both to have covered salient point 707 surfaces, cover again pad 701), chemical technology is simple, and be difficult for short circuit, the good stability of the packaging part of the semiconductor device of formation.
Please refer to Figure 15, form the soakage layer 715 that covers described barrier layer 713.
At least comprise tin element, gold element or silver element in the material of described soakage layer 715, the thickness of described soakage layer 715 is 0.05 micron-3 microns, to improve the adhesion of itself and barrier layer 713, soldered ball.In an embodiment of the present invention, the material of described soakage layer 715 is tin, and its thickness is 1 micron.
Similarly, be the saving processing step, and prevent that 707 of each salient points are short-circuited, the formation technique of described soakage layer 715 is identical with the formation technique of described diffusion layer 713, is chemical plating process.
Need to prove, in other embodiments of the invention, before forming soakage layer 715, can also form other functional layers on described barrier layer 713 surfaces, do not repeat them here.
Please refer to Figure 16, form the soldered ball 711 that covers described soakage layer 715.Described soldered ball 711 covers described soakage layer 715, because described soakage layer 715 covers the surface (top surface and side surface) of salient point 707, therefore, described soldered ball 711 covers top and the sidewall of described salient point 707, and forming bottom shape is the train of dress shape.In the embodiments of the invention, because the existence of soakage layer 715, the soldered ball 711 that forms more easily covers pad 701 surfaces, soldered ball 711 increases with the contact area of soakage layer 715, pad 701, effectively increase the adhesion of 701 of soldered ball 711 and soakage layer 715, pads, improved the intensity of soldered ball 711.
The method for packing of how described soldered ball 711 and step please refer to the associated description in the second embodiment of the invention, do not repeat them here.
After above-mentioned steps is finished, the completing of the semiconductor device of third embodiment of the invention.Adopt the technique of chemical plating to form the top of covering salient point 707 and the barrier layer 713 of sidewall and pad 701, the semiconductor device of formation is difficult for short circuit, good stability, and it is simple to form technique.After forming barrier layer 713, form successively the soakage layer 715 that covers barrier layer 713, cover the soldered ball 711 of described soakage layer 715.Avoid the diffusion between metallic atom in tin in the soldered ball 711 and the pad 701, further improved the intensity of soldered ball 711.
Accordingly, please continue with reference to Figure 16, the inventor also provides a kind of packaging part of semiconductor device, comprising: chip 700, and described chip surface has pad 701; Be positioned at the passivation layer 703 on described chip 700 surfaces, described passivation layer 703 has opening 705, and described opening 705 exposes part pad 701; Be positioned at the salient point 707 on described pad 701 surfaces, the size of described salient point 707 is less than the size of described opening 705; Cover the barrier layer 713 on pad 701 surfaces of described salient point 707 surfaces and covering opening 705 bottoms; Cover the soakage layer 715 of described barrier layer 713; Cover the soldered ball 711 on described soakage layer 715 surfaces.
Wherein, described barrier layer 713 not only covers top and the sidewall of salient point 707, also cover pad 701 surfaces, therefore, described barrier layer 713 can effectively prevent copper atom in tin atom and the salient point 707 in the soldered ball 711 and the metallic atom phase counterdiffusion in the pad 701, and the intensity of soldered ball 701 further strengthens.
Described soakage layer 715 covers described barrier layer 713 surfaces, and namely described soakage layer 715 covers top and sidewall and pad 701 surfaces of salient point 707, effectively stops the oxidation of barrier layer 713, and strengthens the intensity of soldered ball 711.
Described soldered ball 711 covers soakage layer 715 surfaces, namely covers top and sidewall and pad 701 surfaces of described salient point 707.Be subjected to gravity and capillary effect, described soldered ball 711 is spherical, and described soldered ball 711 bottoms are the train of dress shape, and its intensity is high, the good stability of the packaging part of corresponding semiconductor device.
More about the associated description in the third embodiment of the invention, please refer to the present invention first or the second embodiment, do not repeat them here.
Different from the semiconductor device of the second embodiment, except the advantage with first, second embodiment of the present invention, the barrier layer of semiconductor device also covers bond pad surface, effectively stop the metallic atom phase counterdiffusion in tin and the pad in the soldered ball, the conjugation of soldered ball and pad is good, the intensity of soldered ball is large, the stable performance of semiconductor device.
The 4th embodiment
Different from previous embodiment, demand for high density product is considered, in the fourth embodiment of the present invention, salient point is by repeatedly bonding technology formation, the salient point that forms is the multiple-level stack structure, and consistent for guaranteeing the final a plurality of bump height that form, have preferably coplanarity, need to flatten processing after each bonding technology.
Please refer to Figure 17, in the fourth embodiment of the invention, the method for packing of semiconductor device comprises:
Step S801, the chip that provides the surface to have pad, described chip surface is formed with passivation layer, and described passivation layer has the opening that exposes the part bond pad surface;
Step S802 forms the salient point that is positioned at bond pad surface in described opening, the size of described salient point is less than the size of described opening, and described salient point is the multiple-level stack structure;
Step S803 forms the barrier layer that covers described bump surface and cover the open bottom bond pad surface;
Step S804 forms the soakage layer that covers described barrier layer;
Step S805 forms the soldered ball that covers described soakage layer.
Concrete, please refer to Figure 18-Figure 20, Figure 18-Figure 20 shows the cross-sectional view of encapsulation process of the semiconductor device of fourth embodiment of the invention.
Please refer to Figure 18, the chip 900 that provides the surface to have pad 901 and integrated circuit, described pad 901 is electrically connected with integrated circuit, and described chip 900 surfaces are formed with passivation layer 903, and described passivation layer 903 has the opening 905 that exposes part pad 901.
Described chip 900 is used to subsequent technique that workbench is provided; The material of described pad 901 and integrated circuit is aluminium, copper, gold or silver-colored.
Please refer to Figure 19, at described opening 905(as shown in figure 18) in form the salient point 907 be positioned at pad 901 surfaces, the size of described salient point 907 is less than the size of described opening 905, and described salient point 907 is the multiple-level stack structure.
Through research, the inventor finds, described salient point 907 is except can be for the single layer structure, can also be the multiple-level stack structure, to satisfy different technique and product design demand, for example, for satisfying the demand of high density product, the salient point of the packaging part of the semiconductor device that industrial requirements forms is high 6 microns, and the sub-salient point of a lead key closing process formation is 3 microns, then needs lead key closing process 2 times.
Described salient point 907 comprises a plurality of sub-salient points, for example 2-5.The formation technique of described salient point 907 is that the formation technique of depositing operation and etching technics or described salient point 907 is lead key closing process.
In an embodiment of the present invention, described salient point 907 comprises the first sub-salient point 9071 that is positioned at described pad 901 surfaces, and the second sub-salient point 9072 that covers the described first sub-salient point 9071 surfaces, to satisfy different technique and product design demand.
Be to save processing step, the material of the described first sub-salient point 9071, the second sub-salient point 9072 is identical, is copper, and the described first sub-salient point 9071, that the second sub-salient point 9072 forms techniques is identical, is lead key closing process.Highly consistent for guaranteeing the final salient point 907 that forms, have preferably coplanarity, comprise that also each salient point 907 to forming after the lead key closing process flattens.
In an embodiment of the present invention, after each lead key closing process, the processing step that all once flattens.After namely adopting lead key closing process to form the first sub-salient point 9071, each first sub-salient point 9071 is flattened, make the height of each first sub-salient point 9071 consistent; Then adopt the first sub-salient point 9071 surfaces of lead key closing process after pressing to form the second sub-salient point 9072, again the second sub-salient point 9072 that forms is flattened, the height of each salient point 907 of final formation is more reached unanimity, coplanarity is better, the superior performance of the semiconductor device of follow-up formation.
Need to prove, in the fourth embodiment of the present invention, also comprise the salient point 907 that forms is annealed, make the better of combination between stacking sub-salient point, do not repeat them here.
Need to prove, in other embodiments of the invention, described salient point comprises the sub-salient point of multiple-level stack, the sub-salient point that is positioned at the top comprises sub-salient point body and the sub-salient point afterbody (not shown) that is positioned at described sub-salient point body surface, wherein, described salient point afterbody is to form after the starting the arc in the lead key closing process, the height of described sub-salient point afterbody is 0.005 ~ 1.5 times of sub-salient point body height, be beneficial to the contact area of follow-up further increase soldered ball and each layer of bottom, further strengthen the associativity of soldered ball.
Please refer to Figure 20, form the barrier layer 913 of surface and covering opening 905 bottom land 901; Form the soakage layer 915 that covers described barrier layer 913; Form the soldered ball 911 that covers described soakage layer 915.
The material of described barrier layer 913 is nickel, the mutually counterdiffusion of tin atom generation in the copper atom that is used for preventing salient point 907 and the soldered ball; The thickness of described barrier layer 913 is 0.05 micron-10 microns, and is better, is 0.5 micron-5 microns, best, be 1 micron-3 microns; At least comprise tin element, gold element or silver element in the material of described soakage layer 915, be used for preventing the oxidation of barrier layer 513, and improve the adhesion of itself and barrier layer 513, soldered ball, the thickness of described soakage layer 915 is 0.05 micron-3 microns; The material of described soldered ball 911 is tin or ashbury metal, and described soldered ball 911 is spherical, and its bottom is the train of dress shape.
More associated description about fourth embodiment of the invention please in conjunction with first, second and third embodiment of reference the present invention, do not repeat them here.
After above-mentioned steps is finished, the completing of the packaging part of the semiconductor device of fourth embodiment of the invention.Owing to having formed the salient point of multiple-level stack structure, having satisfied different technique and product design demand.And when adopting lead key closing process to form salient point, every formation one sub-salient point namely once flattens, and the height of the final salient point that forms is consistent, and coplanarity is good, and the performance of the packaging part of the semiconductor device of formation is good.
Accordingly, please refer to Figure 20, in the fourth embodiment of the present invention, the inventor also provides a kind of packaging part of semiconductor device, comprising: chip 900, and described chip surface has pad 901; Be positioned at the passivation layer 903 on described chip 900 surfaces, described passivation layer 903 has opening 905(as shown in figure 18), described opening 905 exposes part pad 901; Be positioned at the salient point 907 on described pad 901 surfaces, the size of described salient point 907 is the multiple-level stack structure less than size and the described salient point 907 of described opening 905; Cover described salient point 907 surfaces and cover opening 905 bottoms pad 901 surfaces barrier layer 913; Cover the soakage layer 915 of described barrier layer 913; Cover the soldered ball 911 of described soakage layer 915.
Wherein, described salient point 907 comprises a plurality of stacking sub-salient points, to satisfy different technique and product design demand.In the fourth embodiment of the present invention, described salient point 907 comprises: the first sub-salient point 9071 that is positioned at described pad 901 surfaces; And the second sub-salient point 9072 that covers the described first sub-salient point 9071.In an embodiment of the present invention, the described first sub-salient point 9071 is identical with the material of the second sub-salient point 9072, is copper, to save cost.Need to prove, the described first sub-salient point 9071 and the second sub-salient point 9072 size separately also can be identical or different.
Sidewall and pad 901 surfaces of the top of described barrier layer 913 coverings the described second sub-salient point 9072 and sidewall, the first sub-salient point 9071.The material of described barrier layer 913 is nickel, and thickness is 1 micron-3 microns.
Described soakage layer 915 covers described barrier layer 913, namely covers sidewall and pad 901 surfaces of the top of the described second sub-salient point 9072 and sidewall, the first sub-salient point 9071.At least comprise tin element, gold element or silver element in the material of described soakage layer 915, the thickness of described soakage layer 915 is 0.05 micron-3 microns.
Described soldered ball 911 covers described soakage layer 915, namely covers sidewall and pad 901 surfaces of the top of the described second sub-salient point 9072 and sidewall, the first sub-salient point 9071.Be subjected to gravity, infiltration power and capillary the impact, being shaped as of described soldered ball 911 is spherical, and its bottom is the train of dress shape.
Need to prove, in other examples of the present invention, described salient point can also comprise a plurality of stacking sub-salient points, and the sub-salient point that is positioned at the top comprises sub-salient point body and sub-salient point afterbody.Soldered ball is planted the top therewith, and to have a salient point Contact area of sub-salient point afterbody larger, and the intensity of the soldered ball of formation is higher.
In the fourth embodiment of the present invention, semiconductor device also comprises except the advantage with previous embodiment: salient point is the multiple-level stack structure, satisfies different technique and product design demand.
Comprehensive above-described embodiment, technical scheme of the present invention has the following advantages:
On the one hand, described soldered ball is formed on the salient point, is subjected to gravity, infiltration power and capillary the impact, and the gap between adjacent solder balls increases, and the packaging part of semiconductor device is not prone to short circuit phenomenon, and device performance is stable; On the other hand, because the size of salient point is less than the size of opening, described soldered ball not only covers the top of salient point, also covers the sidewall of salient point, and open bottom.The structure of train of dress shape is formed on the bottom of described soldered ball, has effectively increased the contact area between soldered ball and salient point, thereby has increased both adhesions, so that the bond strength of soldered ball increases, has improved packaging part performance and the yield of semiconductor device.
Further, also comprise: cover the barrier layer of top, sidewall and the open bottom of described salient point, and the soakage layer that covers described barrier layer.Described barrier layer has effectively stoped the altogether generation of compound of tin copper interface alloy, described soakage layer has effectively stoped the oxidation of barrier layer, and improved bond strength between soldered ball and barrier layer, further improved performance and the yield of the packaging part of semiconductor device.
Although the present invention with preferred embodiment openly as above; but it is not to limit claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (12)
1. the packaging part of a semiconductor device is characterized in that, comprising:
Chip, described chip surface has pad;
Be positioned at the passivation layer of described chip surface, described passivation layer has opening, and described opening exposes the part pad;
Be positioned at the salient point of described bond pad surface, the size of described salient point is less than the size of described opening;
Cover the soldered ball of described bump surface and covering open bottom bond pad surface.
2. the packaging part of semiconductor device as claimed in claim 1 is characterized in that, also comprises: cover the top of described salient point and the barrier layer of sidewall, described soldered ball is positioned at the barrier layer surface.
3. the packaging part of semiconductor device as claimed in claim 2 is characterized in that, described barrier layer also covers the pad of open bottom.
4. the packaging part of semiconductor device as claimed in claim 2 is characterized in that, the material of described barrier layer is nickel.
5. the packaging part of semiconductor device as claimed in claim 2 is characterized in that, the thickness of described barrier layer is 0.05 micron-10 microns.
6. the packaging part of semiconductor device as claimed in claim 2 is characterized in that, the thickness of described barrier layer is 1 micron-3 microns.
7. the packaging part of semiconductor device as claimed in claim 2 or claim 3 is characterized in that, also comprise: cover the soakage layer of described barrier layer, described soldered ball is positioned at the soakage layer surface.
8. the packaging part of semiconductor device as claimed in claim 7 is characterized in that, comprises at least tin element, gold element or silver element in the material of described soakage layer.
9. the packaging part of the semiconductor device of stating such as claim 7 is characterized in that the thickness of soakage layer is 0.05 micron-3 microns.
10. the packaging part of semiconductor device as claimed in claim 1 is characterized in that, described salient point comprises single or multiple stacking sub-salient points.
11. the packaging part of semiconductor device as claimed in claim 1 is characterized in that, described salient point comprises a plurality of stacking sub-salient points, and the sub-salient point that is positioned at the top comprises sub-salient point body and the sub-salient point afterbody that is positioned at described sub-salient point body surface.
12. the packaging part of semiconductor device as claimed in claim 1 is characterized in that, the material of described salient point is copper, gold, silver, copper alloy, billon or silver alloy, and the material of described soldered ball is tin or ashbury metal.
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| CN201210445562.8A CN102931164B (en) | 2012-11-08 | 2012-11-08 | The packaging part of semiconductor device |
| PCT/CN2013/086210 WO2014071813A1 (en) | 2012-11-08 | 2013-10-30 | Semiconductor device package and packaging method |
| US14/440,876 US9379077B2 (en) | 2012-11-08 | 2013-10-30 | Metal contact for semiconductor device |
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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |