CN104465500A - Method for improving copper interlinking - Google Patents
Method for improving copper interlinking Download PDFInfo
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- CN104465500A CN104465500A CN201410697334.9A CN201410697334A CN104465500A CN 104465500 A CN104465500 A CN 104465500A CN 201410697334 A CN201410697334 A CN 201410697334A CN 104465500 A CN104465500 A CN 104465500A
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- barrier layer
- dielectric barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a method for improving copper interlinking, and belongs to the technical field of semiconductor manufacturing. The method specifically comprises the steps that firstly, a first dielectric barrier layer, a dielectric layer and a hard mask layer deposit on a copper wire from bottom to top in sequence; secondly, a seed layer with a groove structure is formed with the hard mask layer as the basis in an etching mode; thirdly, the hard mask layer is removed through the chemical-mechanical polishing method; fourthly, a second dielectric barrier layer deposits on the seed layer and is an oxygen bearing dielectric barrier layer. By means of the technical scheme, the method has the advantages that the seed layer is covered with the oxygen bearing dielectric barrier layer, the oxygen bearing dielectric barrier layer can repel metal elements to the upper surface of the copper wire with the oxygen elements as drive power, and therefore the reallocation of the metal elements in the copper wire is not affected, and the resistance of the copper wire is reduced. The improvement of the structure is easy, and the manufacturing cost is low.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of method improving copper-connection.
Background technology
The ELECTROMIGRATION PHENOMENON produced in semiconductor fabrication mainly refers to that conductive ion motion causes the phenomenon of element or circuit malfunction under the effect of electric field, namely when devices function, certain electric current is had to pass through in metal interconnecting wires, metal ion can produce transporting of quality along conductor, its result can make some position of conductor produce cavity or whisker (hillock), specifically comprise occur in adjacent conductor surface as common silver ion migration and the metallization electron transfer occurring in metallic conductor inside.ELECTROMIGRATION PHENOMENON easily causes component failure, such as, cause the parameter degradation etc. of shorted devices, open circuit or device.
In prior art, in 45/40nm and 32/28nm manufacturing process, generally adopt the method for copper alloy Seed Layer to improve ELECTROMIGRATION PHENOMENON, the advantage of this method is that manufacture craft is simple, without the need to increasing extra processing step, and whole technological process is not affected.But adopt the method for copper alloy Seed Layer to improve ELECTROMIGRATION PHENOMENON, due to adding of wherein alloying element, thus the reallocation of alloying element in copper conductor can be affected, cause the resistance of whole copper conductor to increase.
Chinese patent (CN103295958A) discloses a kind of method preparing copper seed layer.After this technical scheme has prepared copper seed layer in use traditional handicraft, proceed a degassing process, the copper that through hole can be made to deposit flows into via bottoms, and then deposit a thinner copper seed layer, thus reduce the depth-to-width ratio of filling, and then improve the spreadability of filling bottom Seed Layer, there is the probability of hole when reducing subsequent copper plating, and then enhance product performance and yield.How technique scheme prepares copper seed layer if only relating to, and not mentionedly how to solve doped alloys element in copper seed layer, therefore cannot solve problems of the prior art.
Chinese patent (CN101573787) discloses a kind of mosaic technology adopting copper fill process to come filling groove (12).Copper is filled (20) and is started from the deposited seed layer (52) comprising copper and titanium.In copper fill process, some titaniums migrate to surface.Anneal to this structure in a nitrogen environment, this fills on the surface of (20) at copper and produces self aligned TiN stop (24).Air gap (26) can be produced in same annealing process.This technique can be used to form sandwich construction.Technique scheme only relates to how adopting Seed Layer formation sandwich construction, can not solve problems of the prior art.
Summary of the invention
According to problems of the prior art, a kind of method improving copper-connection is now provided, specifically comprises:
Improve a method for copper-connection, be applicable to make in the technique of copper conductor, wherein, specifically comprise:
Step 1, depositing first dielectric barrier layer, dielectric layer and hard mask layer successively from bottom to top on described copper conductor;
Step 2, forms with described hard mask layer the Seed Layer that has groove structure;
Step 3, removes described hard mask layer by CMP (Chemical Mechanical Polishing) process;
Step 4, described Seed Layer deposits one second dielectric barrier layer;
Described second dielectric barrier layer is one containing oxygen dielectric barrier layer.
Preferably, the method for this improvement copper-connection, wherein, described step 2 specifically comprises;
Step 21, forms a groove structure by chemical etching;
Step 22. forms a barrier layer by physical gas-phase deposition on described groove structure;
Step 23, forms described Seed Layer by physical gas-phase deposition on described barrier layer;
Step 24, carries out electro-coppering to described Seed Layer.
Preferably, the method for this improvement copper-connection, wherein, in described step 2, described Seed Layer is cupromanganese Seed Layer.
Preferably, the method for this improvement copper-connection, wherein, the thickness of described second dielectric barrier layer is less than 150 dusts.
Preferably, the method for this improvement copper-connection, wherein, the thickness of described second dielectric barrier layer is less than 50 dusts.
Preferably, the method for this improvement copper-connection, wherein, comprises silicon oxynitride in described second dielectric barrier layer, or silicon oxide carbide, or silicon dioxide.
Preferably, the method for this improvement copper-connection, wherein, deposits the temperature of described second dielectric barrier layer not higher than 400 DEG C.
Preferably, the method for this improvement copper-connection, wherein, deposits described first dielectric barrier layer and described second dielectric barrier layer in same semiconductor equipment;
Described semiconductor equipment comprises the first reaction chamber and the second reaction chamber;
In described first reaction chamber, deposit described first dielectric barrier layer, in described second reaction chamber, deposit described second dielectric barrier layer.
Preferably, the method for this improvement copper-connection, wherein, deposits described first dielectric barrier layer and described second dielectric barrier layer in same semiconductor equipment;
Described semiconductor equipment comprises the 3rd reaction chamber;
Described first dielectric barrier layer and described second dielectric barrier layer is deposited successively in described 3rd reaction chamber.
Preferably, the method for this improvement copper-connection, wherein, the oxygen content in described second dielectric barrier layer is 10%-50%.
The beneficial effect of technique scheme is: adopt and cover Seed Layer containing oxygen barrier layers, metallic element can be driven upper surface to copper conductor, thus not affect the reallocation of metallic element in copper conductor, reduce the resistance of copper conductor with oxygen element as actuating force.Architecture advances is simple, low cost of manufacture.
Accompanying drawing explanation
Fig. 1 is in preferred embodiment of the present invention, a kind of schematic flow sheet improving the method for copper-connection;
Fig. 2-3 is in preferred embodiment of the present invention, and on the basis of Fig. 1, application improves the copper interconnection structure schematic diagram of the method for copper-connection;
Fig. 4 is in preferred embodiment of the present invention, on the basis of Fig. 1, there is the schematic flow sheet of the Seed Layer of groove structure.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as limiting to the invention.
As shown in Figure 1, in preferred embodiment of the present invention, a kind of method improving copper-connection, specifically comprises;
Step 1, depositing first dielectric barrier layer, dielectric layer and hard mask layer successively from bottom to top on copper conductor;
In preferred embodiment of the present invention, as Figure 2-3, on copper conductor, first deposit one deck first dielectric barrier layer 1, this first dielectric barrier layer 1 is common dielectric barrier layer (DielectricBarrier, DB); On this first dielectric barrier layer 1, deposit one dielectric layer 2 subsequently, in preferred embodiment of the present invention, this dielectric layer 2 is a ultralow dielectric coefficient layer (Ultra Low K, ULK), and this dielectric layer 2 deposits one deck hard mask layer.In preferred embodiment of the present invention, because hard mask layer can at CMP (Chemical Mechanical Polishing) process (Chemical Mechanical Polishing afterwards, CMP) be removed in, therefore in structural representation as shown in figures 2-3 and not shown above-mentioned hard mask layer.
Step 2, etches the Seed Layer that formation one has groove structure based on hard mask layer;
In preferred embodiment of the present invention, owing to needing the electromigration characteristic improved in copper conductor, therefore can form one deck Seed Layer 4 (Seed) wherein.Further, in preferred embodiment of the present invention, this Seed Layer is a copper alloy Seed Layer, effectively can improve the ELECTROMIGRATION PHENOMENON in copper conductor.
Step 3, removes hard mask layer by CMP (Chemical Mechanical Polishing) process;
Step 4, deposits one second dielectric barrier layer on the seed layer;
Because Seed Layer 4 comprises some doping metallic element 5 wherein, particularly alloying elements, the reallocation of the metallic element in copper conductor can be had influence on, thus affect the resistance (such as increasing the resistance of copper conductor) of copper conductor, affect workmanship and the using state of whole copper conductor.Therefore, in preferred embodiment of the present invention, above-mentioned Seed Layer 4 deposits one deck second dielectric barrier layer 6.
Further, in preferred embodiment of the present invention, first, this second dielectric barrier layer 6 is as dielectric barrier layer Seed Layer 4 be isolated from the outside, secondly, because oxygen element can as the actuating force of metallic element 5, Seed Layer 4 on purpose increases some oxygen elements, metallic element 5 can be made from distribution (as shown in Figure 2) gradually by the upper surface (as shown in Figure 3) driven to copper conductor, thus the metallic element remaining in copper conductor inside is obviously reduced, reduce the resistance of copper conductor itself, to reach the object improving electromigration characteristic, therefore in the second dielectric barrier layer 6, oxygen element is mixed, namely the second dielectric barrier layer 6 is one containing oxygen dielectric barrier layer (O doped Dielectric Barrier), when containing oxygen dielectric barrier deposition above Seed Layer 4 time, if Deng injecting oxygen element above Seed Layer 4, thus drive the metallic element 5 in Seed Layer 4 to move to the upper surface of copper conductor.
Based on mentioned above, the main component of traditional dielectric barrier layer (i.e. the first dielectric barrier layer 1) is fire sand (SiCN), wherein not containing oxygen element.Therefore, in above-mentioned first dielectric barrier layer 1, add some oxygen elements, to form the second dielectric barrier layer 6.
Further, in preferred embodiment of the present invention, described in above, the main component of the second dielectric barrier layer 6 can be silicon oxynitride (SiON), silicon oxide carbide (SiOC) or silicon dioxide (SiO2).The main composition composition of this second dielectric barrier layer 6 is not limited to above-mentioned material, and other are suitable for making dielectric barrier layer and add the material of oxygen element wherein all can as the main component of the second electrical barrier 6 in preferred embodiment of the present invention.
Further, in preferred embodiment of the present invention, above-mentioned Seed Layer 4 is cupromanganese Seed Layer, manganese (Mn) in cupromanganese reacts with the oxydant (such as silicon dioxide) in the second dielectric barrier layer 6, to form MnxSiOx, thus as preventing the barrier layer that in Seed Layer, metallic element 5 spreads, namely cupromanganese Seed Layer has the ability (Self-forming Barrier) that oneself forms barrier layer.
In other embodiments of the present invention, other alloy materials with oneself's formation barrier layer ability can be adopted to form above-mentioned Seed Layer, be not limited to cupromanganese.
In preferred embodiment of the present invention, the thickness of above-mentioned second dielectric barrier layer 6 is less than 150 dusts
further, in preferred embodiment of the present invention, the thickness of above-mentioned second dielectric barrier layer 6 is less than 50 dusts,
Further, in preferred embodiment of the present invention, the depositing temperature of deposit those second dielectric barrier layer 6 is no more than 400 DEG C, to meet the heat budget (thermal budget) of process requirements.
In preferred embodiment of the present invention, above-mentioned second dielectric barrier layer 6 is prepared one deck first dielectric barrier layer (not shown) again, to prevent Seed Layer 4 and extraneous contact further.
In preferred embodiment of the present invention, the flow process preparing above-mentioned first dielectric barrier layer 1 and preparation the second dielectric barrier layer 4 can be carried out in same semiconductor equipment:
In a preferred embodiment of the present invention, one first reaction chamber and one second reaction chamber is comprised at this semiconductor equipment, above-mentioned first dielectric barrier layer 1 is prepared in the first reaction chamber, above-mentioned second dielectric barrier layer 4, two reaction chambers are prepared independent of one another in the second reaction chamber.The object that above-mentioned two processing procedures carry out in same semiconductor equipment can be realized like this, save manufacturing cost.
In another preferred embodiment of the present invention, comprise one the 3rd reaction chamber at this semiconductor equipment, in this second reaction chamber, prepare above-mentioned first dielectric barrier layer 1 and the second dielectric barrier layer 4 successively.Because the difference between the second dielectric barrier layer 4 and the first dielectric barrier layer 1 is mainly that the second dielectric barrier layer 4 comprises the oxygen element additionally added, also namely the difference of both preparation process is to add oxygen source when preparation the second dielectric barrier layer 4.Therefore, in same 3rd reaction chamber, do not add oxygen source when preparation the first dielectric barrier layer 1, and according to normal flow preparation, and add corresponding oxygen source when preparation the second dielectric barrier layer 4.Then when continuing preparation the first dielectric barrier layer 1, oxygen source is removed.Carry out in the same reaction chamber that the technical process of preparation first dielectric barrier layer and the second dielectric barrier layer can be placed on same semiconductor equipment by the application of above-mentioned flow process, greatly save manufacturing cost.
In preferred embodiment of the present invention, as shown in Figure 4, above-mentioned steps 2 specifically comprises:
Step 21, forms a groove structure by chemical etching;
In preferred embodiment of the present invention, on above-mentioned dielectric layer 2, based on hard mask layer, form a groove structure preset by photoetching (litho) and etching (etch);
Step 22, forms a barrier layer on the groove structure by physical gas-phase deposition;
In preferred embodiment of the present invention, as Figure 2-3, in order to by dielectric layer 2 with afterwards the Seed Layer 4 formed on the groove structure is isolated, to avoid the metallic element 5 in Seed Layer 4 to leak, first deposit one deck barrier layer 3 (Barrier) on the groove structure.
Step 23, forms Seed Layer over the barrier layer by physical gas-phase deposition;
In preferred embodiment of the present invention, by physical gas-phase deposition (Physical VaporDeposition, PVD), the barrier layer 3 deposited is formed a Seed Layer 4 in the groove structure such as described in step 21.
Step 24, carries out electro-coppering to Seed Layer.
In preferred embodiment of the present invention, by electro-coppering, above-mentioned Seed Layer 4 becomes a cupromanganese Seed Layer.
The foregoing is only preferred embodiment of the present invention; not thereby embodiments of the present invention and protection range is limited; to those skilled in the art; should recognize and all should be included in the scheme that equivalent replacement done by all utilizations specification of the present invention and diagramatic content and apparent change obtain in protection scope of the present invention.
Claims (10)
1. improve a method for copper-connection, be applicable to make in the technique of copper conductor, it is characterized in that, specifically comprise:
Step 1, depositing first dielectric barrier layer, dielectric layer and hard mask layer successively from bottom to top on described copper conductor;
Step 2, etches the Seed Layer that formation one has groove structure based on described hard mask layer;
Step 3, removes described hard mask layer by CMP (Chemical Mechanical Polishing) process;
Step 4, described Seed Layer deposits one second dielectric barrier layer;
Wherein, described second dielectric barrier layer is one containing oxygen dielectric barrier layer.
2. improve the method for copper-connection as claimed in claim 1, it is characterized in that, described step 2 specifically comprises;
Step 21, forms a groove structure by chemical etching;
Step 22, forms a barrier layer by physical gas-phase deposition on described groove structure;
Step 23, forms described Seed Layer by physical gas-phase deposition on described barrier layer;
Step 24, carries out electro-coppering to described Seed Layer.
3. improve the method for copper-connection as claimed in claim 1, it is characterized in that, in described step 2, described Seed Layer is cupromanganese Seed Layer.
4. improve the method for copper-connection as claimed in claim 1, it is characterized in that, the thickness of described second dielectric barrier layer is less than 150 dusts.
5. improve the method for copper-connection as claimed in claim 4, it is characterized in that, the thickness of described second dielectric barrier layer is less than 50 dusts.
6. improve the method for copper-connection as claimed in claim 1, it is characterized in that, in described second dielectric barrier layer, comprise silicon oxynitride, or silicon oxide carbide, or silicon dioxide.
7. improve the method for copper-connection as claimed in claim 1, it is characterized in that, deposit the temperature of described second dielectric barrier layer not higher than 400 DEG C.
8. improve the method for copper-connection as claimed in claim 1, it is characterized in that, in same semiconductor equipment, deposit described first dielectric barrier layer and described second dielectric barrier layer;
Described semiconductor equipment comprises the first reaction chamber and the second reaction chamber;
In described first reaction chamber, deposit described first dielectric barrier layer, in described second reaction chamber, deposit described second dielectric barrier layer.
9. improve the method for copper-connection as claimed in claim 1, it is characterized in that, in same semiconductor equipment, deposit described first dielectric barrier layer and described second dielectric barrier layer;
Described semiconductor equipment comprises the 3rd reaction chamber;
Described first dielectric barrier layer and described second dielectric barrier layer is deposited successively in described 3rd reaction chamber.
10. improve the method for copper-connection as claimed in claim 1, it is characterized in that, the oxygen content in described second dielectric barrier layer is 10%-50%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410697334.9A CN104465500A (en) | 2014-11-26 | 2014-11-26 | Method for improving copper interlinking |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410697334.9A CN104465500A (en) | 2014-11-26 | 2014-11-26 | Method for improving copper interlinking |
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| CN104465500A true CN104465500A (en) | 2015-03-25 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6184138B1 (en) * | 1999-09-07 | 2001-02-06 | Chartered Semiconductor Manufacturing Ltd. | Method to create a controllable and reproducible dual copper damascene structure |
| CN1565047A (en) * | 2002-06-25 | 2005-01-12 | 索尼株式会社 | Method of manufacturing semiconductor device |
| CN102881633A (en) * | 2011-07-15 | 2013-01-16 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of copper interconnection structure |
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- 2014-11-26 CN CN201410697334.9A patent/CN104465500A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6184138B1 (en) * | 1999-09-07 | 2001-02-06 | Chartered Semiconductor Manufacturing Ltd. | Method to create a controllable and reproducible dual copper damascene structure |
| CN1565047A (en) * | 2002-06-25 | 2005-01-12 | 索尼株式会社 | Method of manufacturing semiconductor device |
| CN102881633A (en) * | 2011-07-15 | 2013-01-16 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of copper interconnection structure |
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Application publication date: 20150325 |