KR100257856B1 - Method of manufacturing a metal line of semiconductor device - Google Patents

Method of manufacturing a metal line of semiconductor device Download PDF

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KR100257856B1
KR100257856B1 KR1019970054432A KR19970054432A KR100257856B1 KR 100257856 B1 KR100257856 B1 KR 100257856B1 KR 1019970054432 A KR1019970054432 A KR 1019970054432A KR 19970054432 A KR19970054432 A KR 19970054432A KR 100257856 B1 KR100257856 B1 KR 100257856B1
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thin film
trench
metal
semiconductor device
forming
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KR1019970054432A
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KR19990033163A (en
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이성권
김남성
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Abstract

PURPOSE: A method for forming a metal wiring of a semiconductor device is provided to improve the reliability of the semiconductor device by forming a metal wiring layer having a superior electric characteristic. CONSTITUTION: An insulating layer(12) is deposited on an upper portion of a semiconductor substrate(11). A trench is formed on a predetermined portion of the insulating layer(12). Then, a barrier layer(13), a pure metal thin film(14A) and a metal thin film having an impurity are sequentially deposited on the upper portion of the resulted structure. After that, the barrier layer(13), the pure metal thin film(14A) and the metal thin film are heat-treated to fill the trench. Then, an etch back process and a planarization process are carried out in order to form a metal wiring in the trench.

Description

반도체 소자의 금속 배선 형성 방법Metal wiring formation method of semiconductor device

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 구리(Cu) 박막을 금속 배선용으로 사용하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method of using a copper (Cu) thin film for metal wiring.

일반적으로, 반도체 소자의 전도층 재료로 많이 사용되고 있는 알루미늄(Al) 합금은 낮은 융점과 높은 비저항 등의 특성으로 인하여 초대규모 집적회로(Ultra Large Scale Integration)급 반도체 소자에서는 더 이상의 적용이 어렵게 되었다. 따라서, 대체 재료의 필요성이 대두되었고, 그러한 재료 중의 하나가 바로 높은 전도도 특성을 갖는 구리 합금이다.In general, aluminum (Al) alloys, which are widely used as conductive layer materials of semiconductor devices, are difficult to be applied in ultra large scale integration class semiconductor devices due to their low melting point and high resistivity. Thus, there is a need for alternative materials, one of which is copper alloys having high conductivity properties.

그러나 금속 배선으로 구리 박막을 이용하게 되는 차세대 반도체 소자는 매우 협소한 디자인 룰(design rule)을 갖기 때문에 구리 박막의 증착시 층덮힘(stepcoverage)이 양호한 화학기상증착법(CVD)으로 증착되어야 한다. 하지만 아직까지 구리 박막 증착 공정 기술 개발 현황은 물리기상증착법(PVD)을 이용한 구리 박막 증착은 용이하나 화학기상증착법을 이용한 구리 박막의 증착은 충분하게 개발되어 있지 않은 실정이다.However, since next-generation semiconductor devices using copper thin films as metal wirings have very narrow design rules, they should be deposited by chemical vapor deposition (CVD) with good step coverage during the deposition of copper thin films. However, the current development of copper thin film deposition process technology is easy to deposit copper thin film using physical vapor deposition (PVD), but the deposition of copper thin film using chemical vapor deposition has not been sufficiently developed.

본 발명은 상기한 문제점을 해결하여 소자의 전기적 특성이 우수한 금속 배선층을 형성하는데 그 목적이 있다.An object of the present invention is to solve the above problems to form a metal wiring layer excellent in the electrical characteristics of the device.

상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속 배선 형성 방법은, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판 상부에 절연막을 증착하고, 상기 절연막의 선택된 부분에 트렌치를 형성하는 단계와, 상기 트렌치를 포함하는 전체 구조 상부에 장벽층, 순수 금속 박막 및 불순물 함유 금속 박막을 순차로 증착한 후, 열처리로 리플로우 시켜 상기 트렌치의 내부가 완전히 매립되도록 하는 단계와, 에치 백 공정 및 평탄화 공정으로 상기 트렌치 내부에 금속 배선이 형성되도록 하는 단계로 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method for forming a metal wiring of a semiconductor device, the method including: depositing an insulating film on a substrate having a structure in which various elements for forming the semiconductor device are formed, and forming a trench in a selected portion of the insulating film; And depositing a barrier layer, a pure metal thin film, and an impurity containing metal thin film on top of the entire structure including the trench, and then reflowing by heat treatment so that the inside of the trench is completely buried. And forming a metal line in the trench by a planarization process.

도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순차적으로 도시한 단면도.1 (a) to 1 (c) are cross-sectional views sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

11 : 기판 12 : 절연막11 substrate 12 insulating film

13 : 장벽층 14A : 순수 구리 박막13: barrier layer 14A: pure copper thin film

14B : 불순물 함유 구리 박막14B: Impurity-containing copper thin film

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순차적으로 도시한 단면도이다.1 (a) to 1 (c) are cross-sectional views sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.

도 1(a)에 도시된 것과 같이, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(11) 상부에 절연막(12)을 증착하고, 금속 배선이 형성될 영역을 식각하여 트렌치(A)를 형성한다. 그리고 나서 트렌치(A)를 포함하는 전체 구조 상부에 장벽층(barrier material ; 13), 순수한 성분의 구리 박막(14A) 및 불순물이 함유된 구리 박막(14B)을 순차로 증착을 증착한다. 이 때 절연막(12)은 실리콘산화막(SiO2), BPSG막 및 질화산화막(oxynitride)중 적어도 어느 하나를 사용하여 화학기상증착법으로 증착하고, 장벽층(13)은 타이타늄나이트라이드(TiN), 코발트나이트라이드(CoN) 및 텅스텐나이트라이드(WN) 중 어느 하나를 사용한다. 또한, 순수한 성분의 구리 박막(14A) 및 불순물이 함유된 구리 박막(14B)은 증착이 용이한 물리기상증착법을 이용하여 증착하고, 불순물로는 5 % 미만인 미량의 마그네슘(Mg)이나 게르마늄(Ge)과 같은 금속등을 사용한다. 금속 배선용 재료로 위와 같은 구리 이외에 차세대 반도체 소자 재료로 적용 가능한 금속 즉, 금(Au), 은(Ag), PZT, BST 및 플래티늄(Pt)등을 사용하는 경우에도 본 발명에 따른 방법의 적용이 가능하다.As illustrated in FIG. 1A, an insulating film 12 is deposited on the substrate 11 having a structure in which various elements for forming a semiconductor device are formed, and a region where metal wiring is to be formed is etched to form a trench A. To form. Then, the deposition is sequentially deposited on the entire structure including the trench A, a barrier material 13, a pure copper thin film 14A and an impurity copper thin film 14B. At this time, the insulating film 12 is deposited by chemical vapor deposition using at least one of a silicon oxide film (SiO 2 ), a BPSG film and an oxynitride, and the barrier layer 13 is made of titanium nitride (TiN) or cobalt. One of nitride (CoN) and tungsten nitride (WN) is used. In addition, the pure copper thin film 14A and the impurity-containing copper thin film 14B are deposited using an easy physical vapor deposition method, and the trace amount of magnesium (Mg) or germanium (Ge) is less than 5% as impurities. Use metal such as). The use of the method according to the present invention also applies to the use of metals applicable to the next-generation semiconductor device materials, namely, gold (Au), silver (Ag), PZT, BST and platinum (Pt), as well as copper. It is possible.

도 1(b)는 아르곤(Ar) 가스와 질소(N2) 가스의 저압 분위기(0.05 Torr ∼ 50 Torr)에서 600 ℃ 이하로 열처리한 구조의 단면도이다. 아르곤 가스와 질소 가스 분위기에 노출된 불순물이 함유된 구리 박막(14B)은, 열처리에 의하여 불순물 원자가 일부 이동하게 된다. 이로 인하여 순수한 성분의 구리 박막(14A) 및 불순물이 함유된 구리 박막(14B)이 리플로우 되면서 트렌치(A) 내부는 순수한 구리층만으로 완전한 층덮힘이 되어 매립 된다.FIG. 1B is a cross-sectional view of a structure heat-treated at 600 ° C. or less in a low pressure atmosphere (0.05 Torr to 50 Torr) of argon (Ar) gas and nitrogen (N 2 ) gas. In the copper thin film 14B containing the impurities exposed to the argon gas and the nitrogen gas atmosphere, some of the impurity atoms are moved by heat treatment. As a result, the pure thin copper film 14A and the impurities containing the thin copper film 14B are reflowed, and the inside of the trench A is completely covered with only a pure copper layer to be filled.

도 1(c)에 도시된 것과 같이, 리플로우된 불순물이 함유된 구리 박막(14B), 순수한 성분의 구리 박막(14A) 및 장벽층(13)을 화학적기계연마법(CMP)을 이용하여 평탄화 시킴으로써 트렌치(A) 내부에 층덮힘이 양호한 금속 배선을 완성할 수 있게 된다.As shown in Fig. 1 (c), the copper thin film 14B containing the reflowed impurities, the copper thin film 14A of the pure component and the barrier layer 13 are planarized by chemical mechanical polishing (CMP). It is possible to complete a metal wiring having a good layer covering inside the trench A. FIG.

상술한 바와 같이 본 발명에 의하면, 구리 금속을 반도체 소자에 적용하게 됨에 따라 소자의 신뢰성이 향상되고, 제조 공정시 구리 박막을 증착이 용이한 물리기상증착법으로 증착하고도 열처리를 통하여 화학기상증착법에서 얻을 수 있는 층덮힘 효과를 갖을 수 있게 된다.As described above, according to the present invention, as the copper metal is applied to the semiconductor device, the reliability of the device is improved, and in the chemical vapor deposition method, the copper thin film is deposited by physical vapor deposition which is easy to deposit during the manufacturing process. It can have a layering effect that can be obtained.

Claims (7)

반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판 상부에 절연막을 증착하고, 상기 절연막의 선택된 부분에 트렌치를 형성하는 단계와,Depositing an insulating film on a substrate having a structure in which various elements for forming a semiconductor device are formed, and forming a trench in a selected portion of the insulating film; 상기 트렌치를 포함하는 전체 구조 상부에 장벽층, 순수 금속 박막 및 불순물 함유 금속 박막을 순차로 증착한 후, 열처리로 리플로우 시켜 상기 트렌치의 내부가 완전히 매립되도록 하는 단계와,Sequentially depositing a barrier layer, a pure metal thin film, and an impurity containing metal thin film on the entire structure including the trench, and then reflowing by heat treatment to completely fill the inside of the trench; 에치 백 공정 및 평탄화 공정으로 상기 트렌치 내부에 금속 배선이 형성되도록 하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And forming a metal wiring inside the trench by an etch back process and a planarization process. 제 1 항에 있어서,The method of claim 1, 상기 장벽층은 타이타늄나이트라이드(TiN), 코발트나이트라이드(CoN) 및 텅스텐나이트라이드(WN) 중 어느 하나인 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The barrier layer is any one of titanium nitride (TiN), cobalt nitride (CoN) and tungsten nitride (WN). 제 1 항에 있어서,The method of claim 1, 배선용 금속은 구리(Cu), 금(Au), 은(Ag), PZT, BST 및 플래티늄(Pt)등의 금속 박막중 어느 하나를 사용하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The wiring metal is any one of metal thin films, such as copper (Cu), gold (Au), silver (Ag), PZT, BST, and platinum (Pt). 제 1 항에 있어서,The method of claim 1, 상기 불순물 함유 금속 박막은 금속 불순물이 5 % 미만 함유된 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The impurity-containing metal thin film is a metal wiring formation method of a semiconductor device, characterized in that less than 5% of metal impurities. 제 4 항에 있어서,The method of claim 4, wherein 상기 금속 불순물은 마그네슘(Mg) 및 게르마늄(Ge) 중 적어도 어느 하나를 사용하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The metal impurity uses at least one of magnesium (Mg) and germanium (Ge). 제 1 항에 있어서,The method of claim 1, 상기 열처리 공정은 0.05 Torr 내지 50 Torr의 저압 및 600 ℃ 이하 온도 영역의 아르곤 가스 및 질소 가스 분위기에서 실시하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The heat treatment step is a metal wiring forming method of a semiconductor device, characterized in that carried out in an argon gas and nitrogen gas atmosphere of a low pressure of 0.05 Torr to 50 Torr and a temperature range of 600 ℃ or less. 제 1 항에 있어서,The method of claim 1, 에치 백 공정 및 평탄화 공정은 화학적기계연마법를 이용하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.An etch back process and a planarization process use a chemical mechanical polishing method.
KR1019970054432A 1997-10-23 1997-10-23 Method of manufacturing a metal line of semiconductor device KR100257856B1 (en)

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