CN104464657A - 基于低温多晶硅半导体薄膜晶体管的goa电路 - Google Patents
基于低温多晶硅半导体薄膜晶体管的goa电路 Download PDFInfo
- Publication number
- CN104464657A CN104464657A CN201410609193.0A CN201410609193A CN104464657A CN 104464657 A CN104464657 A CN 104464657A CN 201410609193 A CN201410609193 A CN 201410609193A CN 104464657 A CN104464657 A CN 104464657A
- Authority
- CN
- China
- Prior art keywords
- transistor
- electrically connected
- constant voltage
- potential
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 49
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 46
- 230000000630 rising effect Effects 0.000 claims description 12
- 238000013461 design Methods 0.000 claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 101150070727 CSNK2B gene Proteins 0.000 description 1
- 102100027992 Casein kinase II subunit beta Human genes 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009131 signaling function Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000004304 visual acuity Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2230/00—Details of flat display driving waveforms
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
- G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Theoretical Computer Science (AREA)
- Ceramic Engineering (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Liquid Crystal (AREA)
- Shift Register Type Memory (AREA)
Abstract
本发明提供一种基于低温多晶硅半导体薄膜晶体管的GOA电路,包括级联的多个GOA单元;第N级GOA单元包括一上拉控制部分(100)、一上拉部分(200)、一第一下拉部分(400)、和一下拉维持电路部分(500);所述下拉维持电路部分(500)采用高低电位反推设计,并设置依次降低的第一、第二、第三直流恒压低电位(VSS1、VSS2、VSS3)、及一直流恒压高电位(H),能够解决低温多晶硅半导体薄膜晶体管的自身特性对GOA驱动电路的影响,尤其是漏电问题带来的GOA功能性不良;同时解决了目前基于低温多晶硅半导体薄膜晶体管的GOA电路中下拉维持电路部分在非作用期间第二节点电位不能处于较高的电位的问题,有效维持第一节点(Q(N))和输出端(G(N))的低电位。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种基于低温多晶硅半导体薄膜晶体管的GOA电路。
背景技术
GOA(Gate Drive On Array),是利用薄膜晶体管(thin film transistor,TFT)液晶显示器阵列(Array)制程将栅极驱动器制作在薄膜晶体管阵列基板上,以实现逐行扫描的驱动方式。
通常,GOA电路主要由上拉部分(Pull-up part)、上拉控制部分(Pull-upcontrol part)、下传部分(Transfer part)、下拉部分(Pull-down part)、下拉维持电路部分(Pull-down Holding part)、以及负责电位抬升的上升部分(Boost part)组成,上升部分一般由一自举电容构成。
上拉部分主要负责将输入的时钟信号(Clock)输出至薄膜晶体管的栅极,作为液晶显示器的驱动信号。上拉控制部分主要负责控制上拉部分的打开,一般是由上级GOA电路传递来的信号作用。下拉部分主要负责在输出扫描信号后,快速地将扫描信号(亦即薄膜晶体管的栅极的电位)拉低为低电平。下拉维持电路部分则主要负责将扫描信号和上拉部分的信号保持在关闭状态(即设定的负电位)。上升部分则主要负责对上拉部分的电位进行二次抬升,确保上拉部分的正常输出。
随着低温多晶硅(Low Temperature Poly-silicon,LTPS)半导体薄膜晶体管的发展,LTPS-TFT液晶显示器也越来越受关注,LTPS-TFT液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点。由于低温多晶硅较非晶硅(a-Si)的排列有次序,低温多晶硅半导体本身具有超高的电子迁移率,比非晶硅半导体相对高100倍以上,可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上,达到***整合的目标、节省空间及驱动IC的成本。然而,现有技术中针对低温多晶硅半导体薄膜晶体管的GOA电路的开发较少,尤其需要克服很多由于低温多晶硅半导体薄膜晶体管电性本身带来的问题。例如:传统的非晶硅半导体薄膜晶体管的电学特性中阈值电压一般大于0V,而且亚阈值区域的电压相对于电流的摆幅较大,但是低温多晶硅半导体薄膜晶体管的阈值电压值较低(一般约为0V左右),而且亚阈值区域的摆幅较小,而GOA电路在关态时很多元件操作与阈值电压接近,甚至高于阈值电压,这样就会由于电路中TFT的漏电和工作电流的漂移,增加LTPS GOA电路设计的难度,很多适用于非晶硅半导体的扫描驱动电路,不能轻易的应用到低温多晶硅半导体的行扫描驱动电路中,会存在一些功能性问题,这样将会直接导致LTPSGOA电路无法工作,所以在设计电路时必须要考虑到低温多晶硅半导体薄膜晶体管的自身特性对GOA电路的影响。
发明内容
本发明的目的在于提供一种基于低温多晶硅半导体薄膜晶体管的GOA电路,解决低温多晶硅半导体薄膜晶体管的自身特性对GOA驱动电路的影响,尤其是漏电问题带来的GOA功能性不良;解决目前基于低温多晶硅半导体薄膜晶体管的GOA电路中下拉维持电路部分在非作用期间第二节点电位不能处于较高的电位的问题。
为实现上述目的,本发明提供一种基于低温多晶硅半导体薄膜晶体管的GOA电路,包括级联的多个GOA单元,设N为正整数,第N级GOA单元包括一上拉控制部分、一上拉部分、一第一下拉部分、和一下拉维持电路部分;
所述上拉控制部分包括第一晶体管,其栅极与源极均电性连接于该第N级GOA单元的上一级第N-1级GOA单元的输出端,漏极电性连接于第一节点;
所述上拉部分包括第二晶体管,其栅极电性连接于第一节点,源极电性连接于时钟驱动信号,漏极电性连接于输出端;
所述下拉维持电路部分电性连接于所述第一节点、输出端、一直流恒压高电位、及第一、第二、与第三直流恒压低电位;所述下拉维持电路部分采用高低电位反推设计,包括:
第三晶体管,所述第三晶体管的栅极和源极均电性连接于直流恒压高电位,漏极电性连接于第五晶体管的源极;
第四晶体管,所述第四晶体管的栅极电性连接于第三晶体管的漏极,源极电性连接于直流恒压高电位,漏极电性连接于第二节点;
第五晶体管,所述第五晶体管的栅极电性连接于第一节点,源极电性连接于第三晶体管的漏极,漏极电性连接于第一直流恒压低电位;
第六晶体管,所述第六晶体管的栅极电性连接于第一节点,源极电性连接于第二节点,漏极电性连接于第八晶体管的栅极;
第七晶体管,所述第七晶体管的栅极电性连接于第一节点,源极电性连接于第二节点,漏极电性连接于第八晶体管的源极;
第八晶体管,所述第八晶体管的栅极电性连接于第六晶体管的漏极,源极电性连接于第七晶体管的漏极,漏极电性连接于第三直流恒压低电位;
第九晶体管,所述第九晶体管的栅极电性连接于第六晶体管的漏极,源极电性连接于第十晶体管的栅极,漏极电性连接于第三直流恒压低电位;
第十晶体管,所述第十晶体管的栅极与源极均电性连接于直流恒压高电位,漏极电性连接于第七晶体管的漏极;
第十二晶体管,所述第十二晶体管的栅极电性连接于第二节点,源极电性连接于第一节点,漏极电性连接于第二直流恒压低电位;
第十三晶体管,所述第十三晶体管的栅极电性连接于第二节点,源极电性连接于输出端,漏极电性连接于第一直流恒压低电位;
所述第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管提供正向高电位,用于控制第十二晶体管和第十三晶体管的打开;所述第八晶体管、第九晶体管构成作用期间的负电位的反向自举,用于在作用期间向第二节点提供更低电位;利用直流恒压高电位在非作用期间向第二节点提供适当的高电位,使得第一节点与输出端维持低电位;
所述第一下拉部分电性连接于所述第一节点、所述第N级GOA单元的下一级第N+1级GOA单元的输出端及第二直流恒压低电位,所述第一下拉部分依据所述第N级GOA单元的下一级第N+1级GOA单元的输出端的输出信号下拉所述第一节点的电位至所述第二直流恒压低电位;
所述第一下拉部分包括一第十四晶体管,所述第十四晶体管的栅极电性连接于所述第N级GOA单元的下一级第N+1级GOA单元的输出端,源极电性连接于第一节点,漏极电性连接于第二直流恒压低电位;
所述第三直流恒压低电位<第二直流恒压低电位<第一直流恒压低电位。
所述第四晶体管、第七晶体管、与第八晶体管串联。
所述基于低温多晶硅半导体薄膜晶体管的GOA电路,还包括一上升部分,所述上升部分电性连接于所述第一节点与输出端之间,用来抬升所述第一节点的电位。
所述上升部分包括一电容,所述电容的一端电性连接于第一节点,另一端电性连接于输出端。
所述时钟驱动信号波形占空比小于50/50。
所述第一节点的信号输出波形呈“凸”字形。
所述GOA电路的第一级连接关系中,第一晶体管的栅极与源极均电性连接于电路的启动信号端。
所述GOA电路的最后一级连接关系中,第十四晶体管的栅极电性连接于电路的启动信号端。
所述GOA电路采用输出端的输出信号作为上下级传信号。
本发明的有益效果:本发明提供的基于低温多晶硅半导体薄膜晶体管的GOA电路,在下拉维持电路部分采用高低电位反推设计,并设置依次降低的第一、第二、第三直流恒压低电位、及一直流恒压高电位,能够解决低温多晶硅半导体薄膜晶体管的自身特性对GOA驱动电路的影响,尤其是漏电问题带来的GOA功能性不良;同时解决了目前基于低温多晶硅半导体薄膜晶体管的GOA电路中下拉维持电路部分在非作用期间第二节点电位不能处于较高的电位的问题,有效维持第一节点和输出端的低电位。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其它有益效果显而易见。
附图中,
图1为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的电路图;
图2为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的第一级连接关系的电路图;
图3为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的最后一级连接关系的电路图;
图4为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的第一种波形设置和关键节点的输出波形图;
图5为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的第二种波形设置和关键节点的输出波形图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1-3,本发明提供一种基于低温多晶硅半导体薄膜晶体管的GOA电路。如图1所示,该基于低温多晶硅半导体薄膜晶体管的GOA电路包括:级联的多个GOA单元,设N为正整数,第N级GOA单元包括一上拉控制部分100、一上拉部分200、一第一下拉部分400、和一下拉维持电路部分500;还可包括一上升部分300。
所述上拉控制部分100包括第一晶体管T1,其栅极与源极均电性连接于该第N级GOA单元的上一级第N-1级GOA单元的输出端G(N-1),漏极电性连接于第一节点Q(N)。
所述上拉部分200包括第二晶体管T2,其栅极电性连接于第一节点Q(N),源极电性连接于时钟驱动信号CKN,漏极电性连接于输出端G(N)。
所述上升部分300包括一电容Cb,所述电容Cb的一端电性连接于第一节点Q(N),另一端电性连接于输出端G(N)。
所述下拉维持电路部分500电性连接于所述第一节点Q(N)、输出端G(N)、一直流恒压高电位H、及第一、第二、与第三直流恒压低电位VSS1、VSS2、VSS3。具体的,所述下拉维持电路部分500包括:第三晶体管T3,所述第三晶体管T3的栅极和源极均电性连接于直流恒压高电位H,漏极电性连接于第五晶体管T5的源极;第四晶体管T4,所述第四晶体管T4的栅极电性连接于第三晶体管T3的漏极,源极电性连接于直流恒压高电位H,漏极电性连接于第二节点P(N);第五晶体管T5,所述第五晶体管T5的栅极电性连接于第一节点Q(N),源极电性连接于第三晶体管T3的漏极,漏极电性连接于第一直流恒压低电位VSS1;第六晶体管T6,所述第六晶体管T6的栅极电性连接于第一节点Q(N),源极电性连接于第二节点P(N),漏极电性连接于第八晶体管T8的栅极;第七晶体管T7,所述第七晶体管T7的栅极电性连接于第一节点Q(N),源极电性连接于第二节点P(N),漏极电性连接于第八晶体管T8的源极;第八晶体管T8,所述第八晶体管T8的栅极电性连接于第六晶体管T6的漏极,源极电性连接于第七晶体管T7的漏极,漏极电性连接于第三直流恒压低电位VSS3;第九晶体管T9,所述第九晶体管T9的栅极电性连接于第六晶体管T6的漏极,源极电性连接于第十晶体管T10的栅极,漏极电性连接于第三直流恒压低电位VSS3;第十晶体管T10,所述第十晶体管T10的栅极与源极均电性连接于直流恒压高电位H,漏极电性连接于第七晶体管T7的漏极;第十二晶体管T12,所述第十二晶体管T12的栅极电性连接于第二节点P(N),源极电性连接于第一节点Q(N),漏极电性连接于第二直流恒压低电位VSS2;第十三晶体管T13,所述第十三晶体管T13的栅极电性连接于第二节点P(N),源极电性连接于输出端G(N),漏极电性连接于第一直流恒压低电位VSS1。
所述第一下拉部分400包括一第十四晶体管T14,所述第十四晶体管T14的栅极电性连接于所述第N级GOA单元的下一级第N+1级GOA单元的输出端G(N+1),源极电性连接于第一节点Q(N),漏极电性连接于第二恒压低电位VSS2。
如图2所示,所述GOA电路的第一级连接关系中,第一晶体管T1的栅极与源极均电性连接于电路的启动信号端STV。
如图3所示,所述GOA电路的最后一级连接关系中,第十四晶体管T14的栅极电性连接于电路的启动信号端STV。
需要特别说明的是,本发明基于低温多晶硅半导体薄膜晶体管的GOA电路设置了一个直流恒压高电位H、及三个直流恒压低电位VSS1、VSS2、VSS3,且三个直流恒压低电位依次降低,即,第三直流恒压低电位VSS3<第二直流恒压低电位VSS2<第一直流恒压低电位VSS1,该三个直流恒压低电位VSS1、VSS2、VSS3一般分开独立控制,便于进行不同电位的调节。
所述下拉维持电路部分500采用高低电位反推设计:所述第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7提供正向高电位,用于控制第十二晶体管T12和第十三晶体管T13的打开;所述第八晶体管T8、第九晶体管T9构成作用期间的负电位的反向自举,用于在作用期间将第二节点P(N)拉低至至第三直流恒压低电位VSS3电位,使第十晶体管T10关闭的较好;在非作用期间利用直流恒压高电位H向第二节点P(N)提供适当的高电位,使得第一节点Q(N)与输出端G(N)维持低电位,消除二者的波纹(Ripple)电压。所述第四晶体管T4、第七晶体管T7、与第八晶体管T8串联,能够防止漏电。
具体的,所述下拉维持电路部分500中第三晶体管T3、第四晶体管T4受直流恒压高电位H的控制处于导通状态,在非作用期间,第五晶体管T5、第六晶体管T6、第七晶体管T7截止,由第四晶体管T4向第二节点P(N)提供一直流恒压高电位H,第二节点P(N)为高电位时,第十二晶体管T12、第十三晶体管T13均导通,通过第十二晶体管T12下拉第一节点Q(N)的电位到第二直流恒压低电位VSS2,通过第十三晶体管下拉输出端G(N)的电位到第一直流恒压低电位VSS1;在作用期间,第五晶体管T5、第六晶体管T6、第七晶体管T7的栅极为从第一节点Q(N)传来的高电位,第五晶体管T5、第六晶体管T6、第七晶体管T7均导通,通过第五晶体管T5下拉第四晶体管T4的栅极电位至第一恒压直流低电位VSS1,第四晶体管T4截止,不再向第二节点P(N)提供直流恒压高电位H,同时,第六晶体管T6接收从第二节点P(N)所传来的直流恒压高电位H,并将此直流恒压高电位H传到第八晶体管T8和第九晶体管T9的栅极,此时,第七晶体管T7和第八晶体管T8均导通,通过第七晶体管T7和第八晶体管T8下拉第二节点P(N)的电位到一更低的第三直流恒压低电位VSS3,同时第九晶体管T9也处于导通状态,通过第九晶体管T9下拉第十晶体管的栅极电位至第三直流恒压低电位VSS3,可以使第十晶体管T10关闭的很好。
所述下拉维持电路部分500搭配直流恒压高电位H、及三个直流恒压低电位VSS1、VSS2、VSS3,能够解决低温多晶硅半导体薄膜晶体管的自身的阈值电压较低、亚阈值区域的摆幅较小等特性对GOA驱动电路的影响,尤其是漏电问题带来的GOA功能性不良;同时解决了目前基于低温多晶硅半导体薄膜晶体管的GOA电路中下拉维持电路部分在非作用期间第二节点电位不能处于较高的电位的问题,有效维持第一节点Q(N)和输出端G(N)的低电位。
所述上升部分300用来在作用期间抬升所述第一节点Q(N)的电位。
所述第一下拉部分400用来在非作用期间依据所述第N级GOA单元的下一级第N+1级GOA单元的输出端G(N+1)的输出信号下拉所述第一节点Q(N)的电位至所述第二直流恒压低电位VSS2,可以达到在第一时间下拉第一节点Q(N)的电位目的。
所述GOA电路采用输出端G(N)的输出信号作为上下级传信号,采用第N级GOA单元的上一级第N-1级GOA单元的输出端G(N-1)与第N级GOA单元的输出端G(N)进行上、下级传,能够减少TFT的颗数,达到有效节省布局(Layout)和功耗的目的。
图4、图5分别为两种本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的波形设置和关键节点的输出波形图。图4中所示的时钟驱动信号CKN的波形占空比不同于图5中所示的时钟驱动信号CKN的波形占空比。图4和图5中,CK1N、CK2N分别表示第一条、第二条时钟驱动信号CKN,由图可知,时钟驱动信号CKN的波形占空比均小于50/50;所述第一节点Q(N)的信号输出波形呈“凸”字形,所述输出端G(N)正常输出。
综上所述,本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路,在下拉维持电路部分采用高低电位反推设计,并设置依次降低的第一、第二、第三直流恒压低电位、及一直流恒压高电位,能够解决低温多晶硅半导体薄膜晶体管的自身特性对GOA驱动电路的影响,尤其是漏电问题带来的GOA功能性不良;同时解决了目前基于低温多晶硅半导体薄膜晶体管的GOA电路中下拉维持电路部分在非作用期间第二节点电位不能处于较高的电位的问题,有效维持第一节点和输出端的低电位。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明权利要求的保护范围。
Claims (9)
1.一种基于低温多晶硅半导体薄膜晶体管的GOA电路,其特征在于,包括级联的多个GOA单元,设N为正整数,第N级GOA单元包括一上拉控制部分(100)、一上拉部分(200)、一第一下拉部分(400)、和一下拉维持电路部分(500);
所述上拉控制部分(100)包括第一晶体管(T1),其栅极与源极均电性连接于该第N级GOA单元的上一级第N-1级GOA单元的输出端(G(N-1)),漏极电性连接于第一节点(Q(N));
所述上拉部分(200)包括第二晶体管(T2),其栅极电性连接于第一节点(Q(N)),源极电性连接于时钟驱动信号(CKN),漏极电性连接于输出端(G(N));
所述下拉维持电路部分(500)电性连接于所述第一节点(Q(N))、输出端(G(N))、一直流恒压高电位(H)、及第一、第二、与第三直流恒压低电位(VSS1、VSS2、VSS3);
所述下拉维持电路部分(500)采用高低电位反推设计,包括:
第三晶体管(T3),所述第三晶体管(T3)的栅极和源极均电性连接于直流恒压高电位(H),漏极电性连接于第五晶体管(T5)的源极;
第四晶体管(T4),所述第四晶体管(T4)的栅极电性连接于第三晶体管(T3)的漏极,源极电性连接于直流恒压高电位(H),漏极电性连接于第二节点(P(N));
第五晶体管(T5),所述第五晶体管(T5)的栅极电性连接于第一节点(Q(N)),源极电性连接于第三晶体管(T3)的漏极,漏极电性连接于第一直流恒压低电位(VSS1);
第六晶体管(T6),所述第六晶体管(T6)的栅极电性连接于第一节点(Q(N)),源极电性连接于第二节点(P(N)),漏极电性连接于第八晶体管(T8)的栅极;
第七晶体管(T7),所述第七晶体管(T7)的栅极电性连接于第一节点(Q(N)),源极电性连接于第二节点(P(N)),漏极电性连接于第八晶体管(T8)的源极;
第八晶体管(T8),所述第八晶体管(T8)的栅极电性连接于第六晶体管(T6)的漏极,源极电性连接于第七晶体管(T7)的漏极,漏极电性连接于第三直流恒压低电位(VSS3);
第九晶体管(T9),所述第九晶体管(T9)的栅极电性连接于第六晶体管(T6)的漏极,源极电性连接于第十晶体管(T10)的栅极,漏极电性连接于第三直流恒压低电位(VSS3);
第十晶体管(T10),所述第十晶体管(T10)的栅极与源极均电性连接于直流恒压高电位(H),漏极电性连接于第七晶体管(T7)的漏极;
第十二晶体管(T12),所述第十二晶体管(T12)的栅极电性连接于第二节点(P(N)),源极电性连接于第一节点(Q(N)),漏极电性连接于第二直流恒压低电位(VSS2);
第十三晶体管(T13),所述第十三晶体管(T13)的栅极电性连接于第二节点(P(N)),源极电性连接于输出端(G(N)),漏极电性连接于第一直流恒压低电位(VSS1);
所述第三晶体管(T3)、第四晶体管(T4)、第五晶体管(T5)、第六晶体管(T6)、第七晶体管(T7)提供正向高电位,用于控制第十二晶体管(T12)和第十三晶体管(T13)的打开;所述第八晶体管(T8)、第九晶体管(T9)构成作用期间的负电位的反向自举,用于在作用期间向第二节点(P(N))提供更低电位;利用直流恒压高电位(H)在非作用期间向第二节点(P(N))提供适当的高电位,使得第一节点(Q(N))与输出端(G(N))维持低电位;
所述第一下拉部分(400)电性连接于所述第一节点(Q(N))、所述第N级GOA单元的下一级第N+1级GOA单元的输出端(G(N+1))及第二直流恒压低电位(VSS2),所述第一下拉部分(400)依据所述第N级GOA单元的下一级第N+1级GOA单元的输出端(G(N+1))的输出信号下拉所述第一节点(Q(N))的电位至所述第二直流恒压低电位(VSS2);
所述第一下拉部分(400)包括一第十四晶体管(T14),所述第十四晶体管(T14)的栅极电性连接于所述第N级GOA单元的下一级第N+1级GOA单元的输出端(G(N+1)),源极电性连接于第一节点(Q(N)),漏极电性连接于第二直流恒压低电位(VSS2);
所述第三直流恒压低电位(VSS3)<第二直流恒压低电位(VSS2)<第一直流恒压低电位(VSS1)。
2.如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路,其特征在于,所述第四晶体管(T4)、第七晶体管(T7)、与第八晶体管(T8)串联。
3.如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路,其特征在于,还包括一上升部分(300),所述上升部分(300)电性连接于所述第一节点(Q(N))与输出端(G(N))之间,用来抬升所述第一节点(Q(N))的电位。
4.如权利要求3所述的基于低温多晶硅半导体薄膜晶体管的GOA电路,其特征在于,所述上升部分(300)包括一电容(Cb),所述电容(Cb)的一端电性连接于第一节点(Q(N)),另一端电性连接于输出端(G(N))。
5.如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路,其特征在于,所述时钟驱动信号(CKN)波形占空比小于50/50。
6.如权利要求4所述的基于低温多晶硅半导体薄膜晶体管的GOA电路,其特征在于,所述第一节点(Q(N))的信号输出波形呈“凸”字形。
7.如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路,其特征在于,所述GOA电路的第一级连接关系中,第一晶体管(T1)的栅极与源极均电性连接于电路的启动信号端(STV)。
8.如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路,其特征在于,所述GOA电路的最后一级连接关系中,第十四晶体管(T14)的栅极电性连接于电路的启动信号端(STV)。
9.如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路,其特征在于,所述GOA电路采用输出端(G(N))的输出信号作为上下级传信号。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410609193.0A CN104464657B (zh) | 2014-11-03 | 2014-11-03 | 基于低温多晶硅半导体薄膜晶体管的goa电路 |
GB1703517.1A GB2548019B (en) | 2014-11-03 | 2015-02-06 | GOA circuit based on LTPS semiconductor TFT |
KR1020177006254A KR101943234B1 (ko) | 2014-11-03 | 2015-02-06 | 저온 폴리 실리콘 반도체 박막 트랜지스터 기반 goa회로 |
US14/422,689 US9552788B2 (en) | 2014-11-03 | 2015-02-06 | GOA circuit based on LTPS semiconductor TFT |
PCT/CN2015/072353 WO2016070508A1 (zh) | 2014-11-03 | 2015-02-06 | 基于低温多晶硅半导体薄膜晶体管的goa电路 |
JP2017522851A JP6579668B2 (ja) | 2014-11-03 | 2015-02-06 | 低温ポリシリコン半導体薄膜トランジスタに基づくgoa回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410609193.0A CN104464657B (zh) | 2014-11-03 | 2014-11-03 | 基于低温多晶硅半导体薄膜晶体管的goa电路 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104464657A true CN104464657A (zh) | 2015-03-25 |
CN104464657B CN104464657B (zh) | 2017-01-18 |
Family
ID=52910614
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410609193.0A Expired - Fee Related CN104464657B (zh) | 2014-11-03 | 2014-11-03 | 基于低温多晶硅半导体薄膜晶体管的goa电路 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9552788B2 (zh) |
JP (1) | JP6579668B2 (zh) |
KR (1) | KR101943234B1 (zh) |
CN (1) | CN104464657B (zh) |
GB (1) | GB2548019B (zh) |
WO (1) | WO2016070508A1 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018040388A1 (zh) * | 2016-08-31 | 2018-03-08 | 深圳市华星光电技术有限公司 | 一种栅极驱动电路 |
CN110097861A (zh) * | 2019-05-20 | 2019-08-06 | 深圳市华星光电半导体显示技术有限公司 | 可降低漏电流的栅极驱动电路及其显示器 |
US10453410B2 (en) * | 2016-08-31 | 2019-10-22 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Gate driving circuit |
CN111145680A (zh) * | 2020-02-24 | 2020-05-12 | Tcl华星光电技术有限公司 | 驱动电路及显示面板 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106205538A (zh) * | 2016-08-31 | 2016-12-07 | 深圳市华星光电技术有限公司 | 一种goa驱动单元及驱动电路 |
US20200035179A1 (en) * | 2018-07-26 | 2020-01-30 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Liquid crystal panel including goa circuit and driving method thereof |
CN111754950A (zh) * | 2020-07-10 | 2020-10-09 | 武汉华星光电技术有限公司 | Goa电路、显示面板和显示装置 |
US11238823B1 (en) | 2020-07-30 | 2022-02-01 | Wuhan China Star Optoelectronics Technology Co., Ltd. | GOA circuit, display panel and display device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100207928A1 (en) * | 2009-02-19 | 2010-08-19 | Jae-Hoon Lee | Gate Driving Circuit and Display Device Having the Gate Driving Circuit |
CN103208262A (zh) * | 2012-01-12 | 2013-07-17 | 三星电子株式会社 | 栅极驱动电路以及具有栅极驱动电路的显示装置 |
CN104050941A (zh) * | 2014-05-27 | 2014-09-17 | 深圳市华星光电技术有限公司 | 一种栅极驱动电路 |
CN104064159A (zh) * | 2014-07-17 | 2014-09-24 | 深圳市华星光电技术有限公司 | 具有自我补偿功能的栅极驱动电路 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI398852B (zh) * | 2008-06-06 | 2013-06-11 | Au Optronics Corp | 可降低時脈偶合效應之移位暫存器及移位暫存器單元 |
TWI400686B (zh) * | 2009-04-08 | 2013-07-01 | Au Optronics Corp | 液晶顯示器之移位暫存器 |
KR101573460B1 (ko) | 2009-04-30 | 2015-12-02 | 삼성디스플레이 주식회사 | 게이트 구동회로 |
TWI511459B (zh) * | 2012-10-11 | 2015-12-01 | Au Optronics Corp | 可防止漏電之閘極驅動電路 |
KR20140057794A (ko) * | 2012-11-05 | 2014-05-14 | 삼성디스플레이 주식회사 | 게이트 구동 회로, 이를 이용한 표시 패널 구동 방법 및 이를 포함하는 표시 장치 |
JP2014206616A (ja) * | 2013-04-12 | 2014-10-30 | 株式会社ジャパンディスプレイ | ゲート信号線駆動回路及び表示装置 |
CN103680451B (zh) * | 2013-12-18 | 2015-12-30 | 深圳市华星光电技术有限公司 | 用于液晶显示的goa电路及显示装置 |
CN103680386B (zh) * | 2013-12-18 | 2016-03-09 | 深圳市华星光电技术有限公司 | 用于平板显示的goa电路及显示装置 |
CN103680388B (zh) * | 2013-12-26 | 2015-11-11 | 深圳市华星光电技术有限公司 | 用于平板显示的可修复的goa电路及显示装置 |
CN104008742B (zh) * | 2014-05-20 | 2016-06-29 | 深圳市华星光电技术有限公司 | 一种扫描驱动电路及一种液晶显示装置 |
US9418613B2 (en) * | 2014-11-03 | 2016-08-16 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | GOA circuit of LTPS semiconductor TFT |
US9407260B2 (en) * | 2014-11-03 | 2016-08-02 | Shenzhen China Star Optoelectronics Technology Co., Ltd | GOA circuit based on LTPS semiconductor TFT |
US9390674B2 (en) * | 2014-11-03 | 2016-07-12 | Shenzhen China Star Optoelectronics Technology Co., Ltd | GOA circuit based on LTPS semiconductor TFT |
CN104464662B (zh) * | 2014-11-03 | 2017-01-25 | 深圳市华星光电技术有限公司 | 基于低温多晶硅半导体薄膜晶体管的goa电路 |
CN104409058B (zh) * | 2014-11-14 | 2017-02-22 | 深圳市华星光电技术有限公司 | 一种扫描驱动电路 |
-
2014
- 2014-11-03 CN CN201410609193.0A patent/CN104464657B/zh not_active Expired - Fee Related
-
2015
- 2015-02-06 GB GB1703517.1A patent/GB2548019B/en not_active Expired - Fee Related
- 2015-02-06 US US14/422,689 patent/US9552788B2/en active Active
- 2015-02-06 KR KR1020177006254A patent/KR101943234B1/ko active IP Right Grant
- 2015-02-06 WO PCT/CN2015/072353 patent/WO2016070508A1/zh active Application Filing
- 2015-02-06 JP JP2017522851A patent/JP6579668B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100207928A1 (en) * | 2009-02-19 | 2010-08-19 | Jae-Hoon Lee | Gate Driving Circuit and Display Device Having the Gate Driving Circuit |
CN103208262A (zh) * | 2012-01-12 | 2013-07-17 | 三星电子株式会社 | 栅极驱动电路以及具有栅极驱动电路的显示装置 |
CN104050941A (zh) * | 2014-05-27 | 2014-09-17 | 深圳市华星光电技术有限公司 | 一种栅极驱动电路 |
CN104064159A (zh) * | 2014-07-17 | 2014-09-24 | 深圳市华星光电技术有限公司 | 具有自我补偿功能的栅极驱动电路 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018040388A1 (zh) * | 2016-08-31 | 2018-03-08 | 深圳市华星光电技术有限公司 | 一种栅极驱动电路 |
US10453410B2 (en) * | 2016-08-31 | 2019-10-22 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Gate driving circuit |
US10460689B2 (en) | 2016-08-31 | 2019-10-29 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Gate driving circuit |
CN110097861A (zh) * | 2019-05-20 | 2019-08-06 | 深圳市华星光电半导体显示技术有限公司 | 可降低漏电流的栅极驱动电路及其显示器 |
WO2020232781A1 (zh) * | 2019-05-20 | 2020-11-26 | 深圳市华星光电半导体显示技术有限公司 | 可降低漏电流的栅极驱动电路及其显示器 |
CN111145680A (zh) * | 2020-02-24 | 2020-05-12 | Tcl华星光电技术有限公司 | 驱动电路及显示面板 |
CN111145680B (zh) * | 2020-02-24 | 2021-07-27 | 苏州华星光电技术有限公司 | 驱动电路及显示面板 |
US11610525B2 (en) | 2020-02-24 | 2023-03-21 | Tcl China Star Optoelectronics Technology Co., Ltd. | Driving circuit and display panel |
Also Published As
Publication number | Publication date |
---|---|
CN104464657B (zh) | 2017-01-18 |
WO2016070508A1 (zh) | 2016-05-12 |
JP6579668B2 (ja) | 2019-09-25 |
US9552788B2 (en) | 2017-01-24 |
US20160343321A1 (en) | 2016-11-24 |
GB201703517D0 (en) | 2017-04-19 |
KR20170038925A (ko) | 2017-04-07 |
GB2548019B (en) | 2020-11-04 |
GB2548019A (en) | 2017-09-06 |
KR101943234B1 (ko) | 2019-01-28 |
JP2018503109A (ja) | 2018-02-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104464662A (zh) | 基于低温多晶硅半导体薄膜晶体管的goa电路 | |
CN104464656A (zh) | 基于低温多晶硅半导体薄膜晶体管的goa电路 | |
CN104464657A (zh) | 基于低温多晶硅半导体薄膜晶体管的goa电路 | |
CN104464660A (zh) | 基于低温多晶硅半导体薄膜晶体管的goa电路 | |
CN104157259B (zh) | 基于igzo制程的栅极驱动电路 | |
CN103151010B (zh) | 一种移位寄存器和显示装置 | |
WO2016037380A1 (zh) | 基于igzo制程的栅极驱动电路 | |
CN104795034A (zh) | 一种goa电路及液晶显示器 | |
CN105469760A (zh) | 基于ltps半导体薄膜晶体管的goa电路 | |
CN104464661A (zh) | 基于低温多晶硅半导体薄膜晶体管的goa电路 | |
CN113096606B (zh) | Goa电路、显示面板及电子装置 | |
CN104464658A (zh) | 基于低温多晶硅半导体薄膜晶体管的goa电路 | |
KR101818673B1 (ko) | 액정 표시 장치의 직류 전압 변환 회로 | |
Park et al. | 48.3 WITHDRAWN 48.4: Invited Paper: Driving Circuit Integration Using Depletion‐Mode Oxide TFTs |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170118 |
|
CF01 | Termination of patent right due to non-payment of annual fee |