CN104428889A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
- Publication number
- CN104428889A CN104428889A CN201280074595.4A CN201280074595A CN104428889A CN 104428889 A CN104428889 A CN 104428889A CN 201280074595 A CN201280074595 A CN 201280074595A CN 104428889 A CN104428889 A CN 104428889A
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- resin bed
- semiconductor element
- semiconductor device
- stress buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 178
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 229920005989 resin Polymers 0.000 claims abstract description 157
- 239000011347 resin Substances 0.000 claims abstract description 157
- 238000005520 cutting process Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims description 40
- 239000000463 material Substances 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 10
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 229920001187 thermosetting polymer Polymers 0.000 claims description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims 1
- 230000035882 stress Effects 0.000 abstract description 59
- 238000007789 sealing Methods 0.000 abstract description 18
- 230000008646 thermal stress Effects 0.000 abstract description 10
- 239000000853 adhesive Substances 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 150000001875 compounds Chemical class 0.000 abstract 1
- 238000005336 cracking Methods 0.000 abstract 1
- 238000005192 partition Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 35
- 238000012360 testing method Methods 0.000 description 12
- 230000004087 circulation Effects 0.000 description 9
- 230000000903 blocking effect Effects 0.000 description 8
- 238000000465 moulding Methods 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 7
- 239000000945 filler Substances 0.000 description 7
- 230000009471 action Effects 0.000 description 6
- 241000446313 Lamella Species 0.000 description 5
- 208000013201 Stress fracture Diseases 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000004952 Polyamide Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229920002647 polyamide Polymers 0.000 description 4
- 238000005382 thermal cycling Methods 0.000 description 4
- 239000004925 Acrylic resin Substances 0.000 description 3
- 229920000178 Acrylic resin Polymers 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 description 3
- 229910052582 BN Inorganic materials 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000006061 abrasive grain Substances 0.000 description 2
- 230000004523 agglutinating effect Effects 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000004378 air conditioning Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910002026 crystalline silica Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005323 electroforming Methods 0.000 description 1
- 238000007610 electrostatic coating method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000005350 fused silica glass Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229920006015 heat resistant resin Polymers 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052500 inorganic mineral Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005461 lubrication Methods 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical class C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 239000011707 mineral Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73263—Layer and strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/8484—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Dicing (AREA)
Abstract
在半导体基板上形成多个电力控制用半导体元件,在划分相邻的半导体元件的带状的切割区域相交叉的交叉区域中,形成覆盖交叉区域的应力缓冲树脂层(7),切割交叉区域而切断应力缓冲树脂层(7)来将半导体元件单片化。由此,获得在使用了SiC等化合物半导体基板的半导体元件中与密封树脂的粘接力高、不易由于动作时的热应力而引起密封树脂的裂痕、剥离的半导体装置。
Description
技术领域
本发明涉及一种具有用于电力控制的功率半导体元件的半导体装置及其制造方法。
背景技术
电力控制用的半导体元件还被称为功率半导体元件,使用了该半导体元件的电力控制用的半导体装置有时还被称为功率模块。电力控制用的半导体装置具有进行较大电流的控制的功能,用于马达等的控制装置中。作为电力控制用的半导体装置,使用了将半导体元件用环氧树脂等热硬化性树脂密封了的模塑密封型(molding-sealed)的半导体装置、和用胶树脂密封了的胶密封型(gel-sealed)的半导体装置。特别是,模塑密封型的半导体装置小型且可靠性优良、处理容易,因此广泛用于空调设备的控制等中。另外,近年来还用于进行马达驱动的汽车的动力控制等中。
模塑密封型的半导体装置首先进行将半导体元件固定到框架的芯片焊接(die bond),接着直接布线到引线或者通过导线布线到分别对应的引线部来组装。半导体元件是将薄板状的晶体晶片切断为四边形而单片化的半导体元件,因此还被称为半导体芯片。在布线后,通过传递模塑(transfer molding)、灌封(potting)等方法用环氧树脂等密封树脂进行成形密封。在上述半导体装置中,以半导体芯片与密封树脂(模塑树脂)的热膨胀系数的差异、密封用树脂的硬化收缩为起因,在半导体芯片中产生热应力。在半导体装置的动作中,重复向半导体元件的断续的通电,因此半导体元件每次通电时重复温度上升和温度下降的温度循环。因此,如果由于上述热应力而在密封树脂与半导体芯片的粘接界面中产生缺陷,产生树脂的剥离、微小裂痕,则有绝缘耐压劣化、或元件的特性变动等而可靠性下降的担心。另外,即使在不至于剥离的情况下,有时也产生半导体芯片的布线变形、破损。上述热应力在半导体芯片的端部中成为最大,因此在大多数的情况下树脂的剥离从半导体芯片端部开始发展。
在以往的半导体装置中,在散热器、半导体芯片、电极块等与布线有关的配件的表面整体涂敷聚酰胺树脂来提高了与密封树脂的紧贴性(例如,参照专利文献1)。
同样地,将配件(收纳部件)的表面用聚酰亚胺系或者聚酰胺酰亚胺系的覆盖树脂来薄薄地覆盖,从其上填充密封树脂进行硬化,实现了耐温循环性、抗湿性的改善(例如,参照专利文献2)。
专利文献1:日本特开2003-124406号公报
专利文献2:日本特开2006-32617号公报
发明内容
在以往的半导体装置中,对完成了芯片焊接、布线等的配件覆盖了树脂层,因此在复杂形状的配件表面难以使树脂层的厚度均匀。例如想要使厚度为10μm以下地薄薄地涂敷时,有时形成了局部厚的部分、或产生没有被涂敷的区域。由于树脂层的不均匀,起不到热应力的缓冲作用,随着温度循环历史累积而产生模塑树脂的剥离。
本发明是为了解决如上所述的课题而作出的,其目的在于获得一种模塑树脂与半导体元件的粘接可靠性优良的半导体装置及其制造方法。
在本发明的半导体装置的制造方法中,包括如下工序:在半导体基板形成多个半导体元件;在划分相邻的半导体元件的带状的切割区域相交叉的交叉区域中,形成覆盖半导体基板上的树脂层;切割交叉区域而切断树脂层;切割树脂层间的切割区域;在通过切割而单片化了的半导体元件进行布线;以及将布线了的所述半导体元件用热硬化性树脂进行密封。
在元件的四角成了应力缓冲树脂层,因此抑制在动作时的温度循环中产生的热应力引起的剥离,能够获得模塑树脂与半导体元件的粘接可靠性优良的半导体装置。
附图说明
图1是本发明的实施方式1的半导体装置中的半导体元件的立体图。
图2是本发明的实施方式1的半导体装置中的半导体元件的俯视图。
图3是表示本发明的实施方式1的半导体装置的结构例的截面图。
图4是表示半导体基板的例子的俯视图。
图5是表示本发明的实施方式1的半导体元件的第1制造方法的俯视图。
图6是表示本发明的实施方式1的半导体元件的第1制造方法的截面图。
图7是表示本发明的实施方式1的半导体元件的第1制造方法的截面图。
图8是表示本发明的实施方式1的半导体元件的制造方法的截面图。
图9是表示本发明的实施方式2的半导体元件的制造方法的俯视图。
图10是表示本发明的实施方式2的半导体元件的俯视图。
图11是表示本发明的实施方式3的半导体元件的制造方法的俯视图。
图12是表示本发明的实施方式3的半导体元件的俯视图。
附图标记说明
1:主电极1;2:绝缘树脂层2;3:基板表面3;7:应力缓冲树脂层7;S:半导体基板S;PD:半导体元件;104:接合材料;110:散热器;111:绝缘薄片;112、113:引线部件。
具体实施方式
实施方式1.
图1是本发明的实施方式1中的电力控制用半导体装置中的电力控制用的半导体元件PD的立体图,示意性地表示了半导体元件PD的上面侧的结构。半导体元件PD是形成于晶片状的半导体基板之后从半导体基板切割成四边形而单片化了的元件。在图1中,形成在半导体基板S上的主电极1成为进行基于半导体元件PD的电力控制的主电流的路径。在半导体元件PD的背面侧形成极性与主电极1不同的背面电极。为了确保背面电极与主电极1的绝缘耐压,形成了覆盖主电极1的外周端部的绝缘树脂层2。绝缘树脂层2由聚酰亚胺或者聚酰胺等耐热性树脂材料构成。在成为半导体基板S表面的最外周的一部分的四角区域形成了应力缓冲树脂层7。应力缓冲树脂层7的一部分也可以覆盖绝缘树脂层2。
图2是实施方式1的半导体装置中的半导体元件的俯视图。为了防止在切割时刀片的堵塞,避开晶片状态下的切割区域而形成绝缘树脂层2。因而,绝缘树脂层2的外周侧不到达半导体基板S的端部,半导体基板S上的四边附近区域暴露着。另一方面,在形成了应力缓冲树脂层7的四角区域中,覆盖了半导体基板S的端部表面。为了提高生产率,应力缓冲树脂层7的涂敷希望是在从晶片切出半导体元件PD之前统一形成在晶片上形成的元件群中。
然而,当进行如上所述的统一形成时,产生如下问题。一般,当切断形成有如树脂那样的软质层的晶片时,在切割刀片附着、堆积有软质层的形成物,产生刀片的孔眼堵塞。刀片的孔眼堵塞招致切断应力的下降,有时还成为被称为崩裂(chipping)的元件的小裂痕的原因。为了防止在切断应力缓冲树脂层7时刀片的孔眼堵塞,要求1边上的两个应力缓冲树脂层7的宽度w1、w2的合计值为每个元件的半导体基板S的1边的长度wS的5%以下。如果在该范围内,则应力缓冲树脂层7成为散布在切割线上的形状、且相对于固定切割长度成为足够小的比例,因此在进行切割的过程中能够实现刀片的自清洁,孔眼堵塞的问题几乎消除。考虑自清洁的作用通过被研磨的基板的切屑进入磨石间而排出树脂来体现。
另外,为了具有密封树脂引起的热应力的应力缓冲作用,需要应力缓冲树脂层7的宽度为边的长度wS的0.73%以上。关于这些数值例将后述。
当参照图2以式子表示上述的条件时,成为如下:
0.05wS≥w1+w2
w1≥0.00365wS
w2≥0.00365wS (式1)
同样地,
0.05dS≥d2+d3
d1≥0.00365dS
d2≥0.00365dS (式2)
半导体元件PD接合在框架等通电部件,并且在主电极1接合引线部件而构成框架配件。框架配件以由环氧树脂等构成的热硬化性的密封树脂进行密封。
图3是表示本发明的实施方式1的半导体装置的结构例的截面图,两个功率半导体元件PD1以及PD2被并联连接。半导体元件PD1、PD2的表面结构与图1、图2相同,主电极经由接合材料104连接在引线部件112。在半导体元件PD1、PD2的背面侧,没有图示的背面电极经由接合材料105接合到兼作通电部件的散热器110。这些配件被模塑树脂R进行密封而构成了半导体装置。此外,也可以在散热器110的背面粘贴由绝缘性部件构成的绝缘薄片111来实现散热器110的绝缘。散热器110连接在引线部件113并被通电。引线部件112、113的非密封部成为外部端子,成为用于连接到外部电路的引线。
已知使用了SiC(碳化硅)、GaN(氮化镓)等带隙大于Si(硅)的半导体基板的半导体元件与Si的半导体元件相比动作温度的上限极高。例如,就装载了SiC的半导体芯片的功率模块而言,有时还在动作时的半导体芯片温度超过150℃的高温下使用、例如在200℃的状态下使用。当提高半导体芯片的动作温度时,与常温的温差变大,因此与密封树脂的粘接界面的热应力进一步变大,具有粘接界面的劣化变得显著的倾向。
也包含Si在内,通常在半导体晶片的切断时,使用以金刚石粒子、立方晶体氮化硼等为磨粒的电铸刀片。在半导体基板为SiC的情况下,SiC极硬,因此希望是如刀片的磨粒密度占磨粒层的体积比率超过20%那样的高集中度刀片。但是,由于磨粒的集中度高,容易产生切断树脂层时的孔眼堵塞,由于使用产生了孔眼堵塞的刀片,产生崩裂、刀片的破损多发的问题。
接着,说明应力缓冲树脂层的形成方法。图4是表示应力缓冲树脂层7形成前的半导体基板的例子的俯视图。多个主电极1以固定间隔配置成矩阵状,以覆盖各主电极1的外周端4的方式配置了绝缘树脂层2。绝缘树脂层2成为四边形的框状的形状,以覆盖其四角的方式形成了应力缓冲树脂层7。绝缘树脂层2在前面覆盖后通过光刻的工序制作图案。在形成了包围主电极1的外周的保护环的情况下,绝缘树脂层2连保护环也覆盖。在绝缘树脂层2中使用绝缘性优良的聚酰亚胺树脂等。绝缘树脂层2间是纵横地带状延伸的能够切割的区域,这里称为切割区域DA。
图5是表示实施方式1的半导体元件的第1制造方法的俯视图,表示切割前的半导体基板S的表面结构。图5的结构是将上述的切割区域DA交叉的区域用应力缓冲树脂层7单独地覆盖而成的结构,应力缓冲树脂层7的各个配置成占据相邻的半导体元件的四角中的一角。相邻的应力缓冲树脂层7之间暴露出基板表面3。因此,当图5的纵向或横方向地进行切割时,随着切割刀片以固定的速度行进,将交替地切断被应力缓冲树脂层7覆盖的交叉区域、和没有被应力缓冲树脂层7覆盖的区域。此外,在基板表面3的区域也可以形成对切割没有影响的薄膜等。切割后的切截面6的假想位置以单点划线表示。
图6是表示实施方式1的半导体元件的制造方法的截面图,示意性地表示图5的线段ab处的切断截面。绝缘树脂层2覆盖主电极1的外周端4而形成。绝缘树脂层2在形成主电极1之后暂时涂敷到半导体基板S表面整体,之后通过光刻的方法形成为框状。
绝缘树脂层的涂敷方法能够使用旋涂、喷涂等。所形成的图案覆盖主电极1以及包围主电极1的保护环而形成。
间隙G是相邻的绝缘树脂层2间的距离,实际上是50~200μm。实质性地,间隙G成为可切割区域的宽度。图7是表示实施方式1的半导体元件中的第1制造方法的截面图,示意性地表示在图6的截面中进行了切割的状态。在切割工序中对每个半导体元件PD切断半导体基板S,形成切割沟5而分离。
切割沟5的宽度根据切割方法而不同。在切割中产生的切截面6是半导体元件PD的外周端部。
图8是表示实施方式1的半导体元件的第1制造方法的截面图,示意性地表示图5的线段cd处的切断截面。应力缓冲树脂层7从绝缘树脂层2的端部上连续地覆盖绝缘树脂层2间的半导体基板S表面。
应力缓冲树脂层7在形成绝缘树脂层2后涂敷到半导体基板S表面整体,之后通过光刻的方法形成为框状。如果应力缓冲树脂层7中使用具有感光性的材料,则能够直接对应力缓冲树脂层7形成图案。在应力缓冲树脂层7为非感光性的情况下,另外通过抗蚀剂涂敷、曝光显像、蚀刻、抗蚀剂去除的工序来加工成所期望的图案。
应力缓冲树脂层7也可以是与绝缘树脂层相同的材料,但是也能够应用耐压低于绝缘树脂层的树脂,因此能够使用聚酰亚胺、聚酰胺系树脂、丙烯酸树脂、硅酮树脂、倍半硅氧烷(silsesquioxane)系树脂、硅醇(silanol)系树脂等。
通过在切割工序中切断应力缓冲树脂层7,成为断开的应力缓冲树脂层7覆盖了半导体元件PD表面的四角的形态。
只要绝缘树脂层具有所期望的绝缘耐性就没有特别限定,可以使用聚酰亚胺、高耐压丙烯酸树脂等。
应力缓冲树脂层7也可以是与绝缘树脂层相同的材料,但能够应用绝缘耐性低于绝缘树脂层的树脂,因此即使是不适于作为绝缘树脂层的材料也能够使用。例如能够将聚酰亚胺、聚酰胺系树脂、丙烯酸树脂、硅酮树脂、倍半硅氧烷系树脂、硅醇系树脂等用于应力缓冲树脂层7。另外,用于应力缓冲树脂层的树脂还能够使用混合多种树脂、或添加填充物而调整了弹性率的树脂。
当应力缓冲树脂层7的膜厚超过固定的厚度时,即使使用本实施方式的方法也会产生切割刀片的孔眼堵塞而产生崩裂、裂痕。因此,应力缓冲树脂层7的膜厚需要在15微米以下,希望是3微米以下。
在构成电路基板的各部件中,以SiC为基板的半导体元件的线膨胀系数是3~5ppm/K,如果端子部件、布线部件是铜则线膨胀系数是17ppm/K,如果端子部件、布线部件是铝则线膨胀系数是23ppm/K。绝缘薄片有效地对从半导体元件发出的热进行散热,因此通过向环氧树脂等树脂中将导热性优良的无机粉末填充物以70vol%左右的高充填率进行填充来提高导热性、且将线膨胀系数抑制为10~20ppm左右。
作为填充到密封树脂、覆盖树脂中的填充物,优选使用绝缘性的填充物。作为绝缘性的填充物,使用熔融二氧化硅等线膨胀系数小的无机粉末、导热性优良的氧化铝等,但是除此之外还能够使用晶体二氧化硅、玻璃、氮化硼、氮化铝、碳化硅、天然矿物系材料等。能够根据着色用、粘度调整用、润滑用等所需用途来选择粒径范围、形状,因此也可以组合使用多个种类的填充物。
引线部件使用导线状或板状的部件,作为材质优选导电性高的铝、铜等部件。
在具有如上所述结构的半导体装置中,在被密封树脂密封的状态下,应力缓冲树脂层7存在于对半导体元件PD施加最大热应力的四角的界面,因此能够抑制以动作时、可靠性评价的热为起因的密封树脂与半导体元件的剥离、裂痕。由此,能够维持半导体元件PD的绝缘性能,并且保护半导体元件PD表面,因此能够获得可靠性优良的半导体装置。
实施方式2.
图9是表示本发明的实施方式2的半导体元件中的制造方法的俯视图。如图9所示,形成在切割区域DA的交叉区域中的应力缓冲树脂层7成为圆形这点与实施方式1不同。该结构也能够使用实施方式1的方法来实现,但是这里与光刻不同而以使用滴涂(dispensing)法、静电涂敷法、喷墨法等来形成应力缓冲树脂层7为前提。这些形成方法难以形成如四边形那样的形状,但是如果是大致圆形的图案则是恰当的方法。通过使用这些形成方法,能够降低树脂的使用量,能够抑制成本上升。
图10是表示实施方式2的半导体元件的俯视图。在半导体元件PD的四角配置了扇状的应力缓冲树脂层7。即使应力缓冲树脂层7是大致圆形,也能够覆盖切割后的半导体元件PD的四角区域,因此能够通过使用这些简便且较廉价的工序来获得生产率优良的半导体装置。
此外,如果应力缓冲树脂层7的形成方法是能够在所期望的地方形成图案的方法则没有特别限定。
通过应力缓冲树脂层7,抑制密封树脂与半导体元件的剥离、裂痕,能够获得可靠性优良的半导体装置。
实施方式3.
图11是表示实施方式3中的半导体元件的制造方法的俯视图。在切割前的半导体基板上使用兼作绝缘树脂层和应力缓冲树脂层的树脂,使用光刻工序来形成图11的图案。通过将应力缓冲树脂层7兼作为保护环上的绝缘树脂层2,能够同时统一地形成绝缘树脂层和应力缓冲树脂层。
图12是表示实施方式3的半导体元件的俯视图。切割的结果,能够获得四角被以与绝缘树脂层相同材料的、连续的应力缓冲树脂层覆盖的半导体元件PD。通过应力缓冲树脂层7,抑制密封树脂和半导体元件的剥离、裂痕,能够获得可靠性优良的半导体装置。
通过省掉单独形成应力缓冲树脂层7的工序而成为简便且廉价的工序,能够获得生产率优良的半导体装置。
此外,关于切割,一般是用切割刀片机械地进行切断的方法,但是能够使用并用切割刀片和超声波的方法、使用激光的激光切割法等。在激光切割中,在以激光束来使半导体基板S内部多晶化的方法中,使用限定在半导体芯片的四角的应力缓冲树脂层也是有益的。即,因为通过极力地限定应力缓冲树脂层的宽度,能够在切割区域的大部分区域照射激光束,因此施加外力时能够实现直线的龟裂发展。另外,也可以在通过激光对划线区域进行多晶化后形成应力缓冲树脂层,通过外力或者热应力来分割半导体芯片。在这种情况下,通过限定应力缓冲树脂层的宽度来平稳地进行芯片分割,因此能够高效进行切割。
实施例
制作使用了图3所示的半导体装置PM的结构的半导体装置,进行了可靠性评价。在半导体装置PM中,将焊料或者烧结性银颗粒材料等用作接合材料来将散热器110与半导体元件、以及半导体元件进行接合。这里,使用烧结性银颗粒来进行了制作。在散热器的另一个面接合了在背面粘贴了金属箔的绝缘薄片。
半导体元件例如使用了被称为IGBT(Insulated Gate BipolarTransistor:绝缘栅双极性晶体管)、MOSFET(Metal OxideSemiconductor Field Effect Transistor:金属氧化物场效应晶体管)的开关元件、肖特基-势垒二极管等整流元件。在使用MOSFET的情况下,在引线部件侧形成了源极电极、栅极电极以及保护环。在散热器侧形成了漏极电极。导通主电流的引线部件被接合在源极电极。引线部件也可以是金属导线、金属丝。这里,使用了将SiC基板作为基底而制作的MOSFET、铜薄板的引线部件以及铜制散热器。
以引线部件的端部(外引线部)和成为散热面的绝缘薄片的金属箔部分暴露的方式进行树脂密封。这里,通过传递模塑成形由分散了填充剂的环氧树脂来进行了密封。
半导体元件形成覆盖保护环部的绝缘树脂层,并在保护环的外侧的四角区域形成应力缓冲树脂层。在绝缘树脂层使用了非感光聚酰亚胺(PIX3400、HD Micro公司制)、在应力缓冲树脂层使用了感光性聚酰亚胺(HD8930、HD Micro公司制)。
使用了制作出的图3所示的参数的半导体元件的规格表示在表1以及表2中。作为半导体元件使用了正方形的MOSFET,因此处于wS=dS的关系。关于应力缓冲树脂层,成为w1+w2=d2+d3。
覆盖率X以下式进行定义。
X=(w1+w2)/wS (式3)
设计上设为w1=w2,但是因切割的位置偏移误差等允许几μm的尺寸偏差。
作为半导体装置的可靠性评价,实施了热循环试验以及功率循环试验。热循环试验是将半导体装置整体放入能够进行温度控制的恒温槽内,并使恒温槽的温度在-60℃与180℃之间反复变化来实施。功率循环试验是通电至半导体元件的温度成为200℃为止,如果达到该温度则停止通电,冷却至半导体元件的温度成为120℃为止,在冷却后再次通电而实施。
表1、表2中表示了各试验的半导体元件和模塑树脂的剥离产生循环数、试验后的裂痕的有无。
[表1]
[表2]
表1的比较例1是在1边的长度5.5mm的半导体元件上不形成应力缓冲树脂层的规格的半导体元件,表示经过功率循环试验的50k循环(50,000循环)而观察到模塑树脂的剥离。另外在热循环中,在初始至300循环之间观察到剥离。与此相对,在实施例1~5中,由于形成应力缓冲树脂层,至剥离的循环数增加。另外,在覆盖率X成为0.73%以上的实施例2~4中,获得了超过被认为是实用的耐久性的功率循环试验中的200k循环、和热循环试验中的1.8k循环的结果。
另外,刀片切割工序中的半导体元件端部在覆盖率X为5%的实施例4中轻微地产生微小裂痕、在覆盖率X为7.27%的实施例5中产生了很多微小裂痕。从实用的观点考虑,判断为覆盖率X的上限为5%。
表2的比较例1是在1边的长度12mm的半导体元件不形成应力缓冲树脂层的规格的半导体元件,表示经过功率循环试验的20k循环(20,000循环)而观察到模塑树脂的剥离。另外在热循环中,在初始至50循环之间观察到了剥离。与此相对,在实施例6~10中,由于形成应力缓冲树脂层,到剥离的循环数增加。另外,在覆盖率X成为0.71%以上的实施例8~9中,获得了超过被认为是实用的耐久性的功率循环试验中的200k循环、和热循环试验中的1.8k循环的结果。
另外,刀片切割工序中的半导体元件端部在覆盖率X为5%的实施例9中轻微地产生微小裂痕、在覆盖率X为8.33%的实施例10中产生了放多微小裂痕。从实用性的观点考虑,判断为覆盖率X的上限为5%。
根据以上的结果,判明为覆盖率X应以0.76%为下限、以5%为上限。
Claims (6)
1.一种半导体装置的制造方法,其特征在于,包括如下工序:
在半导体基板形成电力控制用的多个半导体元件;
在划分相邻的所述半导体元件的带状的切割区域相交叉的交叉区域中,形成覆盖所述半导体基板上的树脂层;
在所述交叉区域进行切割来切断所述树脂层;
在所述树脂层间的所述切割区域进行切割;
在通过切割而单片化了的所述半导体元件进行布线;以及
将布线了的所述半导体元件用热硬化性树脂进行密封。
2.根据权利要求1所述的半导体装置的制造方法,其特征在于,包括如下工序:
在切割前的多个半导体元件分别形成电极;以及
在所述电极的外周部以及交叉区域形成树脂层,
形成覆盖所述外周部以及所述交叉区域的树脂层的图案。
3.根据权利要求1或者2所述的半导体装置的制造方法,其特征在于,
半导体基板是碳化硅的晶片。
4.一种半导体装置,其特征在于,具备:
半导体芯片,从平板状的碳化硅半导体基板切割为四边形;
应力缓冲树脂层,存在于所述半导体芯片表面的四角来覆盖所述四角的外周端;以及
热硬化性树脂,将所述半导体芯片以及所述应力缓冲树脂层进行密封。
5.根据权利要求4所述的半导体装置,其特征在于,
占据在使用刀片而切割了的半导体芯片中的各边上的应力缓冲树脂层的长度为各边长度的0.73%以上、5%以下。
6.根据权利要求4或者5所述的半导体装置,其特征在于,
半导体芯片具备:
主电极,形成在所述半导体芯片的表面;以及
绝缘树脂层,覆盖所述主电极的外周部,
应力缓冲树脂层是与所述绝缘树脂层相同材料的、连续的树脂层。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2012/004472 WO2014009997A1 (ja) | 2012-07-11 | 2012-07-11 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104428889A true CN104428889A (zh) | 2015-03-18 |
CN104428889B CN104428889B (zh) | 2017-05-10 |
Family
ID=49915502
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201280074595.4A Active CN104428889B (zh) | 2012-07-11 | 2012-07-11 | 半导体装置及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9385007B2 (zh) |
JP (1) | JP6029667B2 (zh) |
CN (1) | CN104428889B (zh) |
DE (1) | DE112012006692B4 (zh) |
WO (1) | WO2014009997A1 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106252307A (zh) * | 2015-06-10 | 2016-12-21 | 富士电机株式会社 | 半导体装置 |
TWI611577B (zh) * | 2016-03-04 | 2018-01-11 | 矽品精密工業股份有限公司 | 電子封裝件及半導體基板 |
CN107634032A (zh) * | 2016-07-18 | 2018-01-26 | 南亚科技股份有限公司 | 晶片及晶片制造方法 |
CN109585368A (zh) * | 2017-09-28 | 2019-04-05 | 台湾积体电路制造股份有限公司 | 半导体封装结构、半导体封装结构的形成方法以及半导体组装结构的形成方法 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9502365B2 (en) * | 2013-12-31 | 2016-11-22 | Texas Instruments Incorporated | Opening in a multilayer polymeric dielectric layer without delamination |
JP2015177116A (ja) * | 2014-03-17 | 2015-10-05 | 株式会社東芝 | 半導体装置 |
US9755105B2 (en) * | 2015-01-30 | 2017-09-05 | Nichia Corporation | Method for producing light emitting device |
WO2017115435A1 (ja) * | 2015-12-28 | 2017-07-06 | オリンパス株式会社 | 半導体ウエハ、半導体チップ、および半導体チップの製造方法 |
JP6988219B2 (ja) * | 2017-07-14 | 2022-01-05 | 富士電機株式会社 | 半導体装置、半導体モジュール及び半導体装置の試験方法 |
US11824048B2 (en) * | 2018-09-20 | 2023-11-21 | Mitsubishi Electric Corporation | Power semiconductor module and composite module having peripheral structures surrounding parts of the module main body |
EP4160656A4 (en) | 2020-05-25 | 2023-08-16 | Mitsubishi Electric Corporation | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE |
KR20220087179A (ko) | 2020-12-17 | 2022-06-24 | 삼성전자주식회사 | 반도체 장치 및 반도체 패키지 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006318988A (ja) * | 2005-05-10 | 2006-11-24 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2011228336A (ja) * | 2010-04-15 | 2011-11-10 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
WO2012070261A1 (ja) * | 2010-11-25 | 2012-05-31 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3807354B2 (ja) | 2001-08-06 | 2006-08-09 | 株式会社デンソー | 半導体装置 |
JP2004253678A (ja) * | 2003-02-21 | 2004-09-09 | Renesas Technology Corp | 半導体装置の製造方法 |
JP4319591B2 (ja) | 2004-07-15 | 2009-08-26 | 株式会社日立製作所 | 半導体パワーモジュール |
JP2006156863A (ja) | 2004-12-01 | 2006-06-15 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2006179542A (ja) | 2004-12-21 | 2006-07-06 | Renesas Technology Corp | 半導体装置 |
JP2011040611A (ja) | 2009-08-12 | 2011-02-24 | Fujikura Ltd | 半導体装置および半導体装置の製造方法 |
WO2011145309A1 (ja) | 2010-05-18 | 2011-11-24 | パナソニック株式会社 | 半導体チップおよびその製造方法 |
-
2012
- 2012-07-11 CN CN201280074595.4A patent/CN104428889B/zh active Active
- 2012-07-11 US US14/412,847 patent/US9385007B2/en active Active
- 2012-07-11 WO PCT/JP2012/004472 patent/WO2014009997A1/ja active Application Filing
- 2012-07-11 DE DE112012006692.8T patent/DE112012006692B4/de active Active
- 2012-07-11 JP JP2014524496A patent/JP6029667B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006318988A (ja) * | 2005-05-10 | 2006-11-24 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2011228336A (ja) * | 2010-04-15 | 2011-11-10 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
WO2012070261A1 (ja) * | 2010-11-25 | 2012-05-31 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106252307A (zh) * | 2015-06-10 | 2016-12-21 | 富士电机株式会社 | 半导体装置 |
TWI611577B (zh) * | 2016-03-04 | 2018-01-11 | 矽品精密工業股份有限公司 | 電子封裝件及半導體基板 |
CN107634032A (zh) * | 2016-07-18 | 2018-01-26 | 南亚科技股份有限公司 | 晶片及晶片制造方法 |
CN107634032B (zh) * | 2016-07-18 | 2020-04-21 | 南亚科技股份有限公司 | 晶片及晶片制造方法 |
CN109585368A (zh) * | 2017-09-28 | 2019-04-05 | 台湾积体电路制造股份有限公司 | 半导体封装结构、半导体封装结构的形成方法以及半导体组装结构的形成方法 |
US11139285B2 (en) | 2017-09-28 | 2021-10-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package |
CN109585368B (zh) * | 2017-09-28 | 2022-08-23 | 台湾积体电路制造股份有限公司 | 半导体封装结构、半导体封装结构的形成方法以及半导体组装结构的形成方法 |
Also Published As
Publication number | Publication date |
---|---|
DE112012006692B4 (de) | 2023-04-20 |
JPWO2014009997A1 (ja) | 2016-06-20 |
CN104428889B (zh) | 2017-05-10 |
US20150162219A1 (en) | 2015-06-11 |
US9385007B2 (en) | 2016-07-05 |
JP6029667B2 (ja) | 2016-11-24 |
WO2014009997A1 (ja) | 2014-01-16 |
DE112012006692T5 (de) | 2015-04-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104428889A (zh) | 半导体装置及其制造方法 | |
JP5804203B2 (ja) | 半導体装置およびその製造方法 | |
CN107039362A (zh) | 半导体器件 | |
US8674492B2 (en) | Power module | |
US20050067719A1 (en) | Semiconductor device and method for producing the same | |
US20150221525A1 (en) | Semiconductor device and method of manufacture thereof | |
CN103426837B (zh) | 半导体封装及形成半导体封装的方法 | |
CN102299117A (zh) | 具有冷却机制的半导体模块及其生产方法 | |
TW201419649A (zh) | 具改良的共模暫態抗擾性之數位隔離器 | |
JP2014135470A (ja) | 発光装置、発光装置集合体および電極付基板 | |
US20140353812A1 (en) | Semiconductor device | |
JP2017050374A (ja) | パワーモジュール、パワーモジュールの放熱構造、およびパワーモジュールの接合方法 | |
US10593605B2 (en) | Semiconductor package | |
JP5258825B2 (ja) | パワー半導体装置及びその製造方法 | |
CN105122441A (zh) | 化合物半导体装置及其制造方法以及树脂密封型半导体装置 | |
JP2014116333A (ja) | 半導体装置 | |
JP2007027261A (ja) | パワーモジュール | |
US9355999B2 (en) | Semiconductor device | |
CN114649274A (zh) | 半导体封装及其制造方法 | |
JP2015162645A (ja) | 半導体装置およびその製造方法 | |
JP2006313775A (ja) | 半導体装置及びその製造方法 | |
WO2023080090A1 (ja) | 半導体パッケージ | |
JP6167825B2 (ja) | 半導体装置 | |
JP2014236028A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP7157783B2 (ja) | 半導体モジュールの製造方法及び半導体モジュール |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |