CN104425429A - 具有多层裸片组块的半导体封装 - Google Patents

具有多层裸片组块的半导体封装 Download PDF

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Publication number
CN104425429A
CN104425429A CN201410432996.3A CN201410432996A CN104425429A CN 104425429 A CN104425429 A CN 104425429A CN 201410432996 A CN201410432996 A CN 201410432996A CN 104425429 A CN104425429 A CN 104425429A
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Prior art keywords
lead
chunk
wire
semiconductor die
sunk area
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CN201410432996.3A
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CN104425429B (zh
Inventor
吴国财
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

一种包括组块的半导体封装，具有第一侧，与第一侧相对的第二侧，以及从第二侧朝向第一侧延伸的凹陷区域，使得组块在凹陷区域中具有较薄部分并且在凹陷区域之外具有较厚部分。半导体封装进一步包括每一个具有相对的第一和第二侧的第一半导体裸片和第二半导体裸片。第一半导体裸片布置在组块的凹陷区域中并且在第一半导体裸片的第一侧处附接至组块的较薄部分。第二半导体裸片在第二半导体裸片的第一侧处附接至第一半导体裸片的第二侧。

Description

具有多层裸片组块的半导体封装
技术领域
本发明涉及半导体封装，更具体而言涉及包括多个半导体裸片的半导体封装。
背景技术
许多类型半导体封装包括多个半导体裸片(芯片)。例如在多裸片SO型封装中，每个裸片附接至不同的裸片焊垫(paddle)，使得封装中包括的裸片焊垫的数目等于封装中裸片的数目。每个裸片焊垫占据了特定面积并且SO封装具有最大尺寸，这限制了封装中可以包括的裸片的数目和尺寸。其他类型多裸片封装覆盖了半桥电路。半桥电路是使得在任一方向上跨负载施加电压的电子电路。半桥电路通常包括在不同半导体裸片中实现的高侧晶体管和低侧晶体管。高侧晶体管裸片的源极端子连接至低侧晶体管的漏极元件以形成半桥电路的输出。传统的半桥封装将高侧晶体管裸片的源极端子通过金属夹片或额外的接合引线而连接至低侧晶体管裸片的漏极端子，这在每个情形下增大了封装尺寸和成本。该连接也具有一些不可忽略的电阻，从而增大了半桥电路的功率损耗。传统的半桥封装也通常对于封装中包括的每个晶体管裸片采用不同的裸片焊垫，从而进一步增大了封装的尺寸和成本。
发明内容
根据半导体封装的一个实施例，封装包括组块，具有第一侧，与第一侧相对的第二侧，以及从第二侧朝向第一侧延伸的凹陷区域，使得组块在凹陷区域中具有较薄部分并且在凹陷区域之外具有较厚部分。半导体封装进一步包括每一个具有相对的第一侧和第二侧的第一半导体裸片和第二半导体裸片。第一半导体裸片布置在组块的凹陷区域中，并且在第一半导体裸片的第一侧处附接至组块的较薄部分。第二半导体裸片在第二半导体裸片的第一侧处附接至第一半导体裸片的第二侧。
根据制造半导体封装的方法的一个实施例，该方法包括：在组块中形成凹陷区域，使得组块在凹陷区域中具有较薄部分并且在凹陷区域之外具有较厚部分；将具有相对的第一侧和第二侧的第一半导体裸片布置在组块的凹陷区域中，使得第一半导体裸片的第一侧面向组块的较薄部分；将第一半导体裸片的第一侧附接至组块；将具有相对的第一侧和第二侧的第二半导体裸片布置在第一半导体裸片上，使得第二半导体裸片的第一侧面向第一半导体裸片的第二侧；以及将第二半导体裸片的第一侧附接至第一半导体裸片的第二侧。
根据引线框架的一个实施例，引线框架包括裸片焊垫，具有第一侧，与第一侧相对的第二侧，以及从第二侧朝向第一侧延伸的凹陷区域，使得裸片焊垫在凹陷区域中具有较薄部分并且在凹陷区域之外具有较厚部分。引线框架进一步包括相互间隔开的多个导电引线以及裸片焊垫。引线之一具有凹陷区域以使得引线在引线的凹陷区域中具有较薄部分并且在引线的凹陷区域之外具有较厚部分。
一旦审阅了以下详细说明书并且一旦查看了附图，本领域技术人员将认识到额外的特征和优点。
附图说明
附图的元件并非必需按照相对比例绘制。相同的附图标记表示对应的相同部件。各种所示实施例的特征可以组合，除非它们相互排斥。实施例示出在附图中，并且在以下说明书中详述。
图1A和图1B示出了在制造的不同阶段期间具有多层裸片组块的半导体封装的一个实施例的截面图。
图2示出了具有多层裸片组块的半导体封装的另一实施例的截面图。
图3示出了具有多层裸片组块的半导体封装的又一实施例的截面图。
图4A至图4M示出了在制造的不同阶段期间具有多层裸片组块的半导体封装的另一实施例的截面图。
图5示出了包括在图4的半导体封装中的半桥电路的示意图。
具体实施方式
在此所述的实施例提供了一种半导体封装，包括诸如金属组块、陶瓷组块或引线框架的裸片焊垫之类的组块，该组块具有凹陷区域，在封装中包括的半导体裸片被布置在凹陷区域中。组块在凹陷区域中具有较薄部分并且在凹陷区域之外具有较厚部分。组块可以用作散热器和/或提供去往布置在凹陷区域中半导体裸片的外部电连接的点。该裸片在裸片的一侧附接至组块的较薄部分。在封装中包括的另一裸片导电地附接至布置在组块的凹陷区域中的裸片的另一侧。在此所述的封装通过对于每个裸片堆叠设置消除了至少一个裸片焊垫而减小了尺寸，并且在堆叠的裸片之间提供了直接电连接。此外，堆叠裸片设置并未增大总体封装厚度，因为堆叠设置中裸片的一个布置在组块的凹陷区域中，并且凹陷区域的深度可以选择以完全容纳该裸片的厚度。在此所述的封装可以包括任何数目半导体裸片，在封装中包括裸片的数目取决于其中采用了裸片的电路的类型。
图1A和图1B示出了在制造的不同阶段期间半导体封装的实施例的截面图。图1A示出了在组块102中形成了凹陷区域100之后的封装，使得组块102在凹陷区域100中具有较薄部分(T1)并且在凹陷区域100之外具有较厚部分(T2)。组块102可以是金属组块、陶瓷组块、引线框架的裸片焊垫等等。凹陷区域100可以通过任何标准材料移除工艺而形成在组块102中，诸如化学刻蚀、激光刻蚀、3D打印等等。
第一半导体裸片104布置在组块102的凹陷区域100中，使得裸片104的底侧106朝向组块100的较薄部分T1。裸片104的底侧106附接至组块102的较薄部分T1。裸片104可以经由导电或者绝缘的裸片附接材料108(诸如焊料、粘着剂(导电或者非导电的)等)而附接至组块102的较薄部分T1。在其他一些实施例中，***在第一裸片104与组块102的较薄部分T1之间的材料108是导电或者非导电的间隔件。
在一些情形下，裸片104可以是垂直器件，其中电流沿垂直方向流动在裸片104的底侧和顶侧106、110之间。该类型裸片在裸片104的两侧处具有端子。例如在诸如功率MOSFET之类的功率晶体管裸片的情形中，晶体管裸片104可以在裸片104的底侧106处具有漏极端子，以及在裸片104的顶侧110处具有源极端子和栅极端子。漏极端子可以通过焊料裸片附接或者导电粘附材料108而导电地附接至组块102的较薄部分T1。在二极管的情形中，二极管裸片104可以在裸片104的底侧106处具有阴极端子，以及在裸片104的顶侧110处具有阳极端子。阴极端子可以通过焊料裸片附接或者导电粘附材料108而导电地附接至组块102的较薄部分T1。
在其他一些情形下，裸片104可以是横向器件，其中电流沿着裸片104的顶侧110而以横向方向流动。该类型裸片仅在裸片104的顶侧110处具有端子。横向裸片104的底侧106缺乏端子，但是用作用于裸片104的散热路径。横向裸片104的底侧106可以通过并非必需导电的导热材料108而附接至组块102的较薄部分T1。为了易于说明，裸片端子并未示出在图1A和图1B中。
图1B示出了在第二半导体裸片112被布置在第一半导体裸片104的顶侧110上并且第三半导体裸片114经由裸片附接材料116附接至组块102的较厚部分T2之后的封装。第二半导体裸片112的底侧118经由裸片附接材料120而附接至第一半导体裸片104的顶侧110。第三裸片114沿横向方向(也即垂直于垂直方向的方向)与第一半导体裸片104和第二半导体裸片112间隔开。第一裸片104和第二裸片112以堆叠设置布置。组块102中凹陷区域100的深度(D)可以使得凹陷区域100容纳了第一裸片104的整个厚度(Tdie)。备选地，第一裸片104的一部分可以延伸越过组块102的顶侧122。在每个情形中，在第二裸片11的底侧118处的一个或多个端子可以导电地附接至在第一裸片14的顶侧110处的对应的端子以在堆叠裸片104、112之间形成所需的电连接。第三裸片114的底侧124可以导电地或者非导电地附接至组块102的较厚部分T2，取决于包括在封装中的裸片114和电路的类型。在第二裸片112和第三裸片114的顶侧126、128之间的电连接可以由金属夹片、接合引线、带状电缆等等而实现。其他电连接可以制成封装的引线。为了易于解释说明而未将这些电连接和引线示出在图1A和图1B中。在封装内完成了内部电连接之后可以模塑封装。
图2示出了半导体封装的另一实施例的截面图。图2中所示实施例类似于图1B中所示，然而第二半导体裸片112的部分130突出在组块102的较厚部分T2之上。取决于裸片的类型(垂直或横向)，第一裸片104可以通过导电或非导电裸片附接材料或间隔件108而附接至组块102的较薄部分T1。例如，***在第一裸片104的底侧106与组块102的较薄部分T1之间的材料108可以是非导电间隔件108，使得第一裸片104与组块102断开电连接，并且在第二裸片112的底侧118处的端子可以由导电裸片附接材料132而导电地附接至在第一裸片104的顶侧110处对应的端子以及组块102的较厚部分T2。在该实施例中，组块102是导电的并且形成了封装的引线。
图3示出了半导体封装的又一实施例的截面图。图3中所示实施例类似于图2中所示，然而封装也包括与第一组块102间隔开的第二组块134。第二组块134具有凹陷区域136，使得第二组块134在第二组块134的凹陷区域136中具有较薄部分(T3)以及在第二组块134的凹陷区域136之外具有可选的较厚部分(T4)。第一半导体裸片104部分地布置在第一组块102的凹陷区域100中，并且部分地布置在第二组块134的凹陷区域136中，使得第一半导体裸片104跨越了组块102、134之间的间隙(G)。在一个实施例中，第二组块134是封装的导电引线，并且第一裸片104和第二裸片112是在相应裸片104、112的两侧106、110、118、126处均具有端子的垂直器件。为了易于说明，在图3中未示出端子。在第一裸片104的底侧106处的端子通过电绝缘的裸片附接材料和/或电绝缘的间隔件138而附接至第一组块102的较薄部分T1，并且通过导电的裸片附接材料140而导电地附接至第二组块134的较薄部分T3。如果在第一裸片104与第一组块102的较薄部分T1之间使用间隔件138，则间隔件138的厚度可以容纳将第一裸片104的底侧106附接至第二组块134的较薄部分T3的裸片附接材料140的厚度。
图4A至图4M示出了在制造的不同阶段期间半导体封装的实施例的不同示意图。在封装中包含的集成电路是如图5所示类型的半桥电路。半桥电路包括高侧晶体管裸片400，低侧晶体管裸片402，以及耦合在半桥电路的正性输入(VIN)和负性输入(PGND)之间的输入电容器(Cin)。负性输入可以在一些配置结构中接地。在如图5所示的示例性电路图中，晶体管裸片400、402是MOSFET(金属氧化物半导体场效应晶体管)裸片，每个MOSFET具有栅极(Gn)、漏极(Dn)和源极(Sn)端子。
高侧晶体管裸片400的漏极端子(D1)电连接至半桥电路的正性输入(VIN)。高侧晶体管裸片400的源极端子(S1)电连接至低侧晶体管裸片402的漏极端子(D2)以形成半桥电路的输出(SW)。低侧晶体管裸片402的源极端子(S2)电连接至负性输入(PGND)。晶体管裸片400、402的栅极端子(G1、G2)用作相应的控制信号输入(IN1、IN2)。IGBT(绝缘栅双极晶体管)可以替代MOSFET而使用，其中IGBT的集电极连接将对应于MOSFET的漏极连接，而IGBT的发射极连接将对应于MOSFET的源极连接。通常，包括在封装中的半导体裸片的类型和数目取决于封装设计使用的特定应用，并且在每个情形下可以使用在此所述的堆叠裸片的实施例。
返回至封装的制造，图4A示出了引线框架的裸片焊垫404和引线406的平面图。在图4A中采用标识符(D1、D2、G1、G2、S2)标注引线406，标识符对应于稍后将要连接至每个引线406的裸片端子。裸片焊垫404待连接至低侧晶体管402的漏极端子(D2)。
图4B示出了沿着图4A中标注为A-A’的线获得的截面图。图4C示出了沿着图4A中标注为B-B’的线获得的截面图。裸片焊垫404具有例如约250μm的特定厚度(TDP)。构思了其他裸片焊垫厚度。
图4D示出了在裸片焊垫404中形成凹陷区域408并且在与高侧晶体管400的漏极端子(D1)相关联的引线408中形成凹陷区域410之后的裸片焊垫404和引线406的平面图。图4E示出了沿着图4D中标注为A-A’线获得的截面图，以及图4F示出了沿着图4D中标注为B-B’线获得的截面图。凹陷区域408、410可以由任何标准材料移除工艺而形成，诸如化学刻蚀、激光刻蚀、3D打印等等。裸片焊垫404在凹陷区域408中具有较薄部分(TDPT)并且在凹陷区域408之外具有较厚部分(TDP)。凹陷区域408、410可以完全刻蚀以易于制造引线框架，并且由多于一个裸片焊垫或引线而构造。
裸片焊垫404的凹陷区域408具有特定宽度(WDPR)以容纳将要布置在裸片焊垫404的凹陷区域408中的半导体裸片400。裸片焊垫404的凹陷区域408从裸片焊垫404的顶侧412延伸至深度(DDPR)。在一个实施例中，DDPR范围从50μm至120μm。通常，DDPR取决于将要布置在裸片焊垫404的凹陷区域408中的半导体裸片400的厚度。可以选择以DDPR完全或者部分容纳如在此之前所述的裸片厚度。
具有凹陷区域410的引线406类似地在其凹陷区域410中具有较薄部分(TLT)并且在其凹陷区域410之外具有可选的较厚部分(TL)。引线406的凹陷区域410从引线410的顶侧414延伸至深度(DLR)。在一个实施例中，裸片焊垫404和引线406具有相同的厚度(也即TDP＝TL)，并且凹陷区域408、410延伸至相同深度(也即DDPR＝DLR)。通常，DLR取决于将要布置在引线406的凹陷区域410中的半导体裸片400的厚度，并且可以选择以完全或者部分地容纳如在此之前所述的裸片厚度。
图4G示出了在高侧晶体管裸片400部分地布置在裸片焊垫404的凹陷区域408中以及部分地布在引线406的凹陷区域410中以使得高侧晶体管裸片400跨越在裸片焊垫404和具有凹陷区域410的引线406之间的间隙(G)之后的裸片焊垫404和引线406的平面图。图4H示出了沿着图4G中标注为A-A’的线的截面图，以及图4I示出了沿着图4G中标注为B-B’的线的截面图。高侧晶体管裸片400的漏极端子(D1)通过诸如焊料或导电粘附剂之类的导电裸片附接材料416而导电地附接至引线406的较薄部分TLT。根据该实施例，高侧晶体管裸片400的漏极端子(D1)也通过非导电间隔件418而附接至裸片焊垫404的较薄部分TDPT。间隔件418容纳了将高侧晶体管裸片400的漏极端子(D1)附接至引线406的较薄部分TLT的裸片附接材料416的厚度。高侧晶体管裸片400的栅极端子(G1)和源极端子(S1)位于裸片400的与漏极端子(D1)相对的侧面处并且背离裸片焊垫404。
图4J示出了在低侧晶体管裸片402的漏极端子(D2)经由诸如焊料或导电粘附剂之类的导电裸片附接材料420而导电地附接至高侧晶体管裸片400的源极端子(S1)之后的裸片焊垫404和引线406的平面图。图4K示出了沿着图4J中标注为A-A’线的截面图，以及图4L示出了沿着图4J中标注为B-B’线的截面图。
低侧晶体管裸片402布置在高侧晶体管裸片400上以使得高侧晶体管裸片400的栅极端子(G1)在图4J和图4K中保持并未被低侧晶体管裸片402覆盖。此外根据该实施例，低侧晶体管裸片402的一部分422如图4J和图4L所示突出悬垂在裸片焊垫404的较厚部分TDP之上，或者可以通过裸片附接材料424而附接。低侧晶体管裸片402的漏极端子(D2)也通过裸片附接材料424而导电地附接至裸片焊垫404的较厚部分TDP，并且裸片焊垫404形成了半桥电路的输出(SW)。
图4M示出了在高侧和低侧晶体管裸片400、402的顶侧处端子G1、G2、S2经由诸如金属夹片、接合引线、带状电缆等之类的连接件424而电连接至封装的相应端子406之后的裸片焊垫404和引线406的平面图。例如，高侧晶体管裸片400的栅极端子(G1)电连接至对应的封装引线406，低侧晶体管裸片402的源极端子(S2)电连接至对应的封装引线406，并且低侧晶体管裸片402的栅极端子(G2)电连接至对应的封装引线406。可以在形成了这些连接之后对封装进行密封。
使用诸如“之下”、“下方”、“低于”、“之上”、“高于”等等的空间相对性术语以易于描述解释一个元件相对于第二元件的定位。这些术语意在除了与附图中所示那些不同朝向之外包括器件的不同朝向。此外，也使用诸如“第一”、“第二”等等的术语以描述各种元件、区域、区段等等，并且也并非意在为限定性的。说明书全文中相同的术语涉及相同的元件。
如在此使用的，术语“具有”、“含有”、“包含”、“包括”等等是开放性术语，指示了所述元件或特征的存在，但是并未排除额外的元件或特征。冠词“一”、“一个”和“该”意在包括复数以及单数，除非上下文明确给出相反指示。
考虑到变形例和应用的以上范围，应该理解的是，本发明不限于前述说明书，也不限于附图。替代地，仅由以下权利要求及其法律等价形式限定本发明。

Claims (24)

1.一种半导体封装，包括：
组块，具有第一侧，与所述第一侧相对的第二侧，以及从所述第二侧朝向所述第一侧延伸的凹陷区域，使得所述组块在所述凹陷区域中具有较薄的部分并且在所述凹陷区域之外具有较厚的部分；
第一半导体裸片，具有相对的第一侧和第二侧，所述第一半导体裸片布置在所述组块的所述凹陷区域中并且在所述第一半导体裸片的所述第一侧处附接至所述组块的所述较薄部分；以及
第二半导体裸片，在所述第二半导体裸片的第一侧处附接至所述第一半导体裸片的所述第二侧。
2.根据权利要求1所述的半导体封装，其中，所述第二半导体裸片的一部分突出在所述组块的所述较厚部分之上。
3.根据权利要求2所述的半导体封装，进一步包括，电绝缘的间隔件，布置在所述组块的所述凹陷区域中并且***在所述第一半导体裸片与所述组块的所述较薄部分之间。
4.根据权利要求3所述的半导体封装，其中，在所述第二半导体裸片的所述第二侧处的端子导电地附接至在所述第一半导体裸片的所述第二侧处的端子以及附接至所述组块的所述较厚部分。
5.根据权利要求1所述的半导体封装，进一步包括，多个导电引线，其中所述第一半导体裸片具有在所述第一半导体裸片的所述第二侧的端子，所述端子并未被所述第二半导体裸片覆盖并且电连接至所述引线中的第一引线，以及其中所述第二半导体裸片具有在所述第二半导体裸片的所述第二侧处的端子，所述端子电连接至所述引线中的第二引线。
6.根据权利要求5所述的半导体封装，其中，所述引线中的第三引线具有凹陷区域，使得所述第三引线在所述第三引线的凹陷区域中具有较薄部分并且在所述第三引线的凹陷区域之外具有较厚部分，其中所述第一半导体裸片部分地布置在所述组块的凹陷区域中并且部分地布置在所述第三引线的凹陷区域中，以及其中所述第一半导体裸片具有在所述第一半导体裸片的第一侧处的端子，所述端子导电地附接至所述第三引线的所述较薄部分。
7.根据权利要求6所述的半导体封装，进一步包括，电绝缘的间隔件，布置在所述组块的所述凹陷区域中并且***在所述第一半导体裸片的所述第一侧处的端子与所述组块的所述较薄部分之间。
8.根据权利要求1所述的半导体封装，其中，所述组块是引线框架的裸片焊垫。
9.根据权利要求1所述的半导体封装，进一步包括额外组块，所述额外组块与其他组块间隔开并且具有凹陷的区域，使得所述额外组块在所述额外组块的凹陷区域中具有较薄部分并且在所述额外组块的凹陷区域之外具有较厚部分，以及其中所述第一半导体裸片部分地布置在所述组块的凹陷区域中并且部分地布置在所述额外组块的凹陷区域中，使得所述第一半导体裸片跨越所述组块之间的间隙。
10.根据权利要求1所述的半导体封装，进一步包括第三半导体裸片，所述第三半导体裸片附接至所述组块的较厚部分并且与所述第一半导体裸片和所述第二半导体裸片间隔开。
11.根据权利要求1所述的半导体封装，进一步包括间隔件，所述间隔件布置在所述组块的凹陷区域中并且***在所述第一半导体裸片和所述组块的较薄部分之间。
12.根据权利要求1所述的半导体封装，其中，所述组块的所述凹陷区域从所述组块的所述第二侧延伸至50μm至120μm的深度。
13.根据权利要求1所述的半导体封装，其中，所述第一半导体裸片是半桥电路的高侧晶体管裸片，并且所述第二半导体裸片是所述半桥电路的低侧晶体管裸片，其中所述高侧晶体管裸片具有附接至所述组块的所述较薄部分的漏极端子以及在所述高侧晶体管裸片的相对侧处的源极端子和栅极，其中所述低侧晶体管裸片具有导电地附接至所述高侧晶体管裸片的所述源极端子的漏极端子以及在所述低侧晶体管裸片的相对侧处的源极端子和栅极端子，以及其中所述低侧晶体管裸片布置在所述高侧晶体管裸片上，使得所述高侧晶体管裸片的所述栅极端子保持并未被所述低侧晶体管裸片覆盖。
14.根据权利要求13所述的半导体封装，其中，所述低侧晶体管裸片的一部分突出在所述组块的所述较厚部分之上。
15.根据权利要求14所述的半导体封装，进一步包括电绝缘的间隔件，所述电绝缘的间隔件布置在所述组块的所述凹陷区域中并且***在所述高侧晶体管裸片与所述组块的所述较薄部分之间。
16.根据权利要求15所述的半导体封装，其中，所述低侧晶体管裸片的所述漏极端子导电地附接至所述组块的所述较厚部分，并且其中所述组块是所述封装的输出引线。
17.根据权利要求13所述的半导体封装，进一步包括多个导电引线，其中所述高侧晶体管裸片的所述栅极端子电连接至所述引线中的第一引线，其中所述低侧晶体管裸片的所述源极端子电连接至所述引线中的第二引线，以及其中所述低侧晶体管裸片的所述栅极端子电连接至所述引线中的第三引线。
18.根据权利要求17所述的半导体封装，其中，所述引线中的第四引线具有凹陷区域，使得所述第四引线在所述第四引线的凹陷区域中具有较薄部分并且在所述第四引线的凹陷区域之外具有较厚部分，其中所述高侧晶体管裸片部分地布置在所述组块的凹陷区域中并且部分地布置在所述第四引线的凹陷区域中，以及其中所述高侧晶体管裸片的漏极端子导电地附接至所述第四引线的所述较薄部分。
19.根据权利要求18所述的半导体封装，其中，所述高侧晶体管裸片的所述漏极端子从所述组块的所述凹陷区域之上延伸至所述第四引线的所述凹陷区域之上，所述半导体封装进一步包括电绝缘的间隔件，所述电绝缘的间隔件布置在所述组块的所述凹陷区域中并且***在所述高侧晶体管裸片的所述漏极端子与所述组块的所述较薄部分之间。
20.一种制造半导体封装的方法，所述方法包括：
在组块中形成凹陷区域，使得所述组块在所述凹陷区域中具有较薄部分并且在所述凹陷区域之外具有较厚部分；
将具有相对的第一侧和第二侧的第一半导体裸片布置在所述组块的所述凹陷区域中，使得所述第一半导体裸片的所述第一侧朝向所述组块的所述较薄部分；
将所述第一半导体裸片的所述第一侧附接至所述组块；
将具有相对的第一侧和第二侧的第二半导体裸片布置在所述第一半导体裸片上，使得所述第二半导体裸片的所述第一侧朝向所述第一半导体裸片的所述第二侧；以及
将所述第二半导体裸片的所述第一侧附接至所述第一半导体裸片的所述第二侧。
21.根据权利要求20所述的方法，进一步包括：
提供多个导电引线；
将在所述第一半导体裸片的所述第二侧处的、未被所述第二半导体裸片覆盖的端子电连接至所述引线中的第一引线；以及
将在所述第二半导体裸片的所述第二侧处的端子电连接至所述引线中的第二引线。
22.根据权利要求21所述的方法，进一步包括：
在所述引线中的第三引线中形成凹陷区域，使得所述第三引线在所述第三引线的所述凹陷区域中具有较薄部分并且在所述第三引线的所述凹陷区域之外具有较厚部分，其中所述第一半导体裸片部分地布置在所述组块的所述凹陷区域中并且部分地布置在所述第三引线的所述凹陷区域中；以及
将在所述第一半导体裸片的所述第一侧处的端子导电地附接至所述第三引线的所述较薄部分。
23.根据权利要求22所述的方法，进一步包括，在所述第一半导体裸片的所述第一侧处的所述端子与所述组块的所述较薄部分之间布置电绝缘的间隔件。
24.一种引线框架，包括：
裸片焊垫，具有第一侧，与所述第一侧相对的第二侧，以及从所述第二侧朝向所述第一侧延伸的凹陷区域，使得所述裸片焊垫在所述凹陷区域中具有较薄部分并且在所述凹陷区域之外具有较厚部分；以及
多个导电引线，相互间隔开并且与所述裸片焊垫间隔开，其中所述引线中的一个或多个具有凹陷区域，使得所述一个或多个引线在所述一个或多个引线的所述凹陷区域中具有较薄部分并且在所述一个或多个引线的所述凹陷区域之外具有较厚部分。
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