CN104425266A - Thin film transistor and method for manufacturing display array substrate using the thin film transistor - Google Patents
Thin film transistor and method for manufacturing display array substrate using the thin film transistor Download PDFInfo
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- CN104425266A CN104425266A CN201310371920.XA CN201310371920A CN104425266A CN 104425266 A CN104425266 A CN 104425266A CN 201310371920 A CN201310371920 A CN 201310371920A CN 104425266 A CN104425266 A CN 104425266A
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- 238000000034 method Methods 0.000 title claims abstract description 69
- 239000010409 thin film Substances 0.000 title claims abstract description 65
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims abstract description 38
- 238000000059 patterning Methods 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 29
- 239000012212 insulator Substances 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 18
- 230000008569 process Effects 0.000 claims description 18
- 239000011368 organic material Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000001020 plasma etching Methods 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
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- 238000000576 coating method Methods 0.000 abstract 2
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 239000004065 semiconductor Substances 0.000 description 12
- 229910044991 metal oxide Inorganic materials 0.000 description 11
- 150000004706 metal oxides Chemical class 0.000 description 11
- 239000011651 chromium Substances 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 229910001195 gallium oxide Inorganic materials 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 229910004205 SiNX Inorganic materials 0.000 description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 229910052779 Neodymium Inorganic materials 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
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- 239000011733 molybdenum Substances 0.000 description 4
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 4
- 125000002524 organometallic group Chemical group 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
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- 238000004544 sputter deposition Methods 0.000 description 4
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- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
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- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910003437 indium oxide Inorganic materials 0.000 description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- NQBRDZOHGALQCB-UHFFFAOYSA-N oxoindium Chemical compound [O].[In] NQBRDZOHGALQCB-UHFFFAOYSA-N 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000007711 solidification Methods 0.000 description 3
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- 229910052725 zinc Inorganic materials 0.000 description 3
- 239000011701 zinc Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a method for manufacturing a thin film transistor. The manufacturing method includes: forming a grid electrode on a substrate and a grid electrode insulating layer that covers the grid electrode; forming a channel layer on the grid electrode insulating layer in a position corresponding to the grid electrode, and coating an etching barrier layer on the channel layer; performing high-temperature hard roasting treatment on the etching barrier layer; coating a photoresistance layer on the etching barrier layer; patterning the photoresistance layer, and developing two through guide holes; using the patterned photoresistance layer as a shield, etching the etching barrier layer to the channel layer to form two contact holes; removing the remaining photoresistance layer; and forming a source electrode and a drain electrode in the positions of the two contact holes.
Description
Technical field
The present invention relates to a kind of thin-film transistor and use the manufacture method of array of display substrate of this thin-film transistor.
Background technology
The thin-film transistor (Thin Film Transistor, TFT) utilizing metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor) to form raceway groove is widely used in display field gradually and is used as switch module.Because metal-oxide semiconductor (MOS) is to back-end process in thin-film transistor processing procedure; form wet etching (Wet-Etching) the processing procedure reaction sensitivity of the source of thin-film transistor, drain electrode as being used for, therefore an etch stop layer can be formed so as to protecting the characteristic of this metal oxide semiconductor layer on metal oxide semiconductor layer.But, because etch stop layer must meet certain thickness requirements, as being greater than 1 micron, the channel width between source electrode and drain electrode is made usually to maintain 10 microns when forming contact hole with gold-tinted exposure by affecting of thickness, cannot be reduced to one more among a small circle in, not only cause the characteristic of thin-film transistor itself, as frequency characteristic is affected, and the requirement of the panels such as high-resolution (High Resolution HD) cannot be met.
Summary of the invention
In view of this, be necessary to provide a kind of manufacture method with the thin-film transistor of smaller channels length.
Further, a kind of manufacture method with the array of display substrate of this thin-film transistor is provided.
A manufacture method for thin-film transistor, this manufacture method comprises:
On a substrate, form grid and cover the gate insulator of this grid;
On this gate insulator, corresponding grid place forms channel layer, and is coated with etch stop layer on this channel layer;
The firmly roasting process of high temperature is carried out to this etch stop layer;
Photoresistance is coated with on this etch stop layer;
This photoresistance of patterning, develop two perforating holes;
This etch stop layer of shielding etching is done to this channel layer to form two contact holes with this patterning photoresistance;
Remove this patterning photoresistance; And
Source electrode and drain electrode is formed in this two contact holes place.
A manufacture method for array of display substrate, this manufacture method comprises:
There is provided a substrate, and form thin-film transistor on this substrate, wherein the manufacture method of this thin-film transistor is aforementioned film transistor fabrication process.
Compared to prior art, thin-film transistor of the present invention and use the manufacture method of this thin-film transistor array base-plate etch stop layer to be done the firmly roasting process of high temperature, and utilize the photoresistance of comparatively jitty design to carry out exposure imaging to go out perforating holes, utilize dry etching technology to be etched with contact hole that acquisition has a comparatively short distance to reduce the channel width between the source of thin-film transistor, drain electrode to etch stop layer further, reach the demand of the high-resolution improving TFT performance and meet panel.
Accompanying drawing explanation
Fig. 1 is the part plan structural representation in the array of display substrate one picture element region of first embodiment of the invention.
Fig. 2 is the cross-sectional view of the substrate of array of display shown in Fig. 1 along II-II line.
Fig. 3 to Fig. 8 describes the structural representation of each making step of thin-film transistor shown in Fig. 2.
Fig. 9 is the thin-film transistor manufacturing process schematic diagram shown in Fig. 2.
Figure 10 is the cross-sectional view of the thin-film transistor of second embodiment of the invention.
Figure 11 to Figure 17 describes the structural representation of each making step of thin-film transistor shown in Figure 10.
Figure 18 is the thin-film transistor manufacturing process schematic diagram shown in Figure 10.
Main element symbol description
| Array of display substrate | 10 |
| Thin-film transistor | 100、200 |
| Gate line | 11 |
| Data wire | 12 |
| Grid | 110、210 |
| Source electrode | 120、220 |
| Drain electrode | 130、230 |
| Substrate | 101、201 |
| Channel layer | 103、203 |
| Gate insulator | 105、205 |
| Etch stop layer | 107、207 |
| Inorganic barrier layer | 207a |
| Hard mask layer | 207b |
| Photoresistance | 109、209 |
| Light shield | 14、24 |
| Printing opacity part | 140、240 |
| Light tight part | 141、241 |
| Perforating holes | H1、H2、H21、H22 |
| Contact hole | O1、O2、O21、O22 |
| Step | S301~S315、S401~S417 |
Following embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
Refer to Fig. 1, Fig. 1 is the planar structure schematic diagram of the local in a picture element region of an embodiment of the present invention array of display substrate.This array of display substrate 10 comprises a plurality of gate lines 11 be parallel to each other, a plurality of are parallel to each other and insulate data wire 12 crossing with those gate lines.Each gate line 11 and data wire 12 infall arrange a thin-film transistor (thin-film transistor, TFT) 100, this thin-film transistor 100 comprises the grid signal that the grid 110 that is connected with gate line 11 exports for external gate driver (not shown), and the source electrode 120 be connected with data wire 12 is for the data signals that receives external data driver (not shown) and export and drain electrode 130 spaced with this source electrode 120.
When the threshold voltage of grid signal voltage higher than thin-film transistor 100 that gate line 11 exports, the electrical characteristics being formed in the channel layer 103 (as shown in Figure 2) of thin-film transistor 100 inside become conductor from insulator, and the data signals being applied to source electrode 120 is applied in drain electrode 130 by channel layer 103.
See also Fig. 2, Fig. 2 is the cross-sectional view of the array of display substrate 10 shown in Fig. 1 along II-II line.This thin-film transistor 100 also comprises gate insulator 105 and etch stop layer 107.Wherein, this grid 110 is arranged on substrate 101, and this source electrode 120 is arranged with layer with this drain electrode 130, and this channel layer 103 connects this source electrode 120 and this drain electrode 130.The corresponding grid 110 of this channel layer 103 is arranged, and this gate insulator 105 is arranged between this grid 110 and this channel layer 103, and this etch stop layer 107 is arranged at the surface of this channel layer 103 for this source electrode 120 of interval and this drain electrode 130.
See also Fig. 3-Fig. 9, wherein Fig. 3-Fig. 8 is the structural representation of each making step of thin-film transistor 100 shown in Fig. 2.Fig. 9 is the manufacturing flow chart of thin-film transistor 100 shown in Fig. 2.
Step S301, refers to Fig. 3, provides a substrate 101, forms grid 110 on the substrate 101 and covers the gate insulator 105 of this grid 110.Deposit the first metal layer on the substrate 101, this first metal layer of patterning forms grid 110, then deposits a gate insulator 105, makes this gate insulator 105 cover this grid 110.Wherein, the first metal layer of this patterning can be micro-shadow gold-tinted etching method with the method forming this grid 110.Substrate 101 can be glass substrate or quartz base plate, and this first metal layer can be metal material or metal alloy, as molybdenum (Mo), aluminium (Al), chromium (Cr), copper (Cu), neodymium (Nd) etc.This gate insulator 105 is for can comprise silicon nitride (SiNx) or silica (SiOx).In the present embodiment, the deposition processs such as sputtering method, vacuum vapour deposition, pulsed laser deposition, ion plating, Organometallic Vapor Phase growth method, plasma CVD can be utilized to form gate insulator 105.
Step S303, please continue to refer to Fig. 3, on gate insulator 105, corresponding grid 110 place forms channel layer 103, then forms an etch stop layer 107 to cover whole channel layer 103.Wherein, this channel layer 103 material is metal-oxide semiconductor (MOS), as indium oxide gallium zinc (IGZO), zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO) or its mixture.Particularly, in the present embodiment, can utilize the deposition processs such as sputtering method, vacuum vapour deposition, pulsed laser deposition, ion plating, Organometallic Vapor Phase growth method, plasma CVD on this gate insulator 105, form a metal oxide semiconductor layer, at patterning metal oxide semiconductor layer thus to forming channel layer 103 in grid 105 place.The material of this etch stop layer 107 is transparent organic material, in the present embodiment, this etch stop layer 107 can be the organic material with light sensitive characteristic and also can be the organic material without light sensitive characteristic, wherein, the light sensitive characteristic of this etch stop layer 107 is weaker than the light sensitive characteristic of photoresistance (Photoresistor) material.The infringement that this etch stop layer 107 avoids successive process to cause it for the protection of this channel layer 103, its thickness is generally greater than 1 micron.
Step S305, carries out high temperature firmly roasting (Hard-baking) process to the substrate 101 being formed with this etch stop layer 107.High temperature is firmly roasting makes the planarization make it solidification more of the surface of this etch stop layer 107, effectively can strengthen tack between this etch stop layer 107 and this channel layer 103.In the present embodiment, the temperature that high temperature is baked firmly determines according to the material behavior of etch stop layer 107, and the temperature that general high temperature is baked firmly is within the scope of 100 DEG C ~ 400 DEG C.The organic solvent of the remnants of its inside volatilizees by the barrier material after high temperature is firmly roasting, thus this etch stop layer 107 is solidified, and strengthens the tack between channel layer 103.
Step S307, refers to Fig. 4, on this etch stop layer 107, be coated with photoresist layer 109.
Step S309, refers to Fig. 5, utilizes this photoresist layer 109 of gold-tinted processing procedure patterning thus define perforating holes H1, H2 on the photoresist layer 109 of this patterning.Particularly, light shield (Mask) 14 is utilized to be that shielding carries out to photoresist layer 109 gold-tinted exposure to run through this photoresist layer 109 perforating holes H1, H2 to develop, this perforating holes H1, H2 are the through hole running through this photoresist layer 109 thickness, and distance therebetween equals the narrow channel width desired by the present invention substantially, as: 3-5 micron.Particularly, this light shield 14 comprises two light transmission parts 140 and exposes through UV-irradiation with photoresist layer 109 part of lightproof part 141, two light transmission part 140 correspondence, then forms this perforating holes H1, H2 after development.Distance between the lightproof part 140 of this light shield 14 defines the distance between this perforating holes H1, H2.
Step S311, refer to Fig. 6, doing shielding with this patterning photoresist layer 109 adopts the mode of dry ecthing (Dry-etching) to etch this etch stop layer 107, thus formation through-thickness runs through this etch stop layer 107 and contact hole O1, the O2 through respectively with this perforating holes H1, H2.Therefore, the distance between this contact hole O1, O2 also equals the narrower channel width desired by the present invention substantially, as: 3-5 micron.In the present embodiment, can utilize the dry-etching methods such as electric paste etching (Plasma Etching), reactive ion etching (Reactive Ion Etching, RIE), plasma etching that etch stop layer 107 is etched to channel layer 103.
Step S313, refers to Fig. 7, removes remaining photoresist layer 109.
Step S315, refers to Fig. 8, and this etch stop layer 107 is formed source electrode 120 and drain electrode 130, and this source electrode 120 is filled this contact hole O1, O2 respectively with drain electrode 130 and contacted with this channel layer 103.Particularly, in surface deposition one second metal level of this etch stop layer 107, and utilize one this second metal level of light shield etch process patterning, thus relatively form source electrode 120 and drain electrode 130 in both sides at this channel layer 103, and fill this two contact hole O1, O2.This second metal level is metal material or metal alloy, as molybdenum (Mo), aluminium (Al), chromium (Cr), copper (Cu), neodymium (Nd) etc.Carrying out etching method to the second metal level is wet etching (Wet-Etching) method.
When this thin-film transistor 100 is applied to liquid crystal panel, in successive process, this thin-film transistor 100 can form the conventional construction such as planarization layer, pixel electrode, do not repeat them here.
Refer to Figure 10, Figure 10 is thin-film transistor second execution mode structural representation of the present invention.
The grid 210 of this thin-film transistor 200 is arranged on substrate 201, and the corresponding grid 210 of channel layer 203 is arranged, and gate insulator 210 is arranged between grid 210 and channel layer 203.In the present embodiment, this channel layer 203 is made up of metal-oxide-semiconductor structure, and its material comprises: indium oxide gallium zinc (IGZO), zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO) or its mixture.This thin-film transistor 200 comprises the etch stop layer 207 covering whole channel layer 203 and gate insulation layer 210 surface further; this etch stop layer 207 is for having the transparent insulation structure of certain solidification hardness; avoid successive process to cause damage to it for the protection of this channel layer 203, and a flat surfaces is provided.In the present embodiment, this etch stop layer 207 is a laminated construction, comprises an inorganic barrier layer 207a and the hard mask layer 207b with the stacking setting of this inorganic barrier layer 207a.This inorganic barrier layer 207a is the transparent organic material layer through solidifying process, this transparent organic material layer can be the organic material with light sensitive characteristic and also can be the organic material without light sensitive characteristic, wherein, the light sensitive characteristic of this inorganic barrier layer 207a is weaker than the light sensitive characteristic of photoresistance (Photoresistor) material.This hard mask layer 207b is arranged on this inorganic barrier layer 207a and deviates from the surface of substrate 201, for strengthening the hardness of this inorganic barrier layer 207a.In the present embodiment, the thickness of this hard mask layer 207b is less than the thickness of this inorganic barrier layer 207a, and its material can be selected from the inorganic material such as silicon nitride (SiNx), silica (SiOx), silicon fluoride (SiFx), silicon oxynitride (SiNxOy).Two contact hole O21, O22 through-thickness run through this etch stop layer 207, thus expose part channel layer 203, the channel width L2 of this thin-film transistor 200 of spacing distance correspondence definition between this two contact hole O21, O22.In the present embodiment, the spacing distance between this two contact hole O21, O22 equals the narrow channel width desired by the present invention substantially, is namely less than 10 microns, is preferably 3-5 micron.Correspondingly, the channel width L2 of this thin-film transistor 200 is less than 10 microns, is preferably 3-5 micron.
Further, the source electrode 220 of this thin-film transistor 200 is divided into the relative both sides of channel layer 203 also through contacting with this channel layer 203 via two contact hole O21, O22 with drain electrode 230.In the present invention, this etch stop layer 207 also act as passivation layer and the planarization layer of thin-film transistor 200 simultaneously, for this source/drain 220,230 of interval and this channel layer 230, and provides flat surfaces.
Refer to Figure 11-18 figure, wherein Figure 11-17 each step manufacturing process schematic diagram that is the thin-film transistor 200 shown in Figure 10, Figure 18 is the manufacturing flow chart of thin-film transistor 200 shown in Figure 10.
Step S401, refers to Figure 11, provides a substrate 201, substrate 201 is formed grid 210 and covers the gate insulator 205 of this grid 210.Substrate 201 deposits the first metal layer, and this first metal layer of patterning forms grid 210, then deposits a gate insulator 205, makes this gate insulator 205 cover this grid 210.Wherein, the first metal layer of this patterning can be micro-shadow gold-tinted etching method with the method forming this grid 210.Substrate 201 can be glass substrate or quartz base plate, and this first metal layer can be metal material or metal alloy, as molybdenum (Mo), aluminium (Al), chromium (Cr), copper (Cu), neodymium (Nd) etc.This gate insulator 205 is for can comprise silicon nitride (SiNx) or silica (SiOx).In the present embodiment, the deposition processs such as sputtering method, vacuum vapour deposition, pulsed laser deposition, ion plating, Organometallic Vapor Phase growth method, plasma CVD can be utilized to form gate insulator 205.
Step S403, please continue to refer to Figure 11, on gate insulator 205, corresponding grid 210 place forms channel layer 203, and on this channel layer 203, is coated with inorganic barrier layer 207a to cover whole channel layer 203.This channel layer 203 material is metal-oxide semiconductor (MOS), as indium oxide gallium zinc (IGZO), zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO) or its mixture.Particularly, in the present embodiment, can utilize the deposition processs such as sputtering method, vacuum vapour deposition, pulsed laser deposition, ion plating, Organometallic Vapor Phase growth method, plasma CVD on this gate insulator 205, form a metal oxide semiconductor layer, at patterning metal oxide semiconductor layer thus to forming channel layer 203 in grid 205 place.The material of this inorganic barrier layer 207a is transparent organic material, in the present embodiment, this inorganic barrier layer 207a can be the organic material with light sensitive characteristic and also can be the organic material without light sensitive characteristic, wherein, the light sensitive characteristic of this inorganic barrier layer 207a is weaker than the light sensitive characteristic of photoresistance (Photoresistor) material.The infringement that this inorganic barrier layer 207a avoids successive process to cause it for the protection of this channel layer 103, its thickness is generally greater than 1 micron.
Step S405, carries out high temperature firmly roasting (Hard-baking) process to the substrate 201 being formed with this inorganic barrier layer 207a.High temperature is firmly roasting makes the planarization make it solidification more of the surface of this inorganic barrier layer 207a, and effectively can strengthen tack between this etch stop layer 207 and this channel layer 203.In the present embodiment, the temperature that high temperature is baked firmly determines according to the material behavior of inorganic barrier layer 207a, and the temperature that general high temperature is baked firmly is within the scope of 100 DEG C ~ 400 DEG C.The organic solvent of the remnants of its inside volatilizees by the barrier material after high temperature is firmly roasting, thus this inorganic barrier layer 207a is solidified, and strengthens the tack between channel layer 203.
Step S407, refers to Figure 12, and on this inorganic barrier layer 207a, form hard mask layer 207b, the stacking setting of this hard mask layer 207b and this inorganic barrier layer 207a forms an etch stop layer 207 jointly.In the present embodiment, this hard mask layer 207b is arranged on this inorganic barrier layer 207a and deviates from the surface of substrate 201, for strengthening the hardness of this inorganic barrier layer 207a.In the present embodiment, the thickness of this hard mask layer 207b is less than the thickness of this inorganic barrier layer 207a, and its material can be selected from the inorganic material such as silicon nitride (SiNx), silica (SiOx), silicon fluoride (SiFx), silicon oxynitride (SiNxOy).In the present embodiment, the method depositions such as chemical vapour deposition (CVD) (CVD), physical vapour deposition (PVD) (PVD), evaporation, sputter can be utilized to form this hard mask layer 207b.This hard mask layer 207b material is the materials such as silicon nitride (SiNx), silica (SiOx), silicon fluoride (SiFx).
Step S409, refers to Figure 13, on this etch stop layer 207, be coated with photoresist layer 209.
Step S411, refers to Figure 14, utilizes this photoresist layer 209 of gold-tinted processing procedure patterning thus define perforating holes H21, H22 on the photoresist layer 209 of this patterning.Particularly, light shield (Mask) 24 is utilized to be that shielding carries out to photoresist layer 209 gold-tinted exposure to run through this photoresist layer 209 perforating holes H21, H22 to develop, this perforating holes H21, H22 are the through hole running through this photoresist layer 209 thickness, and distance therebetween equals the narrower channel width desired by the present invention substantially, namely be less than 10 microns, be preferably 3-5 micron.Particularly, this light shield 24 comprises two light transmission parts 240 and exposes through UV-irradiation with photoresist layer 209 part of lightproof part 241, two light transmission part 240 correspondence, then forms this perforating holes H21, H22 after development.Distance between the lightproof part 240 of this light shield 24 defines the distance between this perforating holes H21, H22.
Step S413, refer to Figure 15, make with this patterning photoresist layer 209 this hard mask layer 207b of mode and this inorganic barrier layer 207 that shielding adopts dry ecthing (Dry-etching), thus formation through-thickness runs through contact hole O21, O22 of this hard mask layer 207b and this inorganic barrier layer 207.Therefore, the distance between this contact hole O21, O22 also equals the narrower channel width L2 desired by the present invention substantially, is namely less than 10 microns, is preferably 3-5 micron.In the present embodiment, can utilize the dry-etching methods such as electric paste etching (Plasma Etching), reactive ion etching (Reactive Ion Etching, RIE), plasma etching that etch stop layer 207 is etched to channel layer 203.
Step S415, refers to Figure 16, removes remaining photoresist layer 209.
Step S417, refers to Figure 17, and this hard mask layer 207b is formed source electrode 220 and drain electrode 230, and this source electrode 220 is filled this contact hole O21, O22 respectively with drain electrode 230 and contacted with this channel layer 203.Particularly, in surface deposition one second metal level of this etch stop layer 207, and utilize one this second metal level of light shield etch process patterning, thus relatively form source electrode 220 and drain electrode 230 in both sides at this channel layer 203, and fill this two contact hole O21, O22.This second metal level is metal material or metal alloy, as molybdenum (Mo), aluminium (Al), chromium (Cr), copper (Cu), neodymium (Nd) etc.Carrying out etching method to the second metal level is wet etching (Wet-Etching) method.
When this thin-film transistor 200 is applied to liquid crystal panel, in successive process, this thin-film transistor 200 can form the conventional construction such as planarization layer, pixel electrode, do not repeat them here.
Thin-film transistor of the present invention and use the manufacture method of this thin-film transistor array base-plate etch stop layer to be done the firmly roasting process of high temperature, and utilize one gold-tinted etch process to carry out exposure imaging to photoresistance to go out the distance perforating holes approximate with expection transistor channel width, dry etching technology is utilized to be etched with to etch stop layer the thin-film transistor that acquisition has narrower channel width more further, to improve the characteristic of thin-film transistor, and meet the demand of panel high-resolution.
Above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not depart from the spirit and scope of technical solution of the present invention.
Claims (13)
1. a manufacture method for thin-film transistor, this manufacture method comprises:
On a substrate, form grid and cover the gate insulator of this grid;
On this gate insulator, corresponding grid place forms channel layer, and on this channel layer, form the etch stop layer covering this channel layer;
The firmly roasting process of high temperature is carried out to the substrate being formed with this etch stop layer;
Photoresist layer is formed on this etch stop layer;
This photoresist layer of patterning thus define the perforating holes that two run through this photoresist layer on the photoresist layer of this patterning;
Do this etch stop layer of shielding dry ecthing with this patterning photoresistance, run through this etch stop layer and two contact holes exposing this channel layer to form through-thickness;
Remove remaining photoresist layer; And
This etch stop layer is formed source electrode and drain electrode, and this source electrode contacts with this channel layer via this contact hole with drain electrode.
2. method for fabricating thin film transistor according to claim 1, is characterized in that, this etch stop layer is a transparent organic material layer.
3. method for fabricating thin film transistor according to claim 2, is characterized in that, this transparent organic material layer has light sensitive characteristic, and the light sensitive characteristic of this transparent organic material is weaker than the light sensitive characteristic of this photoresist layer.
4. method for fabricating thin film transistor according to claim 1, is characterized in that, the temperature that high temperature is baked firmly sets within the scope of 100 DEG C ~ 400 DEG C according to this barrier material.
5. method for fabricating thin film transistor according to claim 1, is characterized in that, the distance between this two perforating holes is less than 10 microns.
6. method for fabricating thin film transistor according to claim 1, is characterized in that, the distance between this two perforating holes is between 3-5 micron.
7. method for fabricating thin film transistor according to claim 1, it is characterized in that, the step of this photoresist layer of patterning comprises further: provide a light shield, this light shield comprises two light transmission parts and lightproof part, it is characterized in that, the spacing of two light transmission parts is for defining the spacing between this perforating holes; With this light shield for shielding exposure, develop this photoresist layer, thus on this photoresist layer, define this two perforating holes.
8. method for fabricating thin film transistor according to claim 1, is characterized in that, the method doing this etch stop layer of shielding dry ecthing with this patterning photoresist layer is selected from electric paste etching, reactive ion etching or plasma etching method.
9. method for fabricating thin film transistor according to claim 1, it is characterized in that, this etch stop layer comprises inorganic barrier layer and a hard mask layer of stacking setting, this inorganic barrier layer is the transparent organic material layer through solidifying process, this hard mask layer is formed in this inorganic barrier layer and deviates from the surface of this channel layer, for strengthening the hardness of this inorganic barrier layer.
10. method for fabricating thin film transistor according to claim 9, is characterized in that, this inorganic barrier layer is the organic material with light sensitive characteristic, and the light sensitive characteristic of this inorganic barrier layer is weaker than the light sensitive characteristic of this photoresist layer.
11. method for fabricating thin film transistor according to claim 10, is characterized in that, the thickness of this hard mask layer is less than the thickness of this inorganic barrier layer.
12. method for fabricating thin film transistor according to claim 10, is characterized in that, this hard multitudinous cap layer material is silicon oxynitride, silicon nitride, silica or silicon fluoride.
The manufacture method of 13. 1 kinds of array of display substrates, this manufacture method comprises:
There is provided a substrate, and form multiple thin-film transistor on this substrate, wherein the manufacture method of this thin-film transistor is the manufacture method described in claims 1-12 item any one.
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