CN104409605B - A kind of high-voltage chip LED structure and preparation method thereof - Google Patents
A kind of high-voltage chip LED structure and preparation method thereof Download PDFInfo
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- CN104409605B CN104409605B CN201410710007.2A CN201410710007A CN104409605B CN 104409605 B CN104409605 B CN 104409605B CN 201410710007 A CN201410710007 A CN 201410710007A CN 104409605 B CN104409605 B CN 104409605B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 190
- 238000002955 isolation Methods 0.000 claims abstract description 53
- 230000007797 corrosion Effects 0.000 claims abstract description 46
- 238000005260 corrosion Methods 0.000 claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 43
- 230000004888 barrier function Effects 0.000 claims abstract description 41
- 238000002161 passivation Methods 0.000 claims abstract description 28
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 44
- 238000000926 separation method Methods 0.000 claims description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 238000009413 insulation Methods 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 9
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 239000004593 Epoxy Substances 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 4
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 229910001882 dioxygen Inorganic materials 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 4
- 235000013842 nitrous oxide Nutrition 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000009616 inductively coupled plasma Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 17
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 238000003851 corona treatment Methods 0.000 abstract description 3
- 230000007812 deficiency Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 357
- 238000005516 engineering process Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 150000001336 alkenes Chemical class 0.000 description 1
- 238000005282 brightening Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- JRZJOMJEPLMPRA-UHFFFAOYSA-N olefin Natural products CCCCCCCC=C JRZJOMJEPLMPRA-UHFFFAOYSA-N 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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Abstract
The present invention provides a kind of high-voltage chip LED structure and preparation method thereof, by setting contact layer to protect n type semiconductor layer on n type semiconductor layer, protects it from the influence of etching plasma bulk damage, solves the voltage problem of high-voltage chip；Also, before contact layer formation, barrier layer, corrosion auxiliary layer and side wall overprotection layer are synchronously formd, while LED chip light type is solved, the reliability and breakdown characteristics of LED chip is improved.Secondly, by dynamic etching technics formation isolation channel, solving conventional etching process etching homogeneity deficiency causes the problem of chip fails because of short circuit.Again, before final passivation protection film is formed, surface and side wall to high voltage LED chip carry out corona treatment, the problem of solving high voltage LED chip cut-in voltage.
Description
Technical field
The invention belongs to semiconductor optoelectronic chip manufacturing field, more particularly to a kind of high-voltage chip LED structure and its making
Method.
Background technology
Since early 1990s are commercialized, by the development of twenties years, GaN base LED was widely used
In fields such as indoor and outdoor display screen, Projection Display lighting source, backlight, landscape brightening illumination, advertisement, traffic instructions, and
It is described as 21st century most competitive solid light source of new generation.But for light emitting semiconductor device LED, generation
For conventional light source, into high-end lighting field, it is necessary to consider two factors：One is the lifting of luminosity, and two be yield and can
By the lifting of property.
In recent years, under the excitation and promotion of the various policies of government, it is various for improve LED luminosity technology meet the tendency of and
It is raw, for example patterned substrate technology, side wall coarsening technique, DBR technologies, optimization electrode structure, on substrate or nesa coating
Make 2 D photon crystal etc..Wherein patterned substrate technology most effect, between 2010 to 2012, the cone of front and rear appearance
The dry method patterned substrate of shape structure and the wet method pattern substrate of Pyramid instead of the flat sapphire in surface completely
Substrate turns into the main flow substrate of LED chip, LED crystal structure and luminosity is obtained for revolutionary raising.
With the high speed development of semiconductor integration technology, a kind of LED structure for being referred to as high-voltage chip is arisen at the historic moment, Ci Zhongjie
The LED of structure be usually after light emitting semiconductor layer is formed, by lithographic etch process formed in the light emitting semiconductor layer every
Separation layer is filled from groove, then in isolation channel, electrode is finally made in the light emitting semiconductor layer of each insulated separation and string is formed
It is coupled structure；Although such a structure can improve LED luminosity, make on LED luminosity a new step, this
The yield and reliability of LED chip can also be reduced by planting manufacture craft；First, caused by the limitation of existing etching technics uniformity
Always with the presence of subregion semi-conducting material residual phenomena series chip can be caused to be failed because of short circuit in the isolation channel of formation；
Secondly, it is easy on the side wall of isolation channel form residual during contact layer is formed, this will largely effect on LED chip
Reliability and breakdown characteristics, it can even influence cut-in voltage；3rd, filled by deposition and etching technics in isolation channel
During separation layer, plasma etching can produce loss to semiconductor layer, and this leverages the voltage of LED chip；Finally,
Contact layer edge sawtooth phenomenon can influence the light type of LED chip caused by the isotropic influence corroded due to contact layer.
A kind of high-voltage chip LED structure of above mentioned problem and preparation method thereof is can solve the problem that it would therefore be highly desirable to research and develop.
The content of the invention
High-voltage chip LED reliabilities and breakdown characteristics are improved it is an object of the invention to provide one kind and can be reduced simultaneously
LED structure of its production cost and preparation method thereof.
To solve the above problems, the present invention provides a kind of high-voltage chip LED structure preparation method, including：
One substrate is provided；
Light emitting semiconductor layer is formed over the substrate, and the light emitting semiconductor layer includes the N-type semiconductor stacked gradually
Layer, active layer and p type semiconductor layer；
Etch the light emitting semiconductor layer and form some notch cuttype through hole, the notch cuttype through hole include groove and with institute
The isolation channel of groove connection is stated, the groove exposes the surface of the n type semiconductor layer, and the isolation channel exposes the substrate
Surface, the cross-sectional width of the groove is more than the cross-sectional width of the isolation channel, and the notch cuttype through hole is by light emitting semiconductor layer
It is divided into the independent light emitting semiconductor layer of some separation；
Insulation film is formed on the p type semiconductor layer and the inwall of notch cuttype through hole, and it is thin to etch the insulation
Film synchronously forms barrier layer, corrosion auxiliary layer and side wall overprotection layer, and the barrier layer and corrosion auxiliary layer are respectively positioned on institute
State on p type semiconductor layer and the corrosion auxiliary layer annularly surrounds the barrier layer, the side wall overprotection layer covering institute
State the side wall of groove and the side wall and bottom wall of isolation channel and be connected with the corrosion auxiliary layer；
Contact film is formed on the p type semiconductor layer, barrier layer, corrosion auxiliary layer and side wall overprotection layer, is carved
Etching off is except the corrosion auxiliary layer and the contact film formation contact layer on side wall overprotection layer；
Etching removes the corrosion auxiliary layer and side wall overprotection layer；
Separation layer is filled in the isolation channel of each independent light emitting semiconductor layer；
First electrode is formed on the contact layer above the barrier layer of each independent light emitting semiconductor layer, in each independent hair
Second electrode is formed on contact layer in the notch cuttype through hole of photosemiconductor layer, and by the adjacent independent light emitting semiconductor layer in part
Second electrode and first electrode be electrically connected to form cascaded structure；
Passivation protection layer, the passivation protection layer tool are formed on the surface of independent all exposures of light emitting semiconductor layer
The first electrode in independent light emitting semiconductor layer headed by having in the exposure cascaded structure and the independent emitting semiconductor for tail
The fairlead of second electrode on layer.
Optionally, in described high-voltage chip LED structure preparation method, by dynamic etching technics described luminous half
Isolation channel is formed in conductor layer, the dynamic etching technics includes：
Step one：The substrate geo-stationary is in the reaction cavity of etching machine bench, using inductively coupled plasma pair
Light emitting semiconductor layer performs etching technics；
Step 2：Sense coupling technique is terminated, symmetry motion occurs for the substrate；
Repeat the above steps one and step 2 until forming the isolation channel.
Optionally, in described high-voltage chip LED structure preparation method, after cascaded structure is formed, form described
Before passivation protection layer, in addition to：The side wall on surface and notch cuttype through hole to light emitting semiconductor layer carries out plasma treatment.Institute
Plasma is stated for laughing gas plasma or oxygen gas plasma.
Optionally, in described high-voltage chip LED structure preparation method, the side wall overprotection layer also extends to institute
State the subregion of groove bottom wall.
Optionally, in described high-voltage chip LED structure preparation method, in the p type semiconductor layer, barrier layer, corruption
Formed on erosion auxiliary layer and side wall overprotection layer and photoresist layer is formed after contact film, the photoresist layer exposes the corrosion
Auxiliary layer and the contact film on side wall overprotection layer, the corrosion auxiliary layer is removed by mask etching of the photoresist layer
With the contact film formation contact layer on side wall overprotection layer.The photoresist layer used during contact layer is formed, is connect in formation
Remained after contact layer as the mask layer for removing corrosion auxiliary layer and side wall overprotection layer, institute is removed before filling separation layer
State photoresist layer.
Optionally, in described high-voltage chip LED structure preparation method, the separation layer is epoxy radicals photoresist, third
At least one of olefin(e) acid base photoresist, SOG or polyimides.
Optionally, in described high-voltage chip LED structure preparation method, the material of the contact layer is ITO.
Optionally, in described high-voltage chip LED structure preparation method, the of the independent light emitting semiconductor layer is formed
Connection electrode layer, the second electrode of the adjacent independent light emitting semiconductor layer in part and are formed while one electrode and second electrode
One electrode is electrically connected to form cascaded structure by the connection electrode layer.
Optionally, in described high-voltage chip LED structure preparation method, the separation layer also covers adjacent independent hair
The P-type semiconductor layer surface of photosemiconductor layer.
According to the another side of the present invention, a kind of high-voltage chip LED structure is also provided, including：
Substrate；
The light emitting semiconductor layer on the substrate is formed at, the N-type that the light emitting semiconductor layer includes stacking gradually partly is led
Body layer, active layer and p type semiconductor layer；
Be formed at some notch cuttype through hole in the light emitting semiconductor layer, the notch cuttype through hole include groove and with
The isolation channel of the groove connection, the groove exposes the surface of the n type semiconductor layer, and the isolation channel exposes the substrate
Surface, the cross-sectional width of the groove is more than the cross-sectional width of the isolation channel, and the notch cuttype through hole is by emitting semiconductor
Layer is divided into the independent light emitting semiconductor layer of some separation；
It is formed at the barrier layer on the p type semiconductor layer；
It is formed on the p type semiconductor layer and covering barrier layer and the contact that is formed on the n type semiconductor layer
Layer；
It is formed in the isolation channel of each independent light emitting semiconductor layer and covers the p-type of adjacent independent light emitting semiconductor layer
The separation layer of semiconductor layer surface；
The first electrode on the contact layer above the barrier layer of each independent light emitting semiconductor layer is formed at, is formed at each
The second electrode on contact layer in the notch cuttype through hole of independent light emitting semiconductor layer, the adjacent independent light emitting semiconductor layer in part
Second electrode and first electrode be electrically connected to form cascaded structure；And
It is formed at the passivation protection layer on the surface of all exposures of independent light emitting semiconductor layer, the passivation protection layer
Partly led with the first electrode in the independent light emitting semiconductor layer headed by exposing in the cascaded structure and for the independence of tail is luminous
The fairlead of second electrode on body layer.
Optionally, in described high-voltage chip LED structure, the separation layer is epoxy radicals photoresist, acrylic light
At least one of photoresist, SOG or polyimides.
Optionally, in described high-voltage chip LED structure, the material of the contact layer is ITO.
Optionally, in described high-voltage chip LED structure, formed the independent light emitting semiconductor layer first electrode and
Connection electrode layer is formed while second electrode, the second electrode and first electrode of the adjacent independent light emitting semiconductor layer in part are led to
Cross the connection electrode layer and be electrically connected to form cascaded structure.
Compared with prior art, high-voltage chip LED structure that the present invention is provided and preparation method thereof, by partly being led in N-type
Set contact layer to protect n type semiconductor layer on body layer, protect it from the influence of etching plasma bulk damage, solve high-voltage chip
Voltage problem；Also, before contact layer formation, barrier layer, corrosion auxiliary layer and side wall overprotection layer are synchronously formd,
While LED chip light type is solved, the reliability and breakdown characteristics of LED chip are improved.
Secondly, the high-voltage chip LED structure preparation method that the present invention is provided, by dynamic etching technics formation isolation channel,
Solving conventional etching process etching homogeneity deficiency causes the problem of chip fails because of short circuit.
Again, the high-voltage chip LED structure preparation method that the present invention is provided, before final passivation protection film is formed,
Surface and side wall to high voltage LED chip carry out corona treatment, the problem of solving high voltage LED chip cut-in voltage.
In addition, the first electrode and second electrode of each independent emitting semiconductor can form independent luminous according to demand
Electrically connected while semiconductor first electrode and second electrode by connection electrode layer, that is, form the cascaded structure of any number,
The independent light emitting semiconductor layer for forming cascaded structure is cut without individually being tested again, individually, individually encapsulated, and reduces into
This；Also, because each light emitting semiconductor layer can form cascaded structure while electrode is formed, so provided by the present invention
LED structure can be in larger operating at voltages.
Brief description of the drawings
Referring to the drawings, according to following detailed description, the present invention can be more clearly understood from.For the sake of clarity, scheme
In the relative thickness of each layer and the relative size of given zone be not drawn to draw.In the accompanying drawings：
Fig. 1 is substrat structure schematic diagram in one embodiment of the invention；
Fig. 2 is the structural representation formed after light emitting semiconductor layer in one embodiment of the invention；
Fig. 3 is the structural representation formed after groove in one embodiment of the invention；
Fig. 4 is the structural representation formed after isolation channel in one embodiment of the invention；
Fig. 5 is the structural representation formed after insulation film in one embodiment of the invention；
Fig. 6 is the structural representation formed in one embodiment of the invention after barrier layer, corrosion auxiliary layer and side wall protective layer；
Fig. 7 is the structural representation formed in one embodiment of the invention after contact film；
Fig. 8 is the structural representation formed after contact layer in one embodiment of the invention；
Fig. 9 is that the structural representation after corrosion auxiliary layer and side wall protective layer is removed in one embodiment of the invention；
Figure 10 is the structural representation after filling separation layer in one embodiment of the invention；
Figure 11 a are Figure 10 plan structure sketches；
Figure 11 b are the profiles along 11a dotted lines；
Figure 12 is the structural representation formed after electrode in one embodiment of the invention
Figure 13 is the structural representation formed in one embodiment of the invention after passivation protection layer；
Figure 14 is light emitting semiconductor layer rotational structure schematic diagram in one embodiment of the invention；
Figure 15 is the structural representation that passivation protection layer is formed after fairlead in one embodiment of the invention；
Figure 16 is the schematic flow sheet of one embodiment of the invention mesohigh chip LED construction manufacturing method.
Embodiment
The various exemplary embodiments of the present invention are described in detail now with reference to accompanying drawing.
As shown in figure 16, high-voltage chip LED structure preparation method of the invention, comprises the following steps：
S1：One substrate is provided；
S2：Light emitting semiconductor layer is formed over the substrate, and the N-type that the light emitting semiconductor layer includes stacking gradually partly is led
Body layer, active layer and p type semiconductor layer；
S3：Etch the light emitting semiconductor layer and form some notch cuttype through hole, the notch cuttype through hole include groove and
The isolation channel connected with the groove, the groove exposes the surface of the n type semiconductor layer, and the isolation channel exposes the lining
The surface at bottom, the cross-sectional width of the groove is more than the cross-sectional width of the isolation channel, and the notch cuttype through hole is partly led luminous
Body layer is divided into the independent light emitting semiconductor layer of some separation；
S4：Insulation film is formed on the p type semiconductor layer and the inwall of notch cuttype through hole, and etches the insulation
Film synchronously forms barrier layer, corrosion auxiliary layer and side wall overprotection layer, and the barrier layer and corrosion auxiliary layer are respectively positioned on
On the p type semiconductor layer and the corrosion auxiliary layer annularly surrounds the barrier layer, the side wall overprotection layer covering
The side wall of the groove and the side wall and bottom wall of isolation channel are simultaneously connected with the corrosion auxiliary layer；
S5：Contact film is formed on the p type semiconductor layer, barrier layer, corrosion auxiliary layer and side wall overprotection layer,
Etching removes the corrosion auxiliary layer and the contact film formation contact layer on side wall overprotection layer；
S6：Etching removes the corrosion auxiliary layer and side wall overprotection layer；
S7：Separation layer is filled in the isolation channel of each independent light emitting semiconductor layer, the separation layer also covers adjacent
The part surface of the p type semiconductor layer of independent light emitting semiconductor layer；
S8：First electrode is formed on the contact layer above the barrier layer of each independent light emitting semiconductor layer, each only
Form second electrode on contact layer in the notch cuttype through hole of vertical light emitting semiconductor layer, and partly lead the adjacent independence in part is luminous
The second electrode and first electrode of body layer are electrically connected to form cascaded structure；
S9：Passivation protection layer, the passivation protection are formed on the surface of independent all exposures of light emitting semiconductor layer
Layer is with the first electrode in the independent light emitting semiconductor layer headed by exposing in the cascaded structure and is the independence of tail luminous half
The fairlead of second electrode in conductor layer.
High-voltage chip LED structure provided by the present invention and preparation method thereof is described in more detail with reference to Fig. 1-15.
It should be noted that, accompanying drawing is using very simplified form and uses non-accurately ratio, only conveniently, lucidly to aid in
Illustrate the purpose of the embodiment of the present invention.
As shown in figure 1, performing step S1, there is provided a substrate 1.The substrate 1 is preferably Sapphire Substrate, further,
The substrate 1 is patterned Sapphire Substrate.
As shown in Fig. 2 performing step S2, hair is formed on the substrate 1 by MOCVD techniques or molecular beam epitaxy technique
Photosemiconductor layer 2, the light emitting semiconductor layer 2 at least includes stacking gradually n type semiconductor layer 21, active layer on substrate 1
22 and p type semiconductor layer 23.
As shown in Figure 3 and Figure 4, step S3 is performed, the light emitting semiconductor layer 2 is etched and forms some notch cuttype through hole, institute
Stating notch cuttype through hole includes groove 3 and the isolation channel 4 connected with the groove 3, and the cross-sectional width of the groove 3 is more than described
The cross-sectional width of isolation channel 4, the groove 3 exposes the surface of the n type semiconductor layer 21, and the isolation channel 4 exposes the lining
Light emitting semiconductor layer 2 is divided into the independent light emitting semiconductor layer of some separation by the surface at bottom 1, the notch cuttype through hole.
Specifically, in the step S3, first, as shown in figure 3, by conventional lithographic etch process described luminous
The presumptive area formation groove 3 of semiconductor layer 2, the groove 3 is partly led through p type semiconductor layer 23, active layer 22 and part N-type
Body layer 21, i.e. p type semiconductor layer 23 and active layer 22 in groove 3 are removed completely, and n type semiconductor layer 21 is removed one
Part；Then, as shown in figure 4, forming isolation channel 4 in the light emitting semiconductor layer 2, the isolation channel 4 exposes the substrate 1
Surface, i.e. p type semiconductor layer 23, active layer 22 and n type semiconductor layer 21 in isolation channel 4 are removed completely, the He of groove 3
Isolation channel 4 collectively forms notch cuttype through hole wide at the top and narrow at the bottom.
In preferred embodiment, isolation channel 4 is formed in the light emitting semiconductor layer 2 by dynamic etching technics, it is described dynamic
State etching technics comprises the following steps：
Step one：The geo-stationary of substrate 1 is in the reaction cavity of etching machine bench, using inductively coupled plasma pair
Light emitting semiconductor layer 2 performs etching technics；
Step 2：Sense coupling technique is terminated, symmetry motion occurs for the substrate 1；
Circulating repetition step one and step 2 are until form isolation channel 4.
Due to plasma skewness in the reaction cavity of usual etching machine bench, if substrate 1 rests on one all the time
Position is until uniformity is undesirable in the etching of completion isolation channel, piece, therefore the substrate 1 is carried out into symmetry fortune in step 2
Dynamic, i.e., described substrate 1 is turned an angle after etching every time, and etching is carried out in diverse location every time, is so eliminated anti-
The uneven influence brought of ion distribution in cavity is answered, by above-mentioned dynamic etching technics formation isolation channel 4, existing quarter is solved
The problem of high-voltage chip fails because of short circuit caused by erosion uniformity is not good.
As shown in Figure 5 and Figure 6, step S4, the shape on the p type semiconductor layer 23 and the inwall of notch cuttype through hole are performed
Into insulation film 5, etching insulation film 5 is synchronous to be formed barrier layer 51, corrodes auxiliary layer 52 and side wall overprotection layer 53, described
Barrier layer 51 and corrosion auxiliary layer 52 are located on the p type semiconductor layer 23 and the corrosion auxiliary layer 52 annularly surrounds institute
State barrier layer 51, the side wall of the covering groove 3 of side wall overprotection layer 53 and the side wall and bottom wall of isolation channel 4.
Specifically, in the step S4, first, as shown in figure 5, by PECVD or LPCVD techniques in the p-type half
Insulation film 5 is formed on the inwall of conductor layer 23 and notch cuttype through hole；Then, as shown in fig. 6, having by lithographic etch process
Selectively erodable section insulation film 5, synchronous to form barrier layer 51, corrode auxiliary layer 52 and side wall overprotection layer 53, described
Side wall overprotection layer 53 is formed at the subregion of the notch cuttype through hole inwall and is connected with the corrosion auxiliary layer 52, enters
One step, the side wall overprotection floor 53 also extends to the bottom wall of the groove 3 i.e. part area on the surface of n type semiconductor layer 21
Domain, that is to say, that the edge of the step of notch cuttype through hole is covered by side wall overprotection layer 53.
As shown in Figure 7 and Figure 8, step S5 is performed, in the light emitting semiconductor layer 2, barrier layer 51, corrosion auxiliary layer 52 and
Contact film 6 is formed on side wall overprotection layer 53, and etches the removal corrosion auxiliary layer 52 and side wall overprotection layer 53
On contact film, formed contact layer 61.
The present invention synchronously forms barrier layer 51, corrosion auxiliary layer 52 and side wall overprotection before contact layer is formed
Layer 53, because the corrosion auxiliary layer 52 annularly surrounds the barrier layer 51 equivalent to the contact layer for defining formation to be etched
Border, such as described corrosion auxiliary layer 52 is rectangular ring, then can then etch and obtain the smooth contact layer 61a of rectangular edges,
While LED chip light type is solved, the reliability and breakdown characteristics of LED chip are improved.
Specifically, in the step S5, first, as shown in fig. 7, entirely being served as a contrast by evaporation, sputtering or spraying coating process
Basal surface formation contact film 6, the material of the contact layer 6 is, for example, ITO；Then, by photoetching process in p type semiconductor layer
23 and barrier layer 51 on form photoresist layer, the photoresist layer exposure corrosion auxiliary layer 52 and side wall overprotection layer
Contact film on 53, then using the photoresist layer as mask, etching removes the corrosion auxiliary layer 52 and side wall overprotection
Contact film on layer 53, only retains the contact film formation contact layer 61 on p type semiconductor layer 23 and barrier layer 51, such as schemes
Shown in 8, the contact layer 61 includes part 61a and side wall overprotection layer 53 in corrosion auxiliary layer 52 closed area
Part 61b in closed area.The present invention on n type semiconductor layer 21 by setting contact layer 61b to protect n type semiconductor layer
21, n type semiconductor layer 21 can be made from the influence of etching plasma bulk damage, the voltage problem of high-voltage chip is solved.
As shown in figure 9, step S6 is performed, as shown in figure 9, removing corrosion auxiliary layer 52 and side wall overprotection layer 53.
Preferably, the photoresist layer used when forming contact layer 61 in the step S5, after contact layer is formed simultaneously
Do not remove, the photoresist layer is remained removes corrosion auxiliary layer 52 and side wall overprotection layer 53 as wet method in step S6
Mask layer, the photoresist is removed before step S7.
As shown in Figure 10, step S7 is performed, the filling separation layer 7 in isolation channel 4.The plan structure that Figure 11 a are Figure 10 is shown
It is intended to, Figure 11 b are the profiles along dotted line.As shown in Figure 11 a-11b, the separation layer 7 also covers adjacent independence luminous half
The surface of p type semiconductor layer 23 of conductor layer, to ensure that the side of light emitting semiconductor layer 2 is completely covered in the separation layer 7, is realized exhausted
Edge isolates the purpose of adjacent independent light emitting semiconductor layer.The top surface of the separation layer 7 is preferably inclined plane, it is furthermore preferred that institute
The angle [alpha] stated between the top surface of insulating barrier 7 and the bottom wall of groove 3 is 135 degree, in order to be subsequently formed connection electrode layer.Wherein,
The separation layer 7 can be SU-8 (epoxy radicals photoresist), WPR (acrylic photoresist), SOG or polyimides in extremely
Few one kind.
As shown in figure 12, step S8 is performed, the contact layer 61a in the top of barrier layer 51 of each independent light emitting semiconductor layer
The second electricity is formed on upper formation first electrode 81, the contact layer 61b in the notch cuttype through hole of each independent light emitting semiconductor layer
Pole 82, and selectively and synchronously lead to the second electrode 82 and first electrode 81 of the adjacent independent light emitting semiconductor layer in part
Cross connection electrode layer 83 and electrically connect (first electrode 81, second electrode 82 and the electrode of the adjacent independent light emitting semiconductor layer in part
Articulamentum 83 connects into an overall structure), make the tube core formation cascaded structure that part is adjacent.The high-voltage chip LED junction of the present invention
In structure preparation method, electrode can be formed while independent emitting semiconductor first electrode and second electrode is formed according to demand
Articulamentum 83, that is, form the cascaded structure of any number, forms the independent light emitting semiconductor layer of cascaded structure without carrying out list again
Solely test, individually cutting, individually encapsulation, have saved test, cutting and packaging cost；Secondly as described each lights and partly led
Body layer can form cascaded structure while electrode is formed, thus the high-voltage chip LED structure can under larger voltage work
Make.
As shown in Figure 13 and Figure 15, step S9, the shape on the surface of independent all exposures of light emitting semiconductor layer are performed
Into passivation protection layer 9, the passivation protection layer has in the independent light emitting semiconductor layer headed by exposing in the cascaded structure
First electrode and the fairlead 91,92 for the second electrode in the independent light emitting semiconductor layer of tail.
Specifically, in step s 9, as shown in figure 13, by evaporation, sputtering, PECVD or LPCVD techniques in the independence
Passivation protection layer 9 is formed on the side wall of all exposures of light emitting semiconductor layer；Then, as shown in figure 15, lithographic etch process is passed through
To the first electrode 81 in the independent light emitting semiconductor layer headed by cascaded structure and be in the independent light emitting semiconductor layer of tail the
Passivation protection layer 9 on two electrodes 82 carries out hole opening technology formation fairlead 91,92, the independent emitting semiconductor headed by exposing
The subregion of first electrode 81 and the subregion for second electrode 82 in the independent light emitting semiconductor layer of tail on layer, in order to
Lead.The material of the passivation protection layer 9 is, for example, silica.
In the present embodiment, also include the surface to light emitting semiconductor layer and groove 3 before passivation protection layer 9 is formed
Plasma treatment is carried out with the side wall of isolation channel 4, the plasma is laughing gas plasma or oxygen gas plasma.The present invention
Remove corrosion auxiliary layer 52 and side wall overprotection layer 53 exposes the side wall of groove, thus can use laughing gas or oxygen gas plasma
It can remove and hang chemical bond on the wall of side, so that why the problem of solving to puncture, further, the present invention are forming contact layer 61
Afterwards, carry out the corona treatment before forming passivation protection layer 9, then be because the protection that has contact layer 61 can be avoided etc. from
Daughter damages p type semiconductor layer.
It is preferred that, as shown in figure 14, in order to form surface on the upper surface of independent light emitting semiconductor layer and its each side wall
Flat passivation protection layer 9, during forming passivation protection layer, while substrate 1 revolves round the sun under the drive of carrier 100,
The substrate 1 is also carrying out high speed rotation (i.e. light emitting semiconductor layer is doing the revolution of two kinds of forms).
With reference to Fig. 1 to Figure 15, the present invention also provides a kind of LED structure, including：
Substrate 1；
The light emitting semiconductor layer 2 on the substrate 1 is formed at, the light emitting semiconductor layer includes the N-type half stacked gradually
Conductor layer 21, active layer 22 and p type semiconductor layer 23；
Be formed at some notch cuttype through hole in the light emitting semiconductor layer 2, the notch cuttype through hole include groove 3 and
The isolation channel 4 connected with the groove 3, the groove 3 exposes the surface of the n type semiconductor layer 21, and the isolation channel 4 exposes
The surface of the substrate 1, the cross-sectional width of the groove 3 is more than the cross-sectional width of the isolation channel 4, and the notch cuttype through hole will
Light emitting semiconductor layer 2 is divided into the independent light emitting semiconductor layer of some separation；
It is formed at the barrier layer 51 on the p type semiconductor layer 23；
It is formed on the p type semiconductor layer 23 and covering barrier layer 51 and is formed on the n type semiconductor layer 21
Contact layer 61；
It is formed in the isolation channel of each independent light emitting semiconductor layer and covers the p-type of adjacent independent light emitting semiconductor layer
The separation layer 7 of semiconductor layer surface；
It is formed at the first electrode 81 on the contact layer 61a of the top of barrier layer 51 of each independent light emitting semiconductor layer, shape
Second electrode 82 on the contact layer 61b in the notch cuttype through hole in each independent light emitting semiconductor layer, adjacent only in part
The second electrode 82 and first electrode 81 of vertical light emitting semiconductor layer are electrically connected to form cascaded structure by connection electrode layer 83；
It is formed at the passivation protection layer 9 on the surface of all exposures of independent light emitting semiconductor layer, the passivation protection
Layer 9 is with the first electrode in the independent light emitting semiconductor layer headed by exposing in the cascaded structure and is the independence of tail luminous half
The fairlead 91,92 of second electrode in conductor layer.
In summary, high-voltage chip LED structure that the present invention is provided and preparation method thereof has advantages below：
1st, before contact layer formation, barrier layer, corrosion auxiliary layer and side wall overprotection layer is synchronously formd, is being solved
While LED chip light type, the reliability and breakdown characteristics of LED chip are improved；
2nd, by dynamic etching technics formation isolation channel, solving conventional etching process etching homogeneity deficiency causes chip
The problem of being failed because of short circuit；
3rd, by setting contact layer to protect n type semiconductor layer on n type semiconductor layer, etching plasma damage is protected it from
The influence of wound, solves the voltage problem of high-voltage chip；
4th, before final passivation protection film is formed, surface and side wall to high voltage LED chip are carried out at plasma
Reason, the problem of solving high voltage LED chip cut-in voltage；
5th, the first electrode and second electrode of each independent emitting semiconductor can form independent luminous half according to demand
Electrically connected while conductor first electrode and second electrode by connection electrode layer, that is, form the cascaded structure of any number, shape
Into cascaded structure independent light emitting semiconductor layer without individually being tested again, individually cutting, individually encapsulation, reduce cost；
Also, because each light emitting semiconductor layer can form cascaded structure while electrode is formed, so provided by the present invention
LED structure can be in larger operating at voltages.
Claims (15)
1. a kind of high-voltage chip LED structure preparation method, including：
One substrate is provided；
Form light emitting semiconductor layer over the substrate, n type semiconductor layer that the light emitting semiconductor layer includes stacking gradually, have
Active layer and p type semiconductor layer；
Etch the light emitting semiconductor layer and form some notch cuttype through hole, the notch cuttype through hole include groove and with it is described recessed
The isolation channel of groove connection, the groove exposes the surface of the n type semiconductor layer, and the isolation channel exposes the table of the substrate
Face, the cross-sectional width of the groove is more than the cross-sectional width of the isolation channel, and the notch cuttype through hole divides light emitting semiconductor layer
It is cut into the independent light emitting semiconductor layer of some separation；
Insulation film is formed on the p type semiconductor layer and the inwall of notch cuttype through hole, and it is same to etch the insulation film
Step forms barrier layer, corrosion auxiliary layer and side wall overprotection layer, and the barrier layer and corrosion auxiliary layer are respectively positioned on the p-type
On semiconductor layer and the corrosion auxiliary layer annularly surrounds the barrier layer, the side wall overprotection layer covering groove
Side wall and isolation channel side wall and bottom wall and with it is described corrosion auxiliary layer be connected；
Contact is formed on the p type semiconductor layer, n type semiconductor layer, barrier layer, corrosion auxiliary layer and side wall overprotection layer
Film, etching removes the corrosion auxiliary layer and the contact film formation contact layer on side wall overprotection layer；
Etching removes the corrosion auxiliary layer and side wall overprotection layer；
Separation layer is filled in the isolation channel of each independent light emitting semiconductor layer；
First electrode is formed on the contact layer above the barrier layer of each independent light emitting semiconductor layer, in each independence luminous half
Form second electrode on contact layer in the notch cuttype through hole of conductor layer, and by the of the adjacent independent light emitting semiconductor layer in part
Two electrodes and first electrode are electrically connected to form cascaded structure；
Passivation protection layer is formed on the surface of independent all exposures of light emitting semiconductor layer, the passivation protection layer has sudden and violent
First electrode in independent light emitting semiconductor layer headed by revealing in the cascaded structure and in the independent light emitting semiconductor layer of tail
Second electrode fairlead.
2. high-voltage chip LED structure preparation method as claimed in claim 1, it is characterised in that existed by dynamic etching technics
Isolation channel is formed in the light emitting semiconductor layer, the dynamic etching technics includes：
Step one：The substrate is still in the reaction cavity of etching machine bench, is partly led to luminous using inductively coupled plasma
Body layer performs etching technics；
Step 2：Sense coupling technique is terminated, symmetry motion, the symmetry motion occur for the substrate
Refer to that the substrate turns an angle after etching every time；
Repeat the above steps one and step 2 until forming the isolation channel.
3. high-voltage chip LED structure preparation method as claimed in claim 1, it is characterised in that after cascaded structure is formed,
Formed before the passivation protection layer, in addition to：The side wall on surface and notch cuttype through hole to light emitting semiconductor layer carry out etc. from
Subprocessing.
4. high-voltage chip LED structure preparation method as claimed in claim 3, it is characterised in that the plasma is laughing gas
Plasma or oxygen gas plasma.
5. high-voltage chip LED structure preparation method as claimed in claim 1, it is characterised in that the side wall overprotection layer
Also extend to the subregion of the groove bottom wall.
6. high-voltage chip LED structure preparation method as claimed in claim 1, it is characterised in that the p type semiconductor layer,
Photoresist layer is formed after forming contact film on barrier layer, corrosion auxiliary layer and side wall overprotection layer, the photoresist layer is sudden and violent
The dew corrosion auxiliary layer and the contact film on side wall overprotection layer, are removed described by mask etching of the photoresist layer
Corrode auxiliary layer and the contact film formation contact layer on side wall overprotection layer.
7. high-voltage chip LED structure preparation method as claimed in claim 6, it is characterised in that used when forming contact layer
Photoresist layer, formed contact layer after remain as remove corrosion auxiliary layer and side wall overprotection layer mask layer,
The photoresist layer is removed before filling separation layer.
8. high-voltage chip LED structure preparation method as claimed in claim 1, it is characterised in that the separation layer is epoxy radicals
At least one of photoresist, acrylic photoresist, SOG or polyimides.
9. high-voltage chip LED structure preparation method as claimed in claim 1, it is characterised in that the material of the contact layer is
ITO。
10. high-voltage chip LED structure preparation method as claimed in claim 1, it is characterised in that form the independence luminous half
Connection electrode layer, the of the adjacent independent light emitting semiconductor layer in part are formed while the first electrode and second electrode of conductor layer
Two electrodes and first electrode are electrically connected to form cascaded structure by the connection electrode layer.
11. high-voltage chip LED structure preparation method as claimed in claim 1, it is characterised in that the separation layer also covers phase
The part surface of the p type semiconductor layer of adjacent independent light emitting semiconductor layer.
12. a kind of high-voltage chip LED structure, it is characterised in that including：
Substrate；
It is formed at the light emitting semiconductor layer on the substrate, n type semiconductor layer that the light emitting semiconductor layer includes stacking gradually,
Active layer and p type semiconductor layer；
Be formed at some notch cuttype through hole in the light emitting semiconductor layer, the notch cuttype through hole include groove and with it is described
The isolation channel of groove connection, the groove exposes the surface of the n type semiconductor layer, and the isolation channel exposes the table of the substrate
Face, the cross-sectional width of the groove is more than the cross-sectional width of the isolation channel, and the notch cuttype through hole divides light emitting semiconductor layer
It is cut into the independent light emitting semiconductor layer of some separation；
It is formed at the barrier layer on the p type semiconductor layer；
It is formed on the p type semiconductor layer and covering barrier layer and the contact layer that is formed on the n type semiconductor layer；
The p-type for being formed in the isolation channel of each independent light emitting semiconductor layer and covering adjacent independent light emitting semiconductor layer is partly led
The separation layer of body layer surface；
The first electrode on the contact layer above the barrier layer of each independent light emitting semiconductor layer is formed at, each independence is formed at
The second electrode on contact layer in the notch cuttype through hole of light emitting semiconductor layer, the of the adjacent independent light emitting semiconductor layer in part
Two electrodes and first electrode are electrically connected to form cascaded structure；And
The passivation protection layer on the surface of all exposures of independent light emitting semiconductor layer is formed at, the passivation protection layer has
The first electrode in independent light emitting semiconductor layer headed by the exposure cascaded structure and the independent light emitting semiconductor layer for tail
On second electrode fairlead.
13. high-voltage chip LED structure as claimed in claim 12, it is characterised in that the separation layer be epoxy radicals photoresist,
At least one of acrylic photoresist, SOG or polyimides.
14. high-voltage chip LED structure as claimed in claim 12, it is characterised in that the material of the contact layer is ITO.
15. high-voltage chip LED structure as claimed in claim 12, it is characterised in that form the independent light emitting semiconductor layer
First electrode and second electrode while form connection electrode layer, the second electrode of the adjacent independent light emitting semiconductor layer in part
Cascaded structure is electrically connected to form by the connection electrode layer with first electrode.
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| CN105374909B (en) * | 2015-11-02 | 2018-05-29 | 华灿光电(苏州）有限公司 | A kind of manufacturing method of high-voltage LED |
| CN106090652A (en) * | 2016-08-10 | 2016-11-09 | 李铭钰 | High power lighting lamp |
| CN108346723B (en) * | 2017-01-24 | 2020-10-16 | 山东浪潮华光光电子股份有限公司 | GaAs-based AlGaInP single-sided double-electrode high-brightness quaternary light-emitting diode filament and preparation method thereof |
| CN107611079B (en) * | 2017-07-21 | 2020-04-14 | 华灿光电（浙江）有限公司 | Vertical-structure light-emitting diode chip array and manufacturing method thereof |
| CN108899337B (en) | 2018-07-05 | 2021-01-26 | 京东方科技集团股份有限公司 | Micro light-emitting diode substrate, preparation method thereof and display panel |
| CN109560100B (en) * | 2018-11-23 | 2021-04-20 | 江苏新广联科技股份有限公司 | Forward-mounted GaN-based LED micro-display device and manufacturing method thereof |
| CN111697113A (en) * | 2020-06-15 | 2020-09-22 | 南方科技大学 | Preparation method of Micro-LED device and Micro-LED device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4662988A (en) * | 1984-06-28 | 1987-05-05 | Standard Telephones And Cables Public Limited Company | Semiconductor devices and their fabrication |
| CN1819255A (en) * | 2005-02-03 | 2006-08-16 | 范朝阳 | Micro-led based high voltage ac/dc indicator lamp |
| CN102132429A (en) * | 2008-09-11 | 2011-07-20 | 普瑞光电股份有限公司 | Series connected segmented led |
| CN102214769A (en) * | 2010-04-12 | 2011-10-12 | 富士迈半导体精密工业（上海）有限公司 | Solid light-emitting element and light source module with same |
| CN102983147A (en) * | 2012-09-24 | 2013-03-20 | 杭州士兰明芯科技有限公司 | Light emitting diode chip and production method thereof |
| CN202957243U (en) * | 2012-09-24 | 2013-05-29 | 杭州士兰明芯科技有限公司 | Light emitting diode chip |
| CN204243081U (en) * | 2014-11-28 | 2015-04-01 | 杭州士兰明芯科技有限公司 | A kind of high-voltage chip LED structure |
-
2014
- 2014-11-28 CN CN201410710007.2A patent/CN104409605B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4662988A (en) * | 1984-06-28 | 1987-05-05 | Standard Telephones And Cables Public Limited Company | Semiconductor devices and their fabrication |
| CN1819255A (en) * | 2005-02-03 | 2006-08-16 | 范朝阳 | Micro-led based high voltage ac/dc indicator lamp |
| CN102132429A (en) * | 2008-09-11 | 2011-07-20 | 普瑞光电股份有限公司 | Series connected segmented led |
| CN102214769A (en) * | 2010-04-12 | 2011-10-12 | 富士迈半导体精密工业（上海）有限公司 | Solid light-emitting element and light source module with same |
| CN102983147A (en) * | 2012-09-24 | 2013-03-20 | 杭州士兰明芯科技有限公司 | Light emitting diode chip and production method thereof |
| CN202957243U (en) * | 2012-09-24 | 2013-05-29 | 杭州士兰明芯科技有限公司 | Light emitting diode chip |
| CN204243081U (en) * | 2014-11-28 | 2015-04-01 | 杭州士兰明芯科技有限公司 | A kind of high-voltage chip LED structure |
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