CN104395992A - 晶体管以及晶体管的制造方法 - Google Patents

晶体管以及晶体管的制造方法 Download PDF

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CN104395992A
CN104395992A CN201380034703.XA CN201380034703A CN104395992A CN 104395992 A CN104395992 A CN 104395992A CN 201380034703 A CN201380034703 A CN 201380034703A CN 104395992 A CN104395992 A CN 104395992A
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insulating film
gate insulating
reactive material
semiconductor layer
deposition method
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荒木圣人
桥本正太郎
高尾将和
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Murata Manufacturing Co Ltd
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Abstract

本发明的目的在于提供一种抑制在漏源电极间流动的电流的降低，栅极绝缘膜的绝缘破坏电压高的晶体管。晶体管(100)的特征在于，具备：半导体层(2)、形成在半导体层(2)上的栅极绝缘膜(7)、形成在栅极绝缘膜(7)上的栅电极(8)、在半导体层(2)上夹着栅电极(8)形成的源电极(5)以及漏电极(6)，在栅极绝缘膜(7)中包含的杂质的浓度，从栅极绝缘膜(7)的半导体层2侧的表面到栅极绝缘膜(7)的栅电极(8)侧的表面而减少。

Description

晶体管以及晶体管的制造方法
技术领域
本发明涉及一种具备栅极绝缘膜的晶体管以及晶体管的制造方法。
背景技术
以往，例如专利文献1(日本特开2010－98141号)所公开的晶体管被用作电子电路中的信号放大器。
图4表示以往的晶体管的一个例子。此外，图4为以往的晶体管200的剖视图。
图4所示的晶体管200在基板101上具备由GaN层102a以及AlGaN层102b构成的半导体层102。
在半导体层102上，形成有源电极105以及漏电极106。
在源电极105以及漏电极106上，形成有连接用电极112。
在半导体层102上的一部分，形成有栅极绝缘膜107。
在栅极绝缘膜107上的一部分，形成有栅电极108。
在栅极绝缘膜107上的一部分，形成有保护膜109。
在栅电极108、保护膜109、连接用电极112上，形成有由聚酰亚胺树脂等构成的表面保护树脂115。
在上述的以往的晶体管200中，由氧化铝等构成的栅极绝缘膜107通常以阶梯覆盖性、膜厚均匀性、膜厚控制性优异的原子层沉积(ALD：Atomic Layer Deposition)法形成。
以下，对利用原子沉积法的栅极绝缘膜107的形成方法的一个例子进行说明。
首先，通过将作为第1反应物质的TMA(三甲基铝，Tri MethylAluminum，化学式：Al(CH3)3)供给到半导体层102上，使TMA吸附在半导体层102的表面。接下来，清除未吸附尽的TMA。接下来，通过将作为第2反应物质的O3供给到半导体层102上，使其与吸附于半导体层102的TMA反应。接下来，清除未反应尽的O3，从而形成1个原子层的氧化铝。通过重复这一系列的周期，形成由多个原子层的氧化铝构成的所期望的栅极绝缘膜107。
然而，由于O3反应性不高，所以O3未与TMA充分反应，存在H原子和C原子等杂质在氧化铝中有所残留的情况。其结果，氧化铝膜的密度变小，栅极绝缘膜107的绝缘破坏电压变小。
因此，为了提高栅极绝缘膜107的绝缘破坏电压，有一种作为上述的原子沉积法中的第2反应物质，代替O3，而供给O2等离子体的方法。
或者，作为用于提高栅极绝缘膜107的绝缘破坏电压的方法，如专利文献2(日本特开2009－152640号)所示，有一种作为上述的原子沉积法的第2反应物质，在供给O3后，适当地照射O2等离子体的方法。
与O3相比O2等离子体与TMA的反应性高。因此，在氧化铝膜中H原子和C原子等杂质变得不易剩余，氧化铝膜的密度变大。
图5表示以上述的以往的方法形成的栅极绝缘膜的绝缘破坏电压(MV/cm)的一个例子。图5中的(A)示有作为第2反应物质使用O3形成的栅极绝缘膜的绝缘破坏电压。另外，图5中的(B)示有作为第2反应物质使用O2等离子体形成的栅极绝缘膜的绝缘破坏电压。栅极绝缘膜的膜厚均为30nm。从图5可知，通过作为原子沉积法中的第2反应物质使用O2等离子体，与使用O3的情况相比，栅极绝缘膜的绝缘破坏电压提高。
专利文献1:日本特开2010－98141号
专利文献2:日本特开2009－152640号
然而，在使用上述O2等离子体来形成栅极绝缘膜107时，由于O2等离子体的反应性高，所以半导体层102容易受到损伤。因此，存在受损伤的半导体层102中的电子浓度减少，晶体管200的漏源电极间流动的电流减少的问题。
发明内容
本发明的目的在于提供一种抑制在漏源电极间流动的电流的降低，并且栅极绝缘膜的绝缘破坏电压较高的晶体管及其制造方法。
为实现上述的目的，本发明的晶体管的特征在于，具备：半导体层、形成在半导体层上的栅极绝缘膜、形成在栅极绝缘膜上的栅电极、以及在半导体层上夹着栅电极而形成的源电极以及漏电极，在栅极绝缘膜中含有的杂质的浓度从栅极绝缘膜的半导体层侧的表面到栅极绝缘膜的栅电极侧的表面而减少。
另外，本发明的晶体管的制造方法的特征在于，具备：准备半导体层的工序；通过使用第1反应物质以及第2反应物质的第1原子层沉积法，在半导体层上形成第1栅极绝缘膜的工序；通过使用第1反应物质以及第2反应物质的第2原子层沉积法，在第1栅极绝缘膜上形成第2栅极绝缘膜的工序；在第2栅极绝缘膜上形成栅电极的工序；以及在半导体层上夹着栅电极形成源电极以及漏电极的工序，在第2原子层沉积法中使用的第2反应物质，与在第1原子层沉积法中使用的第2反应物质相比反应性高，第2栅极绝缘膜与第1栅极绝缘膜相比杂质的浓度小。
根据本发明，能够得到一种抑制在漏源电极间流动的电流的降低，并且栅极绝缘膜的绝缘破坏电压高的晶体管。
附图说明
图1(A)～(E)是表示本发明的实施方式的在晶体管100的制造方法中应用的各工序的剖视图。
图2(F)～(I)是图1的接续，是表示本发明的实施方式的在晶体管100的制造方法中应用的各工序的剖视图。此外，图2(I)也是完成的晶体管100的剖视图。
图3是以本发明的方法形成的栅极绝缘膜与通过以往的方法形成的栅极绝缘膜的绝缘破坏电压相比较的图表。
图4是以往的晶体管200的剖视图。
图5是表示通过以往的方法形成的栅极绝缘膜的绝缘破坏电压图。
具体实施方式
以下结合附图，对用于实施本发明方式的一个例子进行说明。
在图2(I)示出本发明的实施方式的晶体管100的剖视图。
晶体管100在由氮化镓、硅，碳化硅素等构成的基板1上具备由氮化镓层2a以及氮化铝镓层2b构成的半导体层2。
在半导体层2上，形成有由含有钛和铝等的材料构成的源电极5以及漏电极6。
在源电极5以及漏电极6上，形成有由含有金等的材料构成的连接用电极12。
在半导体层2上的一部分，形成有由氧化铝等构成的第1栅极绝缘膜7a。第1栅极绝缘膜7a作为杂质含有氢原子以及碳原子中的至少一方。
在第1栅极绝缘膜7a上，形成有由氧化铝等构成的第2栅极绝缘膜7b。第2栅极绝缘膜7b与第1栅极绝缘膜7a相同，作为杂质含有氢原子以及碳原子中的至少一方，其浓度比第1栅极绝缘膜7a小。由于在栅极绝缘膜7中具备该杂质浓度较小的栅极绝缘膜7b，所以在晶体管100中栅极绝缘膜7的绝缘破坏电压升高。
这里，第1栅极绝缘膜7a通过作为第1反应物质使用了TMA、作为第2反应物质使用了臭氧的原子沉积法而形成。由于在第1栅极绝缘膜7a中，使用原子沉积法中反应性低的臭氧，所以几乎没有由臭氧的照射引起的半导体层2的损伤。
另一方面，第2栅极绝缘膜7b与第1栅极绝缘膜7a不同，通过作为第1反应物质使用了TMA、作为第2反应物质使用了氧等离子体的原子沉积法而形成。第2栅极绝缘膜7b由于形成在第1栅极绝缘膜7a上，所以即使使用反应性较高的氧等离子体，也能够减少由氧等离子体的照射引起的对半导体层2的损伤。即，根据本发明，能够在第1栅极绝缘膜7a以及第2栅极绝缘膜7b形成之时，减少对半导体层2的损伤，抑制半导体层2中的电子浓度的减少。因此，能够抑制伴随着电子浓度的减少的在漏源电极间流动的电流的降低。
本发明的实施方式的晶体管100由于具备上述的栅极绝缘膜7，所以能够抑制在漏源电极间流动的电流降低，并且提高栅极绝缘膜7的绝缘破坏电压。
在第2栅极绝缘膜7b上的一部分，形成有由含有金和镍等的材料构成的栅电极8。
在第2栅极绝缘膜7b上的一部分，形成有由氮化硅素等构成的保护膜9。
在保护膜9以及连接用电极12上，形成有聚酰亚胺树脂等表面保护树脂15。
接下来，对由上述结构构成的本发明的实施方式的晶体管100的制造方法的一个例子进行说明。
图1(A)～图2(I)分别为表示本实施方式的晶体管100的制造方法中应用的各工序剖视图。此外，图1(C)～图2(I)放大表示图1(B)中A区域。
首先，如图1(A)所示，在由氮化镓、硅、碳化硅等构成的基板1上，利用MOCVD(Metal Organic Chemical Vapor Deposition：金属有机化学气相沉积)法形成氮化镓层2a。接着，在氮化镓层2a上，利用MOCVD法形成氮化铝镓层2b，完成半导体层2。
接下来，如图1(B)所示，通过干法刻蚀等，在半导体层2的一部分形成必要的深度的槽3，使半导体层2在每一个A的区域电分离。
若需要，利用光刻法和干法刻蚀，除去半导体层2的一部分，形成用于使晶体管100具有常断化等功能的栅极凹槽(未图示)。
接下来，如图1(C)所示，在半导体层2上利用光刻法与真空蒸镀法，形成由含有钛、铝等的材料构成的源电极5以及漏电极6。之后，若需要，利用热处理使源电极5以及漏电极6分别与半导体层2的接触面欧姆接触。
接下来，如图1(D)所示，利用由以下所示的步骤1～4所形成的第1原子沉积法，在半导体层2、源电极5以及漏电极6上，形成由氧化铝构成的第1栅极绝缘膜7a。
首先，在步骤1中，在收纳有基板1的处理室内，供给作为第1反应物质的TMA。此时，1个原子层的量的TMA吸附在半导体层2以及源电极5以及漏电极6上。
在步骤2中，利用干式真空泵等将未吸附尽的TMA从处理室内清除。另外，向处理室内供给一定时间的氮气等惰性气体。
在步骤3中，将臭氧导入处理室内。此时，在步骤1中吸附的TMA与臭氧发生反应，形成1个原子层的氧化铝。
在步骤4中，利用干式真空泵等将臭氧从处理室内清除。另外，向处理室内供给一定时间的氮气等惰性气体。
通过按照规定的次数反复进行步骤1至4，来形成由规定的膜厚的氧化铝构成的第1栅极绝缘膜7a。
接下来，如图1(E)所示，利用由以下所示的步骤1至4所形成的第2原子沉积法，在第1栅极绝缘膜7a上形成由氧化铝构成的第2栅极绝缘膜7b。
首先，在步骤1中，与上述的第1原子沉积法相同，向处理室内供给作为第1反应物质的TMA。此时，在第1栅极绝缘膜7a上沉积TMA。
在步骤2中，利用干式真空泵等从处理室内清除未吸附尽的TMA。另外，向处理室内供给一定时间的氮气等惰性气体。
在步骤3中，向处理室内导入氧气，通过对设置于处理室内的电极间施加高频电力，来等离子体激发氧气。被等离子体激发的氧气(氧等离子体)，与沉积在第1栅极绝缘膜7a上的TMA反应。
作为步骤4，利用干式真空泵等从处理室清除氧气，停止向电极间的高频电力的施加。另外，使氮气等惰性气体在处理室内流动一定时间。
通过按照规定的次数反复进行步骤1至4，在第1栅极绝缘膜7a上形成规定的膜厚的第2栅极绝缘膜7b。
由于氧等离子体与臭氧相比反应性高，所以由氧化铝所构成的第2栅极绝缘膜7b的氢原子和碳原子等杂质浓度，与第1栅极绝缘膜7a相比变小。换言之，晶体管100的第1栅极绝缘膜7a以及第2栅极绝缘膜7b所含的杂质的浓度，从第1栅极绝缘膜7a的半导体层2侧的表面到第2栅极绝缘膜7b的栅电极8侧的上表面减少。其结果，如上所述，由于能够在栅极绝缘膜7中形成杂质浓度小的第2栅极绝缘膜7b，所以晶体管100中栅极绝缘膜7的绝缘破坏电压升高。
此外，在本实施方式的制造方法中，由于在形成第1栅极绝缘膜7a之后使用氧等离子体形成第2栅极绝缘膜7b，所以氧等离子体被第1栅极绝缘膜7a所阻挡而难以到达半导体层2。因此，半导体层2不容易被氧等离子体的照射损伤。
接下来，如图2(F)所示，利用光刻法与真空蒸镀法，在第2栅极绝缘膜7b上，形成由含有金和镍等的材料构成的栅电极8。
接下来，如图2(G)所示，通过CVD法，在源电极5以及漏电极6间形成由氮化硅素等构成的保护膜9。接着，通过利用光刻法与干法刻蚀除去栅电极8上的保护膜9、源电极5以及漏电极6上的第1栅极绝缘膜7a以及第2栅极绝缘膜7b以及保护膜9，从而形成开口10，使栅电极8、源电极5以及漏电极6的一部分露出。
接下来，如图2(H)所示，为了使源电极5以及漏电极6的电阻减少，利用光刻法与真空蒸镀法形成由含有金和铝等的材料构成的连接用电极12、12。
最后，如图2(I)所示，在保护膜9以及连接用电极12上，使连接用电极12、12的一部分露出地形成聚酰亚胺树脂等表面保护树脂15，完成晶体管100。
如以上所述，在本发明中，利用第1栅极绝缘膜7a以及第2栅极绝缘膜7b形成栅极绝缘膜7，从而能够抑制对半导体层2的损伤，并且在栅极绝缘膜7中形成杂质浓度小的层。其结果，能够抑制晶体管100的漏源电极间流动电流的降低，并且使栅极绝缘膜7的绝缘破坏电压提高。
图3是利用本发明的方法形成的栅极绝缘膜的绝缘破坏电压与利用以往的方法形成的栅极绝缘膜的绝缘破坏电压的比较图。图3中的(A)表示通过作为第1反应物质使用了TMA、作为第2反应物质使用了臭氧的以往的原子沉积法而形成的栅极绝缘膜的绝缘破坏电压。图3中的(B)表示通过作为第1反应物质使用了TMA、作为第2反应物质使用了氧等离子体的以往的原子沉积法而形成的栅极绝缘膜的耐压。图3中的(C)表示，通过本实施方式中所示的方法形成的由第1栅极绝缘膜以及第2栅极绝缘膜所构成的栅极绝缘膜的绝缘破坏电压。
图3中的(A)～(C)中的栅极绝缘膜的膜厚皆为相同的30nm。图3中的(C)中的第1栅极绝缘膜以及第2栅极绝缘膜的膜厚皆为15nm。
由图3可知，图3中的(C)的栅极绝缘膜的绝缘破坏电压与图3中的(A)的栅极绝缘膜的绝缘破坏电压相比要高，与图3中的(B)的栅极绝缘膜的绝缘破坏电压相比也不逊色。
此外，本发明的晶体管及其制造方法并不限于本实施方式，能够在其主旨的范围内进行各种变更。
例如，在本实施方式中，作为半导体层2使用氮化镓层2a和氮化铝镓层2b，但也可以使用砷化镓层和砷化铝镓层等。另外，在第1原子层沉积法中，作为第2反应物质使用臭氧，但也可以使用水蒸气等。另外，在第2原子沉积法中，作为第2反应物质使用氧等离子体，但也可以使用等离子体激发的二氧化碳、水蒸气。另外，作为第1栅极绝缘膜7a、第2栅极绝缘膜7b的材料，使用氧化铝，但也可以使用氧化硅、氧化铪等氧化物和氮化硅、氮化铝等氮化物等绝缘物材料。另外，在氮化物材料的形成中，第1原子沉积法中的第2反应物质使用氮和氨等，但也可以第2原子层沉积法中的第2反应物质使用等离子体激发的氮和氨等。
附图标记的说明：1…基板；2…半导体层；2a…氮化镓层；2b…氮化铝镓层；3…槽；5…源电极；6…漏电极；7…栅极绝缘膜；7a…第1栅极绝缘膜；7b…第2栅极绝缘膜；8…栅电极；9…保护膜；10…开口；12…连接用电极；15…表面保护树脂；100…晶体管。

Claims (10)

1.一种晶体管，其特征在于，具备：
半导体层；
栅极绝缘膜，其形成在所述半导体层上；
栅电极，其形成在所述栅极绝缘膜上；以及
源电极以及漏电极，它们在所述半导体层上夹着所述栅电极而形成，
在所述栅极绝缘膜中包含的杂质的浓度从所述栅极绝缘膜的所述半导体层侧的表面到所述栅极绝缘膜的所述栅电极侧的表面而减少。
2.根据权利要求1所述的晶体管，其特征在于，
所述杂质为氢原子以及碳原子中的至少一方。
3.根据权利要求1或2所述的晶体管，其特征在于，
所述栅极绝缘膜具有：
第1栅极绝缘膜，通过使用了第1反应物质以及第2反应物质的第1原子层沉积法形成所述第1栅极绝缘膜；和
第2栅极绝缘膜，通过使用了第1反应物质以及第2反应物质的第2原子层沉积法，在所述第1栅极绝缘膜上形成所述第2栅极绝缘膜，
在所述第2原子层沉积法中使用的所述第2反应物质与在所述第1原子层沉积法中使用的所述第2反应物质相比反应性高，
所述第2栅极绝缘膜与所述第1栅极绝缘膜相比杂质的浓度小。
4.根据权利要求1至3中任一项所述的晶体管，其特征在于，
所述栅极绝缘膜由氧化物材料构成。
5.根据权利要求4所述的晶体管，其特征在于，
所述氧化物材料为氧化铝。
6.根据权利要求3至5中任一项所述的晶体管，其特征在于，
所述第1反应物质为三甲基铝，
在所述第1原子层沉积法中使用的第2反应物质为臭氧或者水蒸气的任一方，
在所述第2原子层沉积法中使用的第2反应物质为氧等离子体。
7.根据权利要求1至6中任一项所述的晶体管，其特征在于，
所述半导体层包括与所述栅极绝缘膜接触的氮化铝镓层、以及与该氮化铝镓层接触的氮化镓层。
8.一种晶体管的制造方法，其特征在于，具备：
准备半导体层的工序；
通过使用第1反应物质以及第2反应物质的第1原子层沉积法，在所述半导体层上形成第1栅极绝缘膜的工序；
通过使用第1反应物质以及第2反应物质的第2原子层沉积法，在所述第1栅极绝缘膜上形成第2栅极绝缘膜的工序；
在所述第2栅极绝缘膜上形成栅电极的工序；以及
在所述半导体层上夹着所述栅电极形成源电极以及漏电极的工序，
在所述第2原子层沉积法中使用的所述第2反应物质与在所述第1原子层沉积法中使用的所述第2反应物质相比反应性高，
所述第2栅极绝缘膜与所述第1栅极绝缘膜相比杂质的浓度小。
9.根据权利要求8所述的晶体管的制造方法，其特征在于，
所述第1反应物质为三甲基铝，
在所述第1原子层沉积法中使用的第2反应物质为臭氧或者水蒸气的任一方，
在所述第2原子层沉积法中使用的第2反应物质为氧等离子体。
10.根据权利要求8或9所述的晶体管的制造方法，其特征在于，
所述杂质为氢原子以及碳原子中的至少一方，
所述第1栅极绝缘膜以及所述第2栅极绝缘膜由氧化铝构成。
CN201380034703.XA 2012-07-13 2013-06-25 晶体管以及晶体管的制造方法 Pending CN104395992A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113454799A (zh) * 2019-02-21 2021-09-28 株式会社村田制作所 石墨烯晶体管及其制造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10658469B2 (en) * 2014-05-01 2020-05-19 Renesas Electronics Corporation Semiconductor device including a plurality of nitride semiconductor layers
JP6528366B2 (ja) * 2014-07-08 2019-06-12 豊田合成株式会社 縦型トレンチｍｏｓｆｅｔの製造方法
JP2016171117A (ja) * 2015-03-11 2016-09-23 株式会社豊田中央研究所 半導体装置
JP2019071497A (ja) * 2019-02-13 2019-05-09 豊田合成株式会社 半導体装置およびその製造方法
FR3112422B1 (fr) * 2020-07-09 2022-08-12 Commissariat Energie Atomique Procédé de réalisation d’une couche diélectrique sur une structure en matériaux III-V

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040191997A1 (en) * 2003-03-24 2004-09-30 Semiconductor Leading Edge Technologies, Inc. Method for manufacturing semiconductor device
US20070048953A1 (en) * 2005-08-30 2007-03-01 Micron Technology, Inc. Graded dielectric layers
CN101002332A (zh) * 2004-06-24 2007-07-18 日本电气株式会社 半导体器件
US20090047798A1 (en) * 2007-08-16 2009-02-19 Tokyo Electron Limited Method of forming high dielectric constant films using a plurality of oxidation sources
CN101620991A (zh) * 2008-07-02 2010-01-06 中芯国际集成电路制造(上海)有限公司 Tft快闪存储单元的原子层沉积外延硅生长
CN101937930A (zh) * 2010-08-31 2011-01-05 清华大学 一种高性能场效应晶体管及其形成方法
US20120001194A1 (en) * 2010-06-30 2012-01-05 Sumitomo Electric Industries, Ltd. Semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101527263B (zh) * 2005-02-17 2013-03-20 株式会社日立国际电气 半导体器件的制造方法
JP2010267925A (ja) * 2009-05-18 2010-11-25 Hitachi Kokusai Electric Inc 半導体装置の製造方法及び基板処理装置
JP2011171468A (ja) * 2010-02-18 2011-09-01 Mitsui Eng & Shipbuild Co Ltd 薄膜形成装置および薄膜形成方法
JP2012134311A (ja) * 2010-12-21 2012-07-12 Hitachi Kokusai Electric Inc 半導体デバイスの製造方法及び基板処理装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040191997A1 (en) * 2003-03-24 2004-09-30 Semiconductor Leading Edge Technologies, Inc. Method for manufacturing semiconductor device
CN101002332A (zh) * 2004-06-24 2007-07-18 日本电气株式会社 半导体器件
US20070048953A1 (en) * 2005-08-30 2007-03-01 Micron Technology, Inc. Graded dielectric layers
US20090047798A1 (en) * 2007-08-16 2009-02-19 Tokyo Electron Limited Method of forming high dielectric constant films using a plurality of oxidation sources
CN101620991A (zh) * 2008-07-02 2010-01-06 中芯国际集成电路制造(上海)有限公司 Tft快闪存储单元的原子层沉积外延硅生长
US20120001194A1 (en) * 2010-06-30 2012-01-05 Sumitomo Electric Industries, Ltd. Semiconductor device
CN101937930A (zh) * 2010-08-31 2011-01-05 清华大学 一种高性能场效应晶体管及其形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113454799A (zh) * 2019-02-21 2021-09-28 株式会社村田制作所 石墨烯晶体管及其制造方法

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