CN104362176A - Self-aligned double-gate small-gap semiconductor transistor with high on-off ratio and manufacturing method thereof - Google Patents
Self-aligned double-gate small-gap semiconductor transistor with high on-off ratio and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a self-aligned double-gate small-gap semiconductor transistor with high on-off ratio and a manufacturing method thereof. According to the transistor, drain bias voltage is fed back to an auxiliary gate, a clamped square barrier is formed around a drain, and reverse tunneling of drain minority carriers can be well inhibited during running under large bias voltage; thus, the on-off ratio can be increased at the premise of keeping high performance of a non-doped small-gap semiconductor top gate device, and bipolarity is evidently inhibited. Meanwhile, the use of a two-step self-aligned process leads to reduction in device size, and the transistor is applicable to large-scale integrations.
Description
Technical field
The invention belongs to field-effect transistor logical device field in spatia zonularis semiconductor CMOS (the ComplementaryMetal Oxide Semiconductor) integrated circuit that is host semiconductor material and display driver circuit, be specifically related to a kind of autoregistration double grid non-impurity-doped spatia zonularis semiconductor transistor construction with high on-off ratio and preparation method thereof.
Background technology
The mobility that spatia zonularis semi-conducting material has superelevation makes it in high speed integrated circuit field, have very large potentiality, particularly the Binary compound semiconductor such as indium antimonide, indium arsenide is widely used in high-speed radio-frequency circuit, and carbon nano-tube, self of the novel nano-materials such as graphene nanobelt is flexible and the feature of high light transmittance makes it in flexible electronic and display driver circuit, have the advantage of uniqueness.Because the device of spatia zonularis semi-conducting material has less on-off ratio usually, and grid spatia zonularis semiconductor device is pushed up for the non-impurity-doped (No-doping) of routine, when strengthening bias operation outside, because drain terminal exists a lower and very thin Schottky barrier, the few sub-reverse tunnel electric current sent from drain terminal is increased greatly, so the off-state current under the large bias voltage of device is increased, and bipolarity clearly.These impacts cause the quiescent dissipation of spatia zonularis semiconductor integrated circuit comparatively large, and easy occurrence logic mistake.How to improve the on-off ratio of spatia zonularis semiconductor transistor, and how effectively to suppress spatia zonularis semiconductor device bipolarity to become the bottleneck problem of spatia zonularis semiconductor integrated circuit and display driver circuit development.
Existing non-impurity-doped spatia zonularis semiconductor transistor is as shown in Fig. 1 (a), comprise: dielectric substrate (101), spatia zonularis semiconductor body or film (102), source electrode (107), drain electrode (108), gate dielectric layer (103), top gate electrode (104), top layer (105) and side wall (106), wherein pushing up gate electrode (104) is positioned on gate dielectric layer (103), top layer (105) is positioned on top gate electrode (104), side wall (106) is positioned at top gate electrode (104), the both sides of top layer (105), form operator guards.Its operation principle be by source-drain electrode to the unipolarity of spatia zonularis semi-conducting material without barrier contact, the non-impurity-doped MOS realizing spatia zonularis semiconductive thin film works, but this device is when OFF state, and the few sub-tunnelling of drain terminal is very serious.For general commercial display driver circuit, require that the on-off ratio of thin-film transistor is greater than 1e6, so keeping high performance while, how to improve spatia zonularis semiconductive thin film devices switch ratio and suppress bipolarity to become the key that non-impurity-doped spatia zonularis semiconductor device integrated circuit realizes commercialization.
Summary of the invention
The object of the present invention is to provide a kind of autoregistration double grid non-impurity-doped spatia zonularis semiconductor transistor with high on-off ratio and preparation method thereof.This structure utilizes and drain terminal bias voltage is fed back to auxiliary grid, thus near drain terminal, form one by the square potential barrier of clamper, drain terminal few sub-reverse tunnel well can be suppressed when working under making large bias voltage, therefore on-off ratio can be increased maintenance spatia zonularis semiconductor top gate device is high performance, and significantly suppress bipolarity simultaneously.Meanwhile, the present invention can, by device dimensions shrink, be applicable to ultra-large integrated in conjunction with two step self-registered technologies.
Technical scheme of the present invention is as follows:
There is an autoregistration double grid spatia zonularis semiconductor transistor for high on-off ratio, comprising: dielectric substrate, spatia zonularis semiconductor layer, gate dielectric layer, main grid (control gate) structure, source electrode, leakage-auxiliary grid combination electrode; Described spatia zonularis semiconductor layer is positioned on dielectric substrate; Described gate dielectric layer is positioned at spatia zonularis semiconductor layer; Described main grid structure is on gate dielectric layer and between source electrode and leakage-auxiliary grid combination electrode, described main grid structure comprises primary gate electrode, top layer and side wall, top layer is positioned at directly over primary gate electrode, side wall be positioned at primary gate electrode and top layer both sides (side wall achieve primary gate electrode respectively with source electrode and the isolation with leakage-auxiliary grid combination electrode, side wall is the key realizing self-registered technology); Described source electrode and leakage-auxiliary grid combination electrode lay respectively on semi-conductor type spatia zonularis semiconductive thin film two ends, between source electrode and spatia zonularis semiconductor layer and leak-between auxiliary grid combination electrode and spatia zonularis semiconductor layer, there is infiltration boundary layer respectively, it is outer and be positioned on gate dielectric layer that auxiliary gate electrode in described leakage-auxiliary grid combination electrode is positioned at side wall, and described auxiliary gate electrode is all connected physically with in electricity with drain electrode.Auxiliary gate electrode and drain electrode remain equipotential, and drain terminal is fixed a rectangular barrier, thus reverse tunnel when suppressing OFF state, improve devices switch ratio.
The material of described dielectric substrate comprises silica, quartz, glass, the hard insulations such as aluminium oxide, and PET (PETG), PEN (PEN), the high-temperature flexible insulating material such as polyimides.
The typical bandgap of described spatia zonularis semiconductor layer is less than 1eV, comprises semiconductor type carbon nano-tube (CarbonNanotubes) film, graphene nanobelt (GrapheneRibbon), molybdenum bisuphide (MoS
2), tungsten disulfide (WS2), the novel nano-materials such as black phosphorus (P); And germanium (Ge), indium arsenide (InAs), indium antimonide (InSb), vulcanized lead (PbS), lead selenide (PbSe), the conventional semiconductor material such as lead telluride (PbTe), and the composite bed of appointing both combinations each other.
The material of described gate dielectric layer can be silica, hafnium oxide, zirconia, yittrium oxide, tantalum oxide, lanthana or lanthana aluminium, the hard materials such as silicon nitride, or epoxy resin, the organic polymer insulating barriers such as PMMA (polymethyl methacrylate).The thickness range of described gate dielectric layer is 2 ~ 100nm.
The material of described primary gate electrode is the various metal such as Pd, Pt, Ti, Cu, Au, Al, W, conductive metal suicide, the electric conducting materials such as doped polycrystalline silicon, and the laminated construction of above-mentioned electric conducting material.The main grid of PMOS should be made to be in hole enhancement mode in conjunction with concrete technology, make the main grid of NMOS be in electronics enhancement mode.The thickness range of described primary gate electrode is 20 ~ 100nm.
The material of described source electrode and leakage-auxiliary grid combination electrode can be the various metal such as Pd, Pt, Ti, Cu, Au, Al, W respectively, conductive metal suicide, the electric conducting materials such as doped polycrystalline silicon, and the laminated construction of above-mentioned electric conducting material.In principle, for PMOS, should select high-work-function metal (work function is greater than 5eV) that source and drain is contacted to hole without potential barrier, make auxiliary grid be in hole depletion type mode of operation, typical metal is platinum, palladium simultaneously; For NMOS, should select low workfunction metal (work function is less than 4.3eV) that source and drain is contacted to electronics without potential barrier, make auxiliary grid be in depleted of electrons type mode of operation, typical metal is scandium, yttrium, aluminium simultaneously.The thickness range of described source electrode and leakage-auxiliary grid combination electrode is 20 ~ 100nm.
The preparation method of above-mentioned double grid spatia zonularis semiconductor transistor, comprises the steps:
1) transfer or growth spatia zonularis semiconductor layer (can be block or two-dimensional film) on an insulating substrate;
2) by photoetching and plasma etch process, the spatia zonularis semiconductor layer of full wafer is patterned into channel region isolated from one another;
3) on spatia zonularis semiconductor layer, gate dielectric layer is deposited;
4) on gate dielectric layer, deposit primary gate electrode metal level and insulating oxide silicon layer successively, and form main grid (control gate) electrode of device with photoetching and etching technics;
5) side wall technique is adopted to form side wall protection structure in primary gate electrode both sides;
6) using main grid structure as half autoregistration mask, the gate medium figure of device is formed in conjunction with photoetching and etching technics;
7) using main grid structure as autoregistration mask, the boundary layer of sedimentary origin electrode, leakage-auxiliary grid combination electrode and electrode metal layer, form source electrode, the leakage-auxiliary grid combination electrode of device by technique one step of photoetching and etching.
In above-mentioned preparation method, described step 1) in the method for transfer spatia zonularis semiconductor layer be selected from one of following method: dry method shifts, coating, nanometer ink jet printing, spin coating.
In above-mentioned preparation method, described step 3) in the method for deposition gate insulation dielectric layer be selected from one of following method: ald, sputter and anneals, sputtering also thermal oxidation, sol-gel process, spin coating hot setting.
In above-mentioned preparation method, described step 4) in deposition primary gate electrode metal level and step 7) in sedimentary origin electrode, leakage-auxiliary grid combination electrode the method for electrode metal layer be selected from one of following method: the hot evaporation of electron beam, sputtering.
Advantage of the present invention and beneficial effect:
(1) existence of auxiliary gate electrode can suppress the few sub-reverse tunnel of drain terminal greatly, reduces off-state leakage current, improves on-off ratio, and inhibit bipolarity significantly, can keep the high-performance of non-impurity-doped spatia zonularis semiconductor top gate device simultaneously preferably.As shown in Figure 3 b, with the embodiment of single tube material for spatia zonularis semiconductor layer, in same carbon nano-tube, preparation has the conventional structure of same channel length and the PMOS device of this modified node method, when drain bias is-0.8V, the pass state value measuring the electric current (403) of modified node method obtained decreases two magnitudes than conventional structure (404), and completely inhibit bipolarity.(2) in conjunction with two step self-registered technologies, make the dimension reduction of device to silica-based 22nm technology node, be applicable to ultra-large integrated.(3) the present invention does not increase process complexity while improvement performance, well can keep the process costs that non-impurity-doped spatia zonularis semiconductor integrated circuit is lower.
Accompanying drawing explanation
Fig. 1 (a) is the profile of existing non-impurity-doped spatia zonularis semiconductor top grid autoregistration field-effect transistor; Fig. 1 (b) is the principle graphical diagram of existing non-impurity-doped spatia zonularis semiconductor top grid autoregistration field-effect transistor on electrical behavior.
Fig. 2 (a) is the profile with the autoregistration double grid non-impurity-doped spatia zonularis semiconductor transistor of high on-off ratio of the present invention; Fig. 2 (b) is the principle graphical diagram of autoregistration double grid non-impurity-doped spatia zonularis semiconductor transistor of the present invention on electrical behavior.
Fig. 3 (a) be of the present invention there is high on-off ratio autoregistration double grid non-impurity-doped spatia zonularis semiconductor transistor (solid line, 401) and existing top grid autoregistration field-effect transistor (dotted line, 402) at the energy band diagram of OFF state; Fig. 3 (b) is the autoregistration double grid non-impurity-doped spatia zonularis semiconductor transistor (solid line with high on-off ratio of the present invention, 403) and existing top grid autoregistration field-effect transistor (dotted line, 404) actual measurement transfer characteristic curve, adopt single semiconductor carbon pipe as the embodiment of spatia zonularis semiconductor, two device channel length are 500nm, wherein the main grid length of structure of the present invention is 200nm with auxiliary grid are long, and drain terminal bias voltage is-0.8V.
Fig. 4 to Fig. 9 is the process section preparing the transistor shown in Fig. 2, wherein:
Fig. 4 display is transfer or growth spatia zonularis semiconductive thin film on an insulating substrate;
The spatia zonularis semiconductive thin film of full wafer is etched into channel region isolated from one another by Fig. 5 display;
Fig. 6 is presented on spatia zonularis semiconductive thin film and deposits gate dielectric layer;
Fig. 7 shows deposition and graphical grid metal electrode and top layer;
Fig. 8 shows the side wall of deposition and graphical main grid;
Fig. 9 shows the graphical gate dielectric layer of half autoregistration;
Figure 10 shows autoregistration one step and graphically forms source electrode, leakage-auxiliary grid combination electrode.
Embodiment
Below with the representative of semiconductor type carbon nano-tube film for spatia zonularis semiconductor; by an instantiation about the PMOS of carbon nano-tube film, content of the present invention is described; only as a reference, the scope that scope defines with claims is as the criterion example.
The present invention has the autoregistration double grid carbon nano-tube film transistor of high on-off ratio, as shown in Fig. 2 (a), comprise: dielectric substrate (201), semiconductor type carbon nano-tube film (202), gate dielectric layer (203), main grid structure (primary gate electrode (204), primary gate electrode top layer (205), with side wall (206)), source electrode (208), leakage-auxiliary gate electrode composite construction (209), semiconductor type carbon nano-tube film (202) respectively and clip between source electrode (208) and leaking-auxiliary gate electrode composite construction (209) and infiltrate boundary layer (207).Main grid realizes the normal switching function of transistor; Auxiliary gate electrode has inhibitory action to the few sub-reverse tunnel of drain terminal.
The material of dielectric substrate (201) can be silica, and quartz, glass, the hard insulations such as aluminium oxide, and PET, PEN, the high-temperature flexible insulating material such as polyimides, using quartz substrate as substrate in the present embodiment.
Semiconductor type carbon nano-tube film (202) is for having the carbon nano-tube film of 90% ~ 99.99% semiconductor ratio, can be carbon nano pipe array and the carbon nano-tube Network film of grown on quartz, carbon pipe self-assembled film, and appoint the composite bed of both combinations each other, be carbon nano-tube Network film in the present embodiment.
Gate dielectric layer (203) material can be silica, hafnium oxide, zirconia, yittrium oxide, tantalum oxide, lanthana or lanthana aluminium, the hard materials such as silicon nitride, or epoxy resin, the organic polymer insulating barriers such as PMMA, thickness range is 2 ~ 100nm, adopts thickness to be the hafnium oxide of 5nm in the present embodiment.
The electrode (209) of source electrode (208) and leakage-auxiliary grid composite construction can Pd, Pt, Ti, Cu, Al, the various metal such as W, conductive metal suicide, the electric conducting materials such as doped polycrystalline silicon, and the laminated construction of above-mentioned electric conducting material, or adopt high-density carbon nano-tube conducting film (transparency electrode), thickness range is 20 ~ 100nm.Thickness is adopted to be that the platinum/palladium composite bed of 30/2nm is as the source electrode of PMOS and leakage-auxiliary grid combination electrode in the present embodiment, wherein 2nm palladium layers is as the infiltration boundary layer (207) between CNT and platinum layer, and the high work function platinum layer of 30nm regulates the auxiliary grid of PMOS to be depletion type mode of operation.Platinum/palladium the composite bed of 30/2nm can meet the needs of PMOS without the contact of potential barrier source and drain and auxiliary grid depletion-mode simultaneously.
The material of primary gate electrode (204) can Pd, Pt, Ti, Cu, Al, the various metal such as W, conductive metal suicide, the electric conducting materials such as doped polycrystalline silicon, and the laminated construction of above-mentioned electric conducting material, or adopt high-density carbon nano-tube conducting film (transparency electrode), thickness range is 20 ~ 100nm.In principle, should in conjunction with concrete technique, select the metal of appropriate work function number to make main grid be in enhancement mode mode of operation, in the present embodiment, primary gate electrode selects thickness to be the Pd of 30nm.
The principle of above-mentioned dual gate FET on electrical behavior is as shown in Fig. 2 (b), corresponding OFF state energy band diagram is as shown in Fig. 3 (a), auxiliary grid (feedback grid) electrode is connected with drain electrode D, make a pinned rectangular barrier near drain electrode, and keep equipotential due to auxiliary gate electrode and drain electrode, this rectangular barrier is made not change with bias voltage like this, thus suppress the few sub-tunnelling of the drain terminal when OFF state and improve bipolarity, S in Fig. 3 (a) represents the electronics filling of source electrode, and D represents the electronics filling of drain electrode.
The above-mentioned preparation method with the double grid carbon nano-tube film transistor of high on-off ratio, as shown in figures 4-9, specifically comprises the following steps:
1., in dielectric substrate (201) (as quartz substrate) upper transfer carbon nano-tube NETWORK film (401), thickness range is from 1nm to 100nm.As shown in Figure 4.Concrete transfer method comprises dry method transfer, coating, nanometer ink jet printing, spin coating.
2. by photoetching and oxygen plasma etch technique, full wafer carbon nano-tube film (202) is etched into channel region isolated from one another, as shown in Figure 5.
3. on semiconductor type carbon nano-tube film (202), deposit the thick gate dielectric layer of one deck 5nm (203) with technique for atomic layer deposition, as shown in Figure 6.
4. deposit the thick primary gate electrode metal palladium layers of 30nm and the thick insulating oxide silicon layer of 30nm, and main grid (control gate) electrode (204) and the top layer (205) of device is formed by conventional photoetching and plasma etch process, the long representative value of main grid is 20nm, as shown in Figure 7.
5. form side wall protection structure (206) by conventional side wall technique in grid both sides, side wall typical thickness is 10nm, and spacer material can be SiN
3, SiO
2and other medium with low dielectric constant materials, as shown in Figure 8.
6. with main grid structure (204,205,206) as half autoregistration mask, the gate medium figure of device is formed in conjunction with photoetching (901 is photoresist mask PR) and oxide etch process, the left margin of photoresist mask PR is at main grid center line, the typical length of the right margin distance right-side wall external boundary of photoresist mask PR is 20nm, as shown in Figure 9.
7. with main grid structure (204,205,206) as autoregistration mask, carry out successively: deposition 2nm Metal Palladium (the infiltration boundary layer (207) as carbon pipe and electrode), deposition 30nm metal platinum, then the technique of photoetching and plasma etching, form the source electrode (208) of device, leakage-auxiliary grid combination electrode (209), the typical length of source-drain electrode is 30nm simultaneously; The length of auxiliary gate electrode is equal to the length of the gate medium figure outside right-side wall, and its typical length is 20nm, as shown in Figure 10.The GatePitch=90nm of the device in whole example, mutually compatible with the lithography process precision of current microelectronics industry.
Claims (10)
1. there is an autoregistration double grid spatia zonularis semiconductor transistor for high on-off ratio, comprising: dielectric substrate, spatia zonularis semiconductor layer, gate dielectric layer, main grid structure, source electrode, leakage-auxiliary grid combination electrode; Described spatia zonularis semiconductor layer is positioned on dielectric substrate; Described gate dielectric layer is positioned at spatia zonularis semiconductor layer; Described main grid structure is on gate dielectric layer and between source electrode and leakage-auxiliary grid combination electrode, described main grid structure comprises primary gate electrode, top layer and side wall, top layer is positioned at directly over primary gate electrode, and side wall is positioned at the both sides of primary gate electrode and top layer; Described source electrode and leakage-auxiliary grid combination electrode lay respectively on spatia zonularis semiconductor layer two ends, between source electrode and spatia zonularis semiconductor layer and leak-between auxiliary grid combination electrode and spatia zonularis semiconductor layer, there is infiltration boundary layer respectively, it is outer and be positioned on gate dielectric layer that auxiliary gate electrode in described leakage-auxiliary grid combination electrode is positioned at side wall, and described auxiliary gate electrode is all connected physically with in electricity with drain electrode.
2. have the autoregistration double grid spatia zonularis semiconductor transistor of high on-off ratio as claimed in claim 1, it is characterized in that, the material of described dielectric substrate comprises silica, quartz, glass, aluminium oxide and PET, PEN, polyimides.
3. have the autoregistration double grid spatia zonularis semiconductor transistor of high on-off ratio as claimed in claim 1, it is characterized in that, the typical bandgap of described spatia zonularis semiconductor layer is less than 1eV, comprise semiconductor type carbon nano-tube film, graphene nanobelt, molybdenum bisuphide, tungsten disulfide, black phosphorus; And germanium, indium arsenide, indium antimonide, vulcanized lead, lead selenide, lead telluride, and the composite bed of appointing both combinations each other.
4. have the autoregistration double grid spatia zonularis semiconductor transistor of high on-off ratio as claimed in claim 1, it is characterized in that, the material of described gate dielectric layer is silica, hafnium oxide, zirconia, yittrium oxide, tantalum oxide, lanthana, lanthana aluminium, silicon nitride, epoxy resin or PMMA.
5. there is the autoregistration double grid spatia zonularis semiconductor transistor of high on-off ratio as claimed in claim 1, it is characterized in that, the material of described primary gate electrode, source electrode and leakage-auxiliary grid combination electrode is selected from Pd, Pt, Ti, Cu, Al, Au, W, conductive metal suicide, doped polycrystalline silicon, and the laminated construction of above-mentioned electric conducting material.
6. there is the autoregistration double grid spatia zonularis semiconductor transistor of high on-off ratio as claimed in claim 1, it is characterized in that, the working method of described transistor is non-impurity-doped formula, and the type of transistor is determined by the unipolarity of the contact berrier of source-drain electrode and semi-conducting material.
7. the arbitrary described preparation method with the autoregistration double grid spatia zonularis semiconductor transistor of high on-off ratio of claim 1-6, comprises the steps:
1) shift on an insulating substrate or grow spatia zonularis semiconductor layer;
2) by photoetching and plasma etch process, the spatia zonularis semiconductor layer of full wafer is patterned into channel region isolated from one another;
3) on spatia zonularis semiconductor layer, gate dielectric layer is deposited;
4) on gate dielectric layer, deposit primary gate electrode metal level and insulating oxide silicon layer successively, and form the primary gate electrode of device with photoetching and etching technics;
5) side wall technique is adopted to form side wall protection structure in primary gate electrode both sides;
6) using main grid structure as half autoregistration mask, gate medium figure is formed in conjunction with photoetching and etching technics;
7) using main grid structure as autoregistration mask, the boundary layer of sedimentary origin electrode, leakage-auxiliary grid combination electrode and electrode metal layer, form source electrode, leakage-auxiliary grid combination electrode by the technique of photoetching and etching.
8. preparation method as claimed in claim 7, is characterized in that, step 1) in the method for transfer spatia zonularis semiconductor layer be selected from dry method transfer, coating, nanometer ink jet printing or spin coating.
9. preparation method as claimed in claim 7, is characterized in that, step 3) in the method for deposition gate insulation dielectric layer be selected from ald, sputter and anneal, sputtering also thermal oxidation, sol-gel process or spin coating hot setting.
10. preparation method as claimed in claim 7, is characterized in that, step 4) in deposition primary gate electrode metal level and step 7) in sedimentary origin electrode, leakage-auxiliary grid combination electrode the method for electrode metal layer be selected from the hot evaporation of electron beam or sputtering.
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