CN108376740B - Composite channel transistor and preparation method thereof - Google Patents
Composite channel transistor and preparation method thereof Download PDFInfo
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- CN108376740B CN108376740B CN201810048091.4A CN201810048091A CN108376740B CN 108376740 B CN108376740 B CN 108376740B CN 201810048091 A CN201810048091 A CN 201810048091A CN 108376740 B CN108376740 B CN 108376740B
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
- H10K10/488—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising a layer of composite material having interpenetrating or embedded materials, e.g. a mixture of donor and acceptor moieties, that form a bulk heterojunction
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Abstract
The invention discloses a composite channel transistor, comprising: an interlayer dielectric layer on the semiconductor substrate; a gate electrode in the interlayer dielectric layer; a gate dielectric layer on the gate; a composite channel layer on the gate dielectric layer and the interlayer dielectric layer; source and drain regions located at two ends of the composite channel layer; a passivation layer located on the interlayer dielectric layer and covering the periphery and the upper surface of the composite channel layer; and the source and drain electrodes are positioned in the passivation layer and connected with the source and drain regions. According to the invention, the graphene with high mobility and the organic film with the adjustable band gap are selected to form the composite channel layer together, so that the problems that the graphene does not have the band gap and the mobility of the organic film transistor is low can be effectively solved, the composite channel transistor with high mobility is prepared, and the composite channel transistor is compatible with the existing CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and feasible, and a small-size and large-scale composite channel transistor array can be conveniently prepared. The invention also discloses a preparation method of the composite channel transistor.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a composite channel transistor and a preparation method thereof.
Background
With the scaling down of the characteristic dimension of the semiconductor device according to the law of mole, the chip integration level is continuously improved, and the performance and power consumption requirements of the device and the circuit are difficult to meet due to the process limit and various negative effects of the traditional silicon-based semiconductor device. Various new materials and new device structures are researched by various scientific research institutions and semiconductor manufacturers at home and abroad so as to replace the existing silicon semiconductor devices.
In recent years, graphene has been used for its ultrahigh electron mobility (up to 200000 cm)2Vs) has become a hotspot of research, but since graphene does not have a bandgap (bandgap), it has poor prospects in applications similar to transistors.
On the other hand, with the development of organic conductive polymers, attempts have been made to replace the insulating layer, semiconductor and gate electrode of the inorganic field effect transistor with organic materials, thereby developing a new type of organic thin film field effect transistor. Compared with inorganic thin film field effect transistors, organic thin film field effect transistors have the following main advantages:
(1) the organic thin film has more and more updated film forming technologies (such as molecular self-assembly technology), the size of the device can be made smaller (molecular scale), the integration level is higher, and the operating power can be effectively reduced.
(2) The organic field effect transistor is simpler in manufacturing process (the manufacturing process does not require strict control of atmosphere conditions and strict purity requirements), so that the cost of the device can be effectively reduced.
(3) The organic thin film can adjust the size of the band gap of the organic thin film by adjusting and modifying the structure of organic molecules.
However, most organic materials have poor electrical conductivity due to their low mobility. Therefore, how to utilize the respective advantages of the graphene and the organic thin film to prepare the composite channel transistor with high mobility, and the composite channel transistor is compatible with the CMOS process, which is a problem to be solved urgently.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned drawbacks of the prior art, and provides a composite channel transistor and a method for fabricating the same.
In order to achieve the purpose, the technical scheme of the invention is as follows:
the invention provides a composite channel transistor, which comprises the following components from bottom to top:
an interlayer dielectric layer on the semiconductor substrate;
a gate electrode in the interlayer dielectric layer;
a gate dielectric layer on the gate;
a composite channel layer on the gate dielectric layer and the interlayer dielectric layer;
source and drain regions located at two ends of the composite channel layer;
the passivation layer is positioned on the interlayer dielectric layer and covers the periphery and the upper surface of the composite channel layer;
the source and drain electrodes are positioned in the passivation layer and are connected with the source and drain regions;
the composite channel layer is a laminated layer consisting of at least one layer of graphene and at least one layer of organic film.
Preferably, the organic thin film material is at least one of acene, oligothiophene, perylene, naphthalene, anthracene, rubrene, and TTF derivative. The gate material is at least one of metal, polysilicon and a conductive polymer. The gate dielectric layer is made of SiO2SiN, SiON, high-k dielectric materials, metal oxides, and organic insulating materials.
Preferably, the source and drain regions are formed by doping the graphene thin film above the interlayer dielectric layers on both sides of the gate.
The invention also provides a preparation method of the composite channel transistor, which comprises the following steps:
step S01: providing a semiconductor substrate, forming an interlayer dielectric layer on the semiconductor substrate, and forming a groove on the interlayer dielectric layer;
step S02: depositing a grid electrode material in the groove to form a grid electrode;
step S03: forming a gate dielectric layer on the gate;
step S04: forming a composite channel layer on the gate dielectric layer;
step S05: forming source and drain regions at two ends of the composite channel layer;
step S06: forming a passivation layer on the device surface on the composite channel layer;
step S07: forming a source drain electrode in the passivation layer above the source drain region;
the composite channel layer is formed by a lamination layer consisting of at least one layer of graphene and at least one layer of organic thin film.
Preferably, in step S04, the composite channel layer is formed through a deposition and/or transfer process.
Preferably, in step S05, the source and drain regions are formed by doping the graphene film on the interlayer dielectric layer on both sides of the gate.
Preferably, when the uppermost layer of the composite channel layer is a graphene layer, the source drain region is formed by directly doping graphene films on two sides of the composite channel layer; when the uppermost layer of the composite channel layer is an organic thin film layer, the organic thin film layers on two sides of the composite channel layer are removed through photoetching and etching processes, the graphene layer below the composite channel layer is exposed, and then the exposed graphene thin film is doped to form the source drain region.
Preferably, in step S07, the source-drain electrode is at least one of a metal, a conductive polymer, and graphene.
According to the technical scheme, the graphene with high mobility and the organic thin film with the adjustable band gap are selected to form the composite channel layer together, the source drain region is formed in the graphene thin film in a doped mode, the problems that the graphene does not have the band gap and the mobility of the organic thin film transistor is low can be effectively solved, the composite channel transistor with the high mobility is prepared, the composite channel transistor is compatible with the existing CMOS process, the preparation process is simple and feasible, and the small-size and large-scale composite channel transistor array can be conveniently prepared.
Drawings
FIG. 1 is a schematic diagram of a composite channel transistor according to a preferred embodiment of the present invention;
FIGS. 2-3 are schematic views of composite channel layer structures according to two preferred embodiments of the present invention;
FIG. 4 is a flow chart of a method for fabricating a composite channel transistor according to the present invention;
fig. 5-11 are schematic diagrams of process steps in fabricating a composite channel transistor according to the method of fig. 4.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following detailed description of the present invention, please refer to fig. 1, in which fig. 1 is a schematic diagram of a composite channel transistor structure according to a preferred embodiment of the present invention. As shown in fig. 1, a composite channel transistor of the present invention at least includes, from bottom to top: the semiconductor substrate 101, the interlayer dielectric layer 102, the gate 103, the gate dielectric layer 104, the composite channel layer 105, the source-drain region 107, the passivation layer 106, the source-drain electrode 108 and the like form a device structure of the field effect transistor.
Please refer to fig. 1. A gate dielectric layer 104 is contiguously disposed between the gate 103 at a lower level and the composite channel layer 105 at an upper level. Wherein, the size of the grid and the grid dielectric layer is smaller than that of the composite channel layer; and, the gate and the gate dielectric layer may be substantially located at a middle position below the composite channel layer. Source and drain regions (i.e., one end is a source region and the other end is a drain region) 107 of the field effect transistor are provided at both ends of the composite channel layer.
The gate material may be at least one of metal, polysilicon, and conductive polymer. The gate metal can be, for example, W, Cu, Al, or the like; examples of the conductive polymer include polyacetylene, polythiophene, polypyrrole, polyaniline, polyphenylene ethylene, polydiyne, and the like.
The gate dielectric layer material can be SiO2SiN, SiON, high-k dielectric materials, metal oxides, organic insulating materials. Among them, organic insulating materials such as cyanoethyl-pluronic (CYEP), polymethyl methacrylate (PMMA), and the like.
Referring to fig. 2-3, fig. 2-3 are schematic views of composite channel layers according to two preferred embodiments of the present invention. The composite channel layer 105 in fig. 1 is a stacked structure composed of at least one graphene layer and at least one organic thin film layer. For example, as shown in fig. 2, the composite channel layer 105 may be composed of a graphene thin film 105a located at a lower layer and an organic thin film 105b located at an upper layer. Alternatively, as shown in fig. 3, the composite channel layer 105 may be formed of a sandwich structure of a graphene film 105c located in a lower layer, an organic film 105d located in an intermediate layer, and another graphene film 105e located in an upper layer. The present invention is not limited thereto.
The organic thin film material may adopt at least one of acene, oligothiophene, perylene, naphthalene, anthracene, rubrene, and TTF derivative. For example, pentacene, C60, C8-BTBT, tetracyanoquinodimethane, polyacetylene, polythiophene, metal phthalocyanine and the like can be used. The organic thin film material has a band gap width of 0.75-3 eV.
The source drain region 107 may be formed by a graphene film over the gate electrode; for example, source and drain regions may be formed on both sides of the channel by doping the graphene film in the composite channel layer over the interlayer dielectric layer on both sides of the gate. Wherein, the doping element can be As, B, P, etc.
Please continue to refer to fig. 1. In the composite channel transistor of the present invention, a passivation layer 106 is further disposed on the interlayer dielectric layer; the passivation layer 106 covers the periphery and upper surface of the composite channel layer 105 from above the device.
A source and drain electrode (namely a source electrode is arranged above the source region, and a drain electrode is arranged above the drain region) 108 is also arranged in the passivation layer above the source and drain regions; source-drain electrodes 108 connect the source-drain regions 107. The source electrode and the drain electrode can be made of at least one of metal, conductive polymer and graphene; for example, the source and drain electrodes may be made of a metal Cu material, or the source and drain electrodes may be formed of a material including a graphene film.
In addition, an interlayer dielectric layer 102 is provided in contact with the passivation layer 106 and the lower layer of the composite channel layer 105. The gate 103 is disposed in the interlayer dielectric layer 102, which covers the periphery and the bottom surface of the gate. A semiconductor substrate 101 is also provided in connection with the lower layer of the interlayer dielectric layer 102.
A method for manufacturing a composite channel transistor according to the present invention will be described in detail below with reference to the accompanying drawings.
Referring to fig. 4, fig. 4 is a schematic flow chart of a method for fabricating a composite channel transistor according to the present invention; referring to fig. 5-11, fig. 5-11 are schematic process steps for fabricating a composite channel transistor according to the method of fig. 4. As shown in fig. 4, the method for manufacturing a composite channel transistor of the present invention can be used for manufacturing the composite channel transistor, and includes the following steps:
step S01: providing a semiconductor substrate, forming an interlayer dielectric layer on the semiconductor substrate, and forming a groove on the interlayer dielectric layer.
Please refer to fig. 5. First, an interlayer dielectric layer 202 may be grown on the semiconductor substrate 201 using a conventional semiconductor substrate 201. The interlayer dielectric layer 202 may be formed using conventional materials. Then, a groove 203 may be formed on the interlayer dielectric layer 202 by a photolithography and etching process. In the present embodiment, the depth of the groove 203 may be 60nm (nanometers).
Step S02: and depositing a gate material in the groove to form a gate.
Please refer to fig. 6. Next, a gate material is deposited in the recess 203, and a polishing process may be used to remove excess gate material outside the recess 203, thereby forming a gate 204 in the recess. The gate material may be at least one of a metal, polysilicon, and a conductive polymer. In the present embodiment, the gate material is Al metal.
Step S03: a gate dielectric layer is formed on the gate.
Please refer to fig. 7. Next, a gate dielectric layer material is deposited on the device surface, and a gate dielectric layer 205 is formed over the gate 204 by photolithography and etching processes. The gate dielectric layer material may be SiO2SiN, SiON, high-k dielectric materials, metal oxides, and organic insulating materials. In the present embodiment, the material of the gate dielectric layer is HfO2The thickness may be 3 nm.
Step S04: and forming a composite channel layer on the gate dielectric layer.
Please refer to fig. 8. Next, a composite channel layer may be formed on the surface of the device by deposition and/or transfer processes. The composite channel layer is formed by a lamination layer consisting of at least one layer of graphene and at least one layer of organic film. For example, the composite channel layer may be formed of at least one layer of graphene 206 positioned at a lower layer and one layer of organic thin film 207 positioned at an upper layer of the graphene 206.
Then, the organic thin film layer 207 at the two ends of the composite channel layer may be removed by photolithography and etching processes, so that the organic thin film layer in the composite channel layer is only located above the gate 204, and the graphene thin film 206 on the interlayer dielectric layer 202 is exposed at the two ends of the composite channel layer.
The organic thin film may be at least one of acene, oligothiophene, perylene, naphthalene, anthracene, rubrene, TTF derivatives. In this embodiment, the composition of the composite channel layer was 5nm of graphene and 10nm of pentacene in this order.
Step S05: and forming source and drain regions at two ends of the composite channel layer.
Please refer to fig. 9. Then, the graphene layer 206 exposed at both ends of the composite channel layer above the gate is doped to form a source drain region 208. Forming source and drain regions on two sides of the channel by doping; the doping element may be As, B, P, etc. In this embodiment, the graphene layer of PMOS is B-doped, and the graphene layer of NMOS is As-doped.
It should be noted that, when the uppermost layer of the composite channel layer is a graphene layer, the graphene films at two ends of the composite channel layer may be directly doped to form the source/drain regions. Only when the uppermost layer of the composite channel layer is the organic thin film layer, the organic thin film layers at two ends of the composite channel layer are removed through photoetching and etching processes, the graphene layer below the composite channel layer is exposed, and then the exposed graphene thin film is doped to form the source drain region.
Step S06: and forming a passivation layer on the surface of the device on the composite channel layer.
Please refer to fig. 10. Next, a passivation layer 209 is deposited over the composite channel layer and source and drain regions. The passivation layer material can be SiO2SiN, SiON, and a low dielectric constant (low k) material. In this embodiment, the passivation layer is SiOC with a thickness of 300 nm.
Step S07: and forming a source drain electrode in the passivation layer above the source drain region.
Please refer to fig. 11. Next, a via hole may be formed in the passivation layer 209 above the source/drain region 208 by photolithography and etching processes, and the via hole may be filled with a source/drain electrode thin film material, such as Cu.
Finally, planarization may be performed by polishing to form source and drain electrodes 210 that are flush with the surface of the passivation layer.
The source and drain electrodes may be made of at least one of metal, conductive polymer, and graphene.
In summary, the graphene with high mobility and the organic thin film with the adjustable band gap are selected to form the composite channel layer together, and the source and drain regions are formed in the graphene thin film by doping, so that the problems that the graphene does not have the band gap and the mobility of the organic thin film transistor is low can be effectively solved, the composite channel transistor with high mobility is prepared, and the composite channel transistor is compatible with the existing CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and feasible, and a small-size and large-scale composite channel transistor array can be conveniently prepared.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
Claims (9)
1. A composite channel transistor comprising, from bottom to top:
an interlayer dielectric layer on the semiconductor substrate;
a gate electrode in the interlayer dielectric layer;
a gate dielectric layer on the gate;
a composite channel layer on the gate dielectric layer and the interlayer dielectric layer;
source and drain regions located at two ends of the composite channel layer;
the passivation layer is positioned on the interlayer dielectric layer and covers the periphery and the upper surface of the composite channel layer;
the source and drain electrodes are positioned in the passivation layer and are connected with the source and drain regions;
the composite channel layer is a laminated layer consisting of at least one layer of graphene and at least one layer of organic thin film, the projection sizes of the grid and the grid dielectric layer perpendicular to the surface of the semiconductor substrate are smaller than the projection size of the composite channel layer, and the organic thin film is made of at least one of acene, oligothiophene, perylene, naphthalene, anthracene, rubrene and TTF derivatives.
2. The compound channel transistor of claim 1, wherein the gate material is at least one of a metal, polysilicon, and a conductive polymer.
3. The composite channel transistor of claim 1, wherein the gate dielectric layer material is at least one of SiO2, SiN, SiON, high-k dielectric material, metal oxide, and organic insulating material.
4. The composite channel transistor of claim 1, wherein the source and drain regions are formed by doping the graphene film over the interlayer dielectric layer on both sides of the gate.
5. A preparation method of a composite channel transistor is characterized by comprising the following steps:
step S01: providing a semiconductor substrate, forming an interlayer dielectric layer on the semiconductor substrate, and forming a groove on the interlayer dielectric layer;
step S02: depositing a grid electrode material in the groove to form a grid electrode;
step S03: forming a gate dielectric layer on the gate;
step S04: forming a composite channel layer on the grid dielectric layer, wherein the projection sizes of the grid and the grid dielectric layer vertical to the surface of the semiconductor substrate are smaller than the projection size of the composite channel layer;
step S05: forming source and drain regions at two ends of the composite channel layer;
step S06: forming a passivation layer on the device surface on the composite channel layer;
step S07: forming a source drain electrode in the passivation layer above the source drain region;
the composite channel layer is formed by a lamination layer formed by at least one layer of graphene and at least one layer of organic thin film, and the organic thin film material is at least one of acene, oligothiophene, perylene, naphthalene, anthracene, rubrene and TTF derivatives.
6. The method of manufacturing a composite channel transistor according to claim 5, wherein in step S04, the composite channel layer is formed by a deposition and/or transfer process.
7. The method of claim 5, wherein in step S05, the source and drain regions are formed by doping the graphene thin film on the interlayer dielectric layer on both sides of the gate.
8. The method for manufacturing the composite channel transistor according to claim 7, wherein when the uppermost layer of the composite channel layer is a graphene layer, the source and drain regions are formed by directly doping graphene films on two sides of the composite channel layer; when the uppermost layer of the composite channel layer is an organic thin film layer, the organic thin film layers on two sides of the composite channel layer are removed through photoetching and etching processes, the graphene layer below the composite channel layer is exposed, and then the exposed graphene thin film is doped to form the source drain region.
9. The method for manufacturing a composite channel transistor according to claim 5, wherein in step S07, the source and drain electrodes are at least one of metal, conductive polymer and graphene.
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| CN108376740B (en) * | 2018-01-18 | 2022-03-29 | 上海集成电路研发中心有限公司 | Composite channel transistor and preparation method thereof |
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| CN114864708A (en) * | 2022-05-06 | 2022-08-05 | 北京交通大学 | Multi-grid graphene field effect transistor type photoelectric sensor and preparation method thereof |
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