CN104332457A - 高密度IO互连PoP堆叠封装结构及其制造工艺 - Google Patents

高密度IO互连PoP堆叠封装结构及其制造工艺 Download PDF

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CN104332457A
CN104332457A CN201410453946.3A CN201410453946A CN104332457A CN 104332457 A CN104332457 A CN 104332457A CN 201410453946 A CN201410453946 A CN 201410453946A CN 104332457 A CN104332457 A CN 104332457A
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copper post
soldered ball
package body
lower package
packaging body
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林挺宇
孙鹏
何洪文
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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Abstract

本发明涉及一种高密度IO互连PoP堆叠封装结构及其制造工艺，包括上封装体和下封装体，其特征是：所述下封装体包括具有内部连线结构的下封装体基板，在下封装体基板的背面设置背面焊球，在下封装体基板正面固定芯片和多个正面焊球，正面焊球上设置铜柱，芯片、正面焊球和铜柱被塑封于塑封材料中，铜柱的下端与正面焊球固定，铜柱的上端凸出于塑封材料的表面；所述上封装体背面的焊球与下封装体中的铜柱上表面连接。本发明通过在PoP下封装体上涂覆焊锡膏和贴装金属铜柱的方式，缩小上、下封装体之间的互连节距，提升I/O互连数量。

Description

高密度IO互连PoP堆叠封装结构及其制造工艺
技术领域
本发明涉及一种高密度IO互连PoP堆叠封装结构及其制造工艺，属于半导体封装技术领域。
背景技术
移动通信产品关键是要解决“带宽”的问题，通俗的讲就是高速处理信号的能力。解决方案之一就是在逻辑器件上放置一枚存储器件（通常为动态存储器）；即，通过叠层封装（Package on Package，POP封装）将内存和处理器封装到了一起，实现小型化，节约电路板空间、减少引脚数、简化***集成和提高性能。PoP封装有助于客户推出体积小巧、功能丰富的无线电话、PDA、数码相机和MP3播放器。
随着用户对先进功能不断增长的需求，PoP封装中逻辑器件和存储器件之间的互连密度不断提高。在这种情况下，靠进一步缩小PoP封装中焊球尺寸的方式来提升互连I/O数量受到材料物理特性和设备工艺的限制，互连I/O数量逐渐成为限制PoP封装性能提升的瓶颈。
而在公布号为CN102325431A的专利申请文件中，公开了一种在电路板上制作铜柱的方法和具有表面铜柱的电路板，在基板上通过电镀制作铜柱的方法,从而可以减小I/O互连节距，提升互连数量。但电镀耗费过大，故有必要提出一种新的铜柱制作方式，以解决现有电镀方式费用过大的问题。
器件的堆叠是提高电子封装高密化的主要途径之一，作为目前封装高密集成的主要方式，PoP封装得到越来越多的重视。现有技术中，典型的两层PoP封装结构一般如图1所示，上封装体1a通过焊球2a的回流过程焊接到下封装体3a的上面。为了避免下封装体3a上的芯片4a碰撞上封装体1a，上封装体1a周边的焊球2a直径一般设计为大于下封装体3a上芯片4a的高度，但是如此设计就增加了焊球2a及其间距的尺寸，这与封装技术的高密集成要求相背。因此有必要对上述封装结构进行进一步改进。
发明内容
本发明的目的是克服现有技术中存在的不足，提供一种高密度IO互连PoP堆叠封装结构及其制造工艺，缩小上封装体和下封装体之间的互连节距，提升I/O互连数量；另外所述制造工艺相比基板电镀工艺，成熟度高，成本低。
按照本发明提供的技术方案，所述高密度IO互连PoP堆叠封装结构，包括上封装体和下封装体，其特征是：所述下封装体包括具有内部连线结构的下封装体基板，在下封装体基板的背面设置背面焊球，在下封装体基板正面固定芯片和多个正面焊球，正面焊球上设置铜柱，芯片、正面焊球和铜柱被塑封于塑封材料中，铜柱的下端与正面焊球固定，铜柱的上端凸出于塑封材料的表面；所述上封装体背面的焊球与下封装体中的铜柱上表面连接。
进一步的，所述铜柱的外圆周面包裹一层塑胶层，铜柱的上下表面为裸露表面。
进一步的，所述铜柱的高度大于芯片的高度。
进一步的，所述的塑胶层的厚度为10～20μm。
所述高密度IO互连PoP堆叠封装结构的制造工艺，其特征是，包括以下步骤：
（1）在做好内部连线结构的下封装体基板的上表面涂覆焊锡膏，得到多个正面焊球；
（2）将铜柱放置于对应的正面焊球处，并将铜柱的一端与正面焊球焊接固定；
（3）在下封装体基板上表面安装芯片；
（4）采用塑封材料将正面焊球、铜柱和芯片塑封成一整体；
（5）对塑封材料的上表面进行抛光，以露出铜柱的上表面，使铜柱的上端凸出于塑封材料的上表面；
（6）在下封装体基板下表面进行植球，得到背面焊球，完成下封装体的制作；
（7）将步骤（6）得到的下封装体与上封装体进行堆叠，上封装体背面的焊球与下封装体中的铜柱上表面连接。
进一步的，所述铜柱凸出于塑封材料上表面的高度为10～20μm。
本发明所述高密度IO互连PoP堆叠封装结构及其制造工艺，通过在PoP下封装体上涂覆焊锡膏和贴装金属铜柱（或塑胶包裹铜柱结构）的方式，缩小上、下封装体之间的互连节距，提升I/O互连数量。同时，本发明所述工艺相比基板电镀工艺，成熟度高，成本低，本发明为一些高密度I/O互连叠层封装PoP产品提供了一套实际高效的解决方案。
附图说明
图1为现有技术中两层PoP封装结构的示意图。
图2～图8为所述高密度IO互连PoP堆叠封装结构的制备流程图。其中：
图2为在下封装体基板上涂覆焊锡膏的示意图。
图3为在正面焊球上固定铜柱的示意图。
图4为在下封装体中安装芯片的示意图。
图5将正面焊球、铜柱和芯片进行塑封的示意图。
图6为对塑封材料进行抛光的示意图。
图7为制作背面焊球的示意图。
图8为本发明所述高密度IO互连PoP堆叠封装结构的示意图。
图9为采用塑胶芯表面镀铜结构铜柱的封装结构示意图。
图中序号：下封装体基板1、正面焊球2、铜柱3、塑胶层3-1、芯片4、塑封材料5、背面焊球6、下封装体7。
具体实施方式
下面结合具体附图对本发明作进一步说明。
如图8所示：所述高密度IO互连PoP堆叠封装结构包括上封装体1a和下封装体7，下封装体7包括已做好内部连线结构的下封装体基板1，在下封装体基板1的背面设置背面焊球6，在下封装体基板1正面固定芯片4和多个正面焊球2，正面焊球2上设置铜柱3，铜柱3的高度大于芯片4的高度，芯片4、正面焊球2和铜柱3被塑封于塑封材料5中，铜柱3的下端与正面焊球2固定，铜柱3的上端凸出于塑封材料5的表面，铜柱3凸出于塑封材料5表面的高度为10～20μm；所述上封装体1a背面的焊球2a与下封装体7中的铜柱3上表面实现电连接，可以避免下封装体7上的芯片4碰撞上封装体1a；
所述铜柱3也可以采用如图9所示的结构，在铜柱3的外圆周面包裹一层塑胶层3-1，铜柱3的上下表在为裸露表面，起到保护铜柱3，防止氧化的作用。
上述高密度IO互连PoP堆叠封装结构的制造工艺，包括以下步骤：
（1）如图2所示，在做好内部连线结构的下封装体基板1的上表面涂覆焊锡膏，得到多个正面焊球2；
（2）如图3所示，采用表面贴装工艺将铜柱3放置于对应的正面焊球2处，并将铜柱3的一端与正面焊球2焊接固定；
（3）如图4所示，在下封装体基板1上表面安装芯片4，具体方法为：采用传统工艺（即die attach，芯片黏着工艺），在下封装体基板1上涂die attach paste（固晶胶），然后将芯片采用加压的方式安装在下封装体基板1上，进行固化；图4中采用的为倒装芯片；
（4）如图5所示，采用塑封材料5将正面焊球2、铜柱3和芯片4塑封成一整体；所述塑封材料5一般采用环氧树脂塑封料；
（5）如图6所示，对塑封材料5的上表面进行抛光，以露出铜柱3的上表面，使铜柱3的上端凸出于塑封材料5的上表面，以方便上下器件之间的堆叠加；所述铜柱3凸出于塑封材料5上表面的高度大概为10～20μm；
（6）如图7所示，在下封装体基板1下表面进行植球，得到背面焊球6，完成下封装体7的制作；
（7）如图8所示，将步骤（6）得到的下封装体7与已做好内层和外层连线结构的上封装体1a进行堆叠，上封装体1a背面的焊球2a与下封装体7中的铜柱3上表面实现电连接，可以避免下封装体7上的芯片4碰撞上封装体1a。
其中，步骤（2）所采用的铜柱3也可以采用如图9所示的结构，在铜柱3的外圆周面包裹一层塑胶层3-1，起到保护铜柱3，防止氧化的作用；其中，所述的塑胶层3-1采用的厚度为10～20μm。

Claims (6)

1.一种高密度IO互连PoP堆叠封装结构，包括上封装体（1a）和下封装体（7），其特征是：所述下封装体（7）包括具有内部连线结构的下封装体基板（1），在下封装体基板（1）的背面设置背面焊球（6），在下封装体基板（1）正面固定芯片（4）和多个正面焊球（2），正面焊球（2）上设置铜柱（3），芯片（4）、正面焊球（2）和铜柱（3）被塑封于塑封材料（5）中，铜柱（3）的下端与正面焊球（2）固定，铜柱（3）的上端凸出于塑封材料（5）的表面；所述上封装体（1a）背面的焊球（2a）与下封装体（7）中的铜柱（3）上表面连接。
2.如权利要求1所述的高密度IO互连PoP堆叠封装结构，其特征是：所述铜柱（3）的外圆周面包裹一层塑胶层（3-1），铜柱（3）的上下表面为裸露表面。
3.如权利要求1所述的高密度IO互连PoP堆叠封装结构，其特征是：所述铜柱（3）的高度大于芯片（4）的高度。
4.如权利要求2所述的高密度IO互连PoP堆叠封装结构，其特征是：所述的塑胶层（3-1）的厚度为10～20μm。
5.一种高密度IO互连PoP堆叠封装结构的制造工艺，其特征是，包括以下步骤：
（1）在做好内部连线结构的下封装体基板（1）的上表面涂覆焊锡膏，得到多个正面焊球（2）；
（2）将铜柱（3）放置于对应的正面焊球（2）处，并将铜柱（3）的一端与正面焊球（2）焊接固定；
（3）在下封装体基板（1）上表面安装芯片（4）；
（4）采用塑封材料（5）将正面焊球（2）、铜柱（3）和芯片（4）塑封成一整体；
（5）对塑封材料（5）的上表面进行抛光，以露出铜柱（3）的上表面，使铜柱（3）的上端凸出于塑封材料（5）的上表面；
（6）在下封装体基板（1）下表面进行植球，得到背面焊球（6），完成下封装体（7）的制作；
（7）将步骤（6）得到的下封装体（7）与上封装体（1a）进行堆叠，上封装体（1a）背面的焊球（2a）与下封装体（7）中的铜柱（3）上表面连接。
6.如权利要求5所述的高密度IO互连PoP堆叠封装结构的制造工艺，其特征是：所述铜柱（3）凸出于塑封材料（5）上表面的高度为10～20μm。
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