CN104316866A - Testing structure and method for chip - Google Patents
Testing structure and method for chip Download PDFInfo
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- CN104316866A CN104316866A CN201410667831.4A CN201410667831A CN104316866A CN 104316866 A CN104316866 A CN 104316866A CN 201410667831 A CN201410667831 A CN 201410667831A CN 104316866 A CN104316866 A CN 104316866A
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Abstract
The invention relates to a testing method for a chip. The testing method includes the steps that a testing vector is generated according to the logical function of a processing unit inside the chip; the testing vector is solidified and stored inside the chip; the processing unit is controlled to be switched between a working mode and a testing mode through switching operation; in the testing mode, the testing vector is called and transmitted to the processing unit, and then the processing unit is controlled to perform testing on the logical function. A solidifying and storing unit and a logic switching unit are integrated inside the chip, in this way, a peripheral plate in a traditional testing method is omitted, a vector storing unit is omitted, the cost is lowered, and testing time is shortened.
Description
Technical field
The present invention relates to chip processor field, espespecially a kind of test structure of chip and method of testing.
Background technology
Chip designs according to function during design and technical parameter, and the chip manufacturing and designing out, tests technical parameter when whether its performance reaches design, such as electric current, voltage, resistance, sequential, the test vectors such as cycle always.But this kind of digital circuit test of chip gets up very difficult, because including the logical circuit of thousands of logic gate compositions in chip, simple functional test in the past can not meet the test needs of chip, existing chip detecting method, as shown in Figure 1, utilize vector to produce software 101 and generate test vector, test vector is write in peripheral board 102, test vector is again by chip pin input chip 103, chip 103 is made to enter test module, chip logic 104 is tested, reach the object of test chip 103, but there is following defect in such way:
One, need peripheral board to generate test vector electric signal, peripheral board increases development task, lengthens the chip development time;
Two, test vector electric signal is very restricted by chip pin speed, causes test vector electric signal to input the time of chip to be measured well beyond internal chip enable signal speed more than ten times orders of magnitude;
Three, there is the existence of peripheral board, and also needing, the outside coaming plate of vector location is set inculcate test vector, make it cannot realize test environment miniaturization.
Summary of the invention
The object of the invention is to the defect overcoming prior art, there is provided a kind of test structure and method of testing of chip, solving the lengthening development time, the pin speed that exist in existing chip detecting method, to limit test vector electric signal input time of causing long and cannot realize the problem of test environment miniaturization.
The technical scheme realizing above-mentioned purpose is:
The method of testing of a kind of chip of the present invention, comprising:
According to the logic function of processing unit in chip and production test is vectorial;
Described test vector solidification is stored in described chip;
Controlled described processing unit to switch in mode of operation and test pattern by blocked operation; In described test pattern, transfer described test vector and described test vector is sent to described processing unit, and then controlling the test that described processing unit carries out described logic function.
Test vector is stored in chip, when logic function test is carried out to chip, directly transfer test vector, save the peripheral board in conventional test methodologies, avoid the exploitation of peripheral board, save vector location, cost-saving, shorten the test duration, and test environment miniaturization can be made.Adopt integration testing vector in chip, realize directly transmitting in test vector electric signal to processing unit carrying out chip testing, transfer rate, higher than being entered more than ten times of chip logic circuit in classic method by chip pin, shortens the test duration of chip greatly.
The further improvement of the method for testing of chip of the present invention is, controlled described processing unit to switch in mode of operation and test pattern by blocked operation, comprise: receive the external control signal outside from described chip, and carry out blocked operation according to described external signal.
The further improvement of the method for testing of chip of the present invention is, described external signal comprises high level signal and low level signal, when described external signal is high level signal, control described processing unit and be in test pattern, when described external signal is low level signal, controls described processing unit and be in mode of operation.
The test structure of a kind of chip of the present invention, comprising:
Be located at the processing unit in chip, there is logic function to be achieved;
Be located at the solidification storage unit in described chip, described solidification memory cell contains the test vector adapting to described logic function; And
Be located at the switching logic unit in described chip, processing unit described in described switching logic unit control linkage and described solidification storage unit, described switching logic unit switches in mode of operation and test pattern for controlling described processing unit; In described test pattern, described switching logic unit reads the test vector in described solidification storage unit, and is sent to described processing unit, and then controls described processing unit and carry out logic function test.
Chip arranges solidification cell stores test vector, and the test of chip has been controlled by switching logic unit, save the peripheral board in conventional test methodologies, avoid the exploitation of peripheral board, save vector location, cost-saving, shorten the test duration, and test environment miniaturization can be made.Adopt core Embedded solidification storage unit and switching logic unit, realize directly transmitting in test vector electric signal to processing unit carrying out chip testing, transfer rate, higher than being entered more than ten times of chip logic circuit in classic method by chip pin, shortens the test duration of chip greatly.
The further improvement of the test structure of chip of the present invention is, described switching logic unit comprises functional module and test module, described switching logic unit, by switching the duty of described functional module and described test module, realizes controlling described processing unit and switches in mode of operation and test pattern.
The further improvement of the test structure of chip of the present invention is, also comprise wire jumper circuit board, described wire jumper circuit board is provided with high level end and low level end, described switching logic unit connects high level end on described wire jumper circuit board and low level end by change-over switch, control described switching logic unit by change-over switch and connect described high level end or described low level end, realize the switching of the duty between described functional module in described switching logic unit and described test module.
The further improvement of the test structure of chip of the present invention is, when described change-over switch connects described high level end, the test module in described switching logic unit is in running order, and then controls described processing unit and be in test pattern; When described change-over switch connects described low level end, the functional module in described switching logic unit is in running order, and then controls described processing unit and be in mode of operation.
Accompanying drawing explanation
Fig. 1 is the structural representation of the method for testing of prior art chips;
Fig. 2 is the schematic diagram of the test structure of chip of the present invention; And
Fig. 3 is the circuit diagram of switching logic unit in chip of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described.
Consult Fig. 2, show the schematic diagram of the test structure of chip of the present invention.The test structure of chip of the present invention and method of testing, set up solidification storage unit in the chips for On-board test vector, the test of chip has been controlled by switching logic unit, this switching logic unit comprises functional module and test module, by the switching of duty between functional module and test module, realize the switching of processing unit between mode of operation and test pattern.Switching logic unit is by handoff functionality module work, and control chip processing unit is in mode of operation, and the processing unit realizing chip works operation normally, realizes the design logic function of processing unit; Switching logic unit is by switch test module work, the processing unit of control chip is in test pattern, carry out the test of logic function, test vector is transferred to processing unit by the test vector that this test module reads in solidification storage unit, and controlled processing unit carries out the test of logic function.The test structure of chip of the present invention and method of testing, the exploitation of existing peripheral board can be reduced, save the chip development time, chip arranges wire jumper circuit board, the work of the functional module and test module that control switching logic unit switches, and generates peripheral board without the need to designing complicated vector; Test vector chip storage inside and transmit, transfer rate is higher than more than ten when being transmitted by chip pin times; Only be provided with wire jumper in the periphery of chip, without the need to arranging peripheral board, the volume of huge compression peripheral board, can make full use of the test space.Below in conjunction with accompanying drawing, the test structure of chip of the present invention and method of testing are described.
Consult Fig. 2, show the schematic diagram of the test structure of chip of the present invention, below in conjunction with Fig. 2, the test structure of chip of the present invention is described.
As shown in Figure 2, the test structure of chip of the present invention comprises the processing unit 201 be located in chip 20, solidification storage unit 202, and switching logic unit 203, processing unit 201 has logic function to be achieved, the test vector of the logic function adapting to processing unit 201 is stored in solidification storage unit 202, switching logic unit 203 control linkage processing unit 201 and solidification storage unit 202, switching logic unit 203 controlled processing unit 201 switches in mode of operation and test pattern, in test pattern, switching logic unit 203 transfers the test vector stored in solidification storage unit 202, and send processing unit 201 to, controlled processing unit 201 carries out logic function test.
Functional module 2031 and test module 2032 is included in this switching logic unit 203, switching logic unit 203, by the switching of the duty of controlling functions module 2031 and test module 2032, realizes the blocked operation of mode of operation to processing unit 201 and test pattern.This functional module 2031 controlled processing unit 201 is in mode of operation, realize the logic function of processing unit 201 self, this test module 2032 controlled processing unit 201 is in test pattern, this test module 2032 reads the test vector in solidification storage unit 202, and the test vector of reading is sent to processing unit 201, and then controlled processing unit 201 carries out logic function test.
The test structure of chip of the present invention also comprises wire jumper circuit board 21, wire jumper circuit board 21 is provided with high level end 211 and low level end 212, switching logic unit 203 is by the high level end 211 on change-over switch 213 tie jumper circuit board 21 and low level end 212, this change-over switch 213 controls switching logic unit 203 and connects high level end 211 or switching logic unit 203 connects low level end 212, change-over switch 213 controls switching logic unit 203 when connecting high level end 211, test module 2032 in switching logic unit 203 works, controlled processing unit 201 is in test pattern, this test module 2032 reads the test vector in solidification storage unit 202, the test vector of reading is sent to processing unit 201, and then controlled processing unit 201 carries out logic function test.Change-over switch 213 controls switching logic unit 203 when connecting low level end 212, functional module 2031 in switching logic unit 203 works, controlled processing unit 201 is in mode of operation, this functional module 2031 controlled processing unit 201 is in running order, realizes the logic function of processing unit 201 self.The switching of the duty between functional module 2031 and test module 2032 is achieved by change-over switch 213.As shown in Figure 3, the circuit diagram of switching logic unit in chip of the present invention is shown.Wherein S is selecting side, A and B is respectively input, and Y exports.The Boolean expression of its Y is:
when S is low level, namely 0 time,
namely Y equals A, and circuit disconnects B and connects between Y, and Y is switched to A.When S is high level, namely 1 time,
namely Y equals B, and circuit disconnects A and connects between Y, and Y is switched to B.In the present embodiment, A is held linkage function module 2031, B is held connecting test module 2032, Y holds connection handling unit 201, S selecting side connects change-over switch 213, and the low and high level of change-over switch 213 control S selecting side, carries out control output end Y linkage function module 2031 or test module 2032, realize the duty of handoff functionality module 2031 and test module 2032, and then the processing unit 201 controlling chip is in mode of operation or test pattern.
Below the method for testing of chip of the present invention is described.
The method of testing of chip of the present invention comprises:
As shown in Figure 2, generate test vector according to the logic function of processing unit in chip 201, processing unit 201 has logic function to be achieved, and this test vector is matched with this logic function;
Test vector solidification is stored in chip, solidification storage unit 202 can be set on chip 20, for storing this test vector;
By blocked operation, controlled processing unit 201 switches in mode of operation and test pattern; In test pattern, transfer test vector and test vector is sent to processing unit 201, and then controlled processing unit 201 carries out the test of logic function.Switching logic unit 203 can be set on chip 20, processing unit 201 is switched between mode of operation and test module and controls, by switching logic unit 203 control linkage solidification storage unit 202 and processing unit 201, switching logic unit 203 controlled processing unit 201 switches in mode of operation and test pattern, when controlled processing unit 201 is switched to test pattern, the test vector that switching logic unit 203 is transferred in solidification storage unit 202 sends processing unit 201 to, and controlled processing unit 201 carries out logic function test.
Wherein: by blocked operation, controlled processing unit switches in mode of operation and test pattern, comprising: receive the external control signal outside from chip, and carry out blocked operation according to external signal.This external signal comprises high level signal and low level signal, and when external signal is high level signal, controlled processing unit is in test pattern, and when external signal is low level signal, controlled processing unit is in mode of operation.Functional module 2031 and test module 2032 are set in switching logic unit 203, by the duty of switching logic unit 203 handoff functionality module 2031 and test module 2032, realize the switching of processing unit 201 between mode of operation and test pattern.The switching of the functional module 2031 in control switching logic unit 203 and the duty of test module 2032, can at the outer setting wire jumper circuit board 21 of chip 20, this wire jumper circuit board 21 is provided with high level end 211 and low level end 212, switching logic unit 203 is by the high level end 211 on change-over switch 213 tie jumper circuit board 21 or low level end 212, change-over switch 213 controls switching logic unit 203 and connects high level end 211, test module 2032 in switching logic unit 203 works, this test module 2032 reads the test vector in solidification storage unit 202, and the test vector of reading is sent to processing unit 201, and then controlled processing unit 201 carries out logic function test.Change-over switch 213 controls switching logic unit 203 and connects low level end 212, and the functional module 2031 in switching logic unit 203 works, and this functional module 2031 controlled processing unit 201 is in mode of operation, realizes the logic function of processing unit 201 self.
The test structure of chip of the present invention and the beneficial effect of method of testing are:
Adopt integrated solidification storage unit and switching logic unit on chip, the processing unit realized on chip can carry out logic function test easily, save the peripheral board in conventional test methodologies, avoid the exploitation of peripheral board, save vector location, cost-saving, shorten the test duration, and test environment miniaturization can be made.
Adopt core Embedded solidification storage unit and switching logic unit, realize directly transmitting in test vector electric signal to processing unit carrying out chip testing, transfer rate, higher than being entered more than ten times of chip logic circuit in classic method by chip pin, shortens the test duration of chip greatly.
The trigging control of switching logic unit only needs the low and high level of wire jumper circuit board to control, and structure is simple, easy to operate.
Below embodiment is to invention has been detailed description by reference to the accompanying drawings, and those skilled in the art can make many variations example to the present invention according to the above description.Thus, some details in embodiment should not form limitation of the invention, the present invention by the scope that defines using appended claims as protection scope of the present invention.
Claims (7)
1. a method of testing for chip, is characterized in that, comprising:
Test vector is generated according to the logic function of processing unit in chip;
Described test vector solidification is stored in described chip;
Controlled described processing unit to switch in mode of operation and test pattern by blocked operation; In described test pattern, transfer described test vector and described test vector is sent to described processing unit, and then controlling the test that described processing unit carries out described logic function.
2. the method for testing of chip as claimed in claim 1, it is characterized in that, controlled described processing unit to switch in mode of operation and test pattern by blocked operation, comprising: receive the external control signal outside from described chip, and carry out blocked operation according to described external signal.
3. the method for testing of chip as claimed in claim 2, it is characterized in that, described external signal comprises high level signal and low level signal, when described external signal is high level signal, control described processing unit and be in test pattern, when described external signal is low level signal, controls described processing unit and be in mode of operation.
4. a test structure for chip, is characterized in that, comprising:
Be located at the processing unit in chip, there is logic function to be achieved;
Be located at the solidification storage unit in described chip, described solidification memory cell contains the test vector adapting to described logic function; And
Be located at the switching logic unit in described chip, processing unit described in described switching logic unit control linkage and described solidification storage unit, described switching logic unit switches in mode of operation and test pattern for controlling described processing unit; In described test pattern, described switching logic unit reads the test vector in described solidification storage unit, and is sent to described processing unit, and then controls described processing unit and carry out logic function test.
5. the test structure of chip as claimed in claim 4, it is characterized in that, described switching logic unit comprises functional module and test module, described switching logic unit, by switching the duty of described functional module and described test module, realizes controlling described processing unit and switches in mode of operation and test pattern.
6. the test structure of chip as claimed in claim 5, it is characterized in that, also comprise wire jumper circuit board, described wire jumper circuit board is provided with high level end and low level end, described switching logic unit connects high level end on described wire jumper circuit board and low level end by change-over switch, control described switching logic unit by change-over switch and connect described high level end or described low level end, realize the switching of the duty between described functional module in described switching logic unit and described test module.
7. the test structure of chip as claimed in claim 6, it is characterized in that, when described change-over switch connects described high level end, the test module in described switching logic unit is in running order, and then controls described processing unit and be in test pattern; When described change-over switch connects described low level end, the functional module in described switching logic unit is in running order, and then controls described processing unit and be in mode of operation.
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Cited By (10)
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| CN106405373A (en) * | 2016-08-29 | 2017-02-15 | 北京自动测试技术研究所 | Active test vector matching method |
| CN108333497A (en) * | 2017-11-28 | 2018-07-27 | 上海华力微电子有限公司 | A kind of method of chip testing |
| CN109581199A (en) * | 2019-01-22 | 2019-04-05 | 上海艾为电子技术股份有限公司 | Digital volume production test machine, pumping signal acquisition methods and testing data comparative approach |
| CN109901051A (en) * | 2019-03-01 | 2019-06-18 | 马鞍山创久科技股份有限公司 | A kind of chip Dynamic Current Testing system |
| CN111307420A (en) * | 2020-01-23 | 2020-06-19 | 珠海荣邦智能科技有限公司 | Infrared quality testing device and method for infrared transmitting tube product |
| CN112782551A (en) * | 2019-11-04 | 2021-05-11 | 珠海零边界集成电路有限公司 | Chip and test system of chip |
| CN112802538A (en) * | 2021-01-06 | 2021-05-14 | 上海华岭集成电路技术股份有限公司 | Method for increasing vector depth of test machine |
| WO2021179601A1 (en) * | 2020-03-11 | 2021-09-16 | 长鑫存储技术有限公司 | Method for testing control chip and related device |
| CN113567832A (en) * | 2021-07-08 | 2021-10-29 | 北京中电华大电子设计有限责任公司 | Testing device for IO connectivity of circuit board |
| US11862268B2 (en) | 2020-03-11 | 2024-01-02 | Changxin Memory Technologies, Inc. | Test method for control chip and related device |
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| US11862268B2 (en) | 2020-03-11 | 2024-01-02 | Changxin Memory Technologies, Inc. | Test method for control chip and related device |
| US11867758B2 (en) | 2020-03-11 | 2024-01-09 | Changxin Memory Technologies, Inc. | Test method for control chip and related device |
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| CN113567832A (en) * | 2021-07-08 | 2021-10-29 | 北京中电华大电子设计有限责任公司 | Testing device for IO connectivity of circuit board |
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Effective date of registration: 20211115 Address after: 610000 China (Sichuan) pilot Free Trade Zone, Chengdu, Sichuan 301, 302, 401 and 402, building 4, No. 715, north section of Hupan Road, Zhengxing street, Tianfu new area, Chengdu Patentee after: Hualizhi core (Chengdu) integrated circuit Co., Ltd Address before: 201702 room 133, Zone C, floor 1, building 1, No. 1362, Huqingping highway, Qingpu District, Shanghai Patentee before: Shanghai Huali chuangtong Semiconductor Co., Ltd |