CN103928345B - Ion implanting forms the UMOSFET preparation method of N-type heavy doping drift layer table top - Google Patents
Ion implanting forms the UMOSFET preparation method of N-type heavy doping drift layer table top Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The present invention relates to a kind of ion implanting and form the UMOSFET device preparation method of N-type heavy doping drift layer table top, epitaxial growth N-type drift region；Ion implanting forms N+ trap；N+ trap etching is table top；Epitaxial growth P epitaxial layer；Epitaxial growth N+ source region layer；Etching grooving；Etching forms source region；Oxidation forms groove grid；Depositing polysilicon；Opening contact hole: prepare passivation layer, opens electrode contact hole；Prepare electrode: evaporated metal, prepare electrode.The present invention improves the doping content of N-type drift region table top in the carborundum UMOSFET device with N-type drift layer table top by ion implanting and etching technics, reduces the conducting resistance of this device.
Description
Technical field
The present invention relates to microelectronics technology, particularly relate to a kind of ion implanting and form N-type heavy doping
The carborundum UMOSFET device preparation method of drift layer table top.
Background technology
Third generation semi-conducting material carborundum has broad-band gap, high critical breakdown electric field, and high electronics is saturated
Excellent physics and the chemical property such as drift velocity and higher thermal conductivity, in high temperature, high pressure, big merit
In rate semiconductor devices, tool has great advantage.
Power MOSFET is as switch, and its forward conduction resistance and breakdown reverse voltage are that conflict closes
System, and the UMOSFET of vertical structure eliminates parasitic accumulation layer resistance and JFET resistance, so
UMOSFET compares with the MOSFET of transversary in this respect has certain advantage.
UMOSFET self there is also shortcoming, and the electric field concentration effect of its Cao Shan corner causes device to carry
Front puncture, reduce the reliability of device.A kind of can reduce groove grid turning electric field with N-
The SiC UMOSFET device of drift layer table top has been developed, the P-epitaxial layer parcel of this device
Groove grid turnings, instead of the SiO at turning with SiC PN junction interface2/ SiC bears at interface reverse electricity
Pressure, improves the reliability of device.
But owing in the program, P-epitaxial layer has wrapped up groove grid turning, make conductive path become at table top
Narrow, and impurity concentration and the drift layer concentration at table top is equal, and doping content is relatively low, and this is all right
The disadvantageous factor of conducting resistance.
In view of drawbacks described above, creator of the present invention obtains this finally through research for a long time and practice
Creation.
Summary of the invention
It is an object of the invention to provide a kind of ion implanting and form N-type heavy doping drift layer table top
UMOSFET preparation method, in order to overcome above-mentioned technological deficiency.
For achieving the above object, the present invention provides a kind of ion implanting to form N-type heavy doping drift layer platform
The UMOSFET preparation method in face, this detailed process is:
Step a, epitaxial growth N-type drift region: at silicon carbide N+substrate print Epitaxial growth thickness about
Being 12 μm～25 μm, Nitrogen ion doping content is 1 × 1015cm-3～5 × 1015cm-3N-type drift region；
Step b, ion implanting forms N+ trap: carries out ion implanting in N-type drift region, is formed heavily doped
Miscellaneous N+ trap, N+ trap width is 3 μm～4 μm, and implanted dopant is Nitrogen ion, and the degree of depth is 0.5 μm,
Doping content is 1 × 1017cm-3；
Step c, N+ trap etching is for table top: N+ trap is etched into a table top, table surface height and N+ trap
Deep equality, mesa width is equal with the width of trap；
Step d, epitaxial growth P-epitaxial layer: grow in N-type drift region and N+ drift layer table top
Layer P-epitaxial layer, thickness is 3 μm, and Al-doping concentration is 5 × 1017cm-3～1 × 1018cm-3；
Step e, epitaxial growth N+ source region layer: grow one layer of N+ source region layer, thickness on P-epitaxial layer
Being 0.5 μm, doping content is 5 × 1018cm-3；
Step f, etches grooving: use ICP etching to be formed directly over N-type heavy doping drift layer table top
Groove, width is 6 μm, and the degree of depth is 3 μm, and two base angles of such groove are wrapped up by P-epitaxial layer；
Step g, etching forms source region: use ICP etching to form source contact；
Step h, oxidation forms groove grid: by thermal oxidation technology preparation vessel gate medium SiO2, thickness is
100nm。
Step i, depositing polysilicon: the groove gate medium SiO in groove grid2Upper deposit polySi layer；
Step j, opening contact hole: prepare passivation layer, open electrode contact hole；
Step k, prepares electrode: evaporated metal, prepares electrode.
Further, in above-mentioned steps a, first to carry out RCA standard clear for the silicon carbide substrates sheet to N-type
Wash, be then 12 μm～25 μm at whole substrate slice Epitaxial growth thickness, Nitrogen ion doping content
It is 1 × 1015cm-3～5 × 1015cm-3N-drift layer, its process conditions are: temperature is 1600 DEG C, pressure
Power is 100mbar, and reacting gas uses silane and propane, and carrier gas uses pure hydrogen, doped source
Use liquid nitrogen.
Further, the detailed process of above-mentioned steps b is:
Step b01, uses low pressure chemical vapor deposition mode to deposit thick layer at whole silicon carbide
Degree is the SiO of 0.2 μm2, then the Al that deposition thickness is 1 μm is as the barrier layer of N~+ implantation,
Forming N+ trap injection region by photoetching and etching, N+ trap injection region width is 3-4 μm；
Step b02, carries out three N~+ implantation, successively Implantation Energies under the environment temperature of 500 DEG C
Being respectively 520keV, 300keV, 150keV, corresponding dosage is 9.8 × 1011cm-2、7×1011cm-2、
4.9×1011cm-2, injecting the degree of depth is 0.5 μm；
Step b03, silicon carbide is carried out by standard RCA of employing, does the protection of C film after drying.
Then carrying out ion-activated annealing in 1750 DEG C of argon atmospheres, the time is 15min.
Further, in above-mentioned steps c, N+ trap width is 3 μm～4 μm, and implanted dopant is Nitrogen ion,
The degree of depth is 0.5 μm, and doping content is 1 × 1017cm-3, its process conditions are: implantation temperature 500 DEG C,
Ion-activated annealing temperature 1750 DEG C, annealing time 10min.
Further, in above-mentioned steps d, N-type drift region and N+ drift layer table top grow one layer of P-
Epitaxial layer, thickness is 3 μm, and Al-doping concentration is 5 × 1017cm-3～1 × 1018cm-3；N+ trap is carved
Erosion is table top, and the height of table top is equal to N+ trap width, and its process conditions are: ICP coil power 850W,
Source power 100W, reacting gas SF6And O2It is respectively 48sccm and 12sccm.
Further, in above-mentioned steps e, growing a layer thickness on P-epitaxial layer is 0.5 μm, nitrogen
Ion doping concentration is 5 × 1018cm-3N-type silicon carbide epitaxial layers, as N+ source region layer, its technique
Condition is: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas uses silane and propane, carries
Fortune body uses pure hydrogen, and doped source uses liquid nitrogen.
Further, in above-mentioned steps f, first magnetron sputtering one layerTi film as ICP
Etch mask, then gluing photoetching, carry out ICP etching, and the width etching groove is 6 μm, the degree of depth
It is 3 μm, finally removes photoresist, go etch mask, clean into mating plate；Process conditions are: ICP coil merit
Rate 850W, source power 100W, reacting gas SF6And O2It is respectively 48sccm and 12sccm.
Further, in above-mentioned steps g, first magnetron sputtering one layerTi film as ICP
Etch mask, then gluing photoetching, carry out ICP etching, forms source contact hole, finally removes photoresist,
Go etch mask, clean into mating plate；Process conditions are: ICP coil power 850W, source power 100W,
Reacting gas SF6And O2It is respectively 48sccm and 12sccm.
Further, in above-mentioned steps h, dry oxygen technique is used to prepare SiO at 1150 DEG C2Grid are thick
Degree is 100nm, then at 1050 DEG C, N2Anneal under atmosphere, reduce SiO2Film surface thick
Rugosity.
Further, in above-mentioned steps i, use low pressure hot wall chemical vapor deposition method growth ploySi
Filling up groove, deposition temperature is 600～650 DEG C, and deposit pressure is 60～80Pa, and reacting gas is silicon
Alkane and hydrogen phosphide, carrier gas is helium, then gluing photoetching, etches ploySi layer, forms polycrystalline
Si-gate, finally removes photoresist, and cleans.
The beneficial effects of the present invention is compared with prior art: the present invention passes through ion implanting and quarter
Etching technique improves the N-type drift region in the carborundum UMOSFET device with N-type drift layer table top
The doping content of table top, reduces the conducting resistance of this device；Ion implantation technology can be controlled accurately
System injects concentration and the degree of depth of ion, and for matrix material, ion implanting does not has obvious boundary
, the most there is not adhesion and crack and flake off problem in face, and ion implanting not waste material cost-effective.
Accompanying drawing explanation
Fig. 1 is the present invention structural representation with the carborundum UMOSFET device of N-type drift layer table top
Figure；
Fig. 2 is the present invention manufacture craft with the carborundum UMOSFET device of N-type drift layer table top
Flow chart.
Detailed description of the invention
Below in conjunction with accompanying drawing, to the present invention, above-mentioned and other technical characteristic and advantage are made more detailed
Explanation.
Referring to shown in Fig. 2, it is the present invention carborundum UMOSFET with N-type drift layer table top
The structural representation of device, this detailed process is:
Step a, epitaxial growth N-type drift region: at silicon carbide N+substrate print Epitaxial growth thickness about
Being 12 μm～25 μm, Nitrogen ion doping content is 1 × 1015cm-3～5 × 1015cm-3N-type drift region；
Step b, ion implanting forms N+ trap: carries out ion implanting in N-type drift region, is formed heavily doped
Miscellaneous N+ trap, N+ trap width is 3 μm～4 μm, and implanted dopant is Nitrogen ion, and the degree of depth is 0.5 μm,
Doping content is 1 × 1017cm-3；
Step c, N+ trap etching is for table top: N+ trap is etched into a table top, table surface height and N+ trap
Deep equality, N+ trap width is 3 μm～4 μm, and implanted dopant is Nitrogen ion, and the degree of depth is 0.5 μm,
Doping content is 1 × 1017cm-3, its process conditions are: implantation temperature 500 DEG C, ion-activated annealing
Temperature 1750 DEG C, annealing time 10min.
Step d, epitaxial growth P-epitaxial layer: grow in N-type drift region and N+ drift layer table top
Layer P-epitaxial layer, thickness is 3 μm, and Al-doping concentration is 5 × 1017cm-3～1 × 1018cm-3；N+
Trap etching is table top, and the height of table top is equal to N+ trap width, and its process conditions are: ICP coil power
850W, source power 100W, reacting gas SF6And O2It is respectively 48sccm and 12sccm.
Step e, epitaxial growth N+ source region layer: grow one layer of N+ source region layer, thickness on P-epitaxial layer
Being 0.5 μm, doping content is 5 × 1018cm-3；
Step f, etches grooving: use ICP etching to be formed directly over N-type heavy doping drift layer table top
Groove, width is 6 μm, and the degree of depth is 3 μm, and two base angles of such groove are wrapped up by P-epitaxial layer；
Step g, etching forms source region: use ICP etching to form source contact；
Step h, oxidation forms groove grid: by thermal oxidation technology preparation vessel gate medium SiO2, thickness is
100nm。
Step i, depositing polysilicon: the groove gate medium SiO in groove grid2Upper deposit polySi layer；
Step j, opening contact hole: prepare passivation layer, open electrode contact hole；
Step k, prepares electrode: evaporated metal, prepares electrode.
Each embodiment based on above-mentioned steps, as described below:
Embodiment one:
Step a1, epitaxial growth N-type drift region, as shown in a in Fig. 2；
First the silicon carbide substrates sheet to N-type carries out RCA standard cleaning, then on whole substrate slice outside
Epitaxial growth thickness is 12 μm, and Nitrogen ion doping content is 1 × 1015cm-3N-drift layer, its technique
Condition is: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas uses silane and propane, carries
Fortune body uses pure hydrogen, and doped source uses liquid nitrogen.
Step b1, ion implanting forms N+ trap, as shown in the b in Fig. 2；
Step b11, uses low pressure chemical vapor deposition mode to deposit thick layer at whole silicon carbide
Degree is the SiO of 0.2 μm2, then the Al that deposition thickness is 1 μm is as the barrier layer of N~+ implantation,
Forming N+ trap injection region by photoetching and etching, N+ trap injection region width is 3 μm；
Step b12, carries out three N~+ implantation, successively Implantation Energies under the environment temperature of 500 DEG C
Being respectively 520keV, 300keV, 150keV, corresponding dosage is 9.8 × 1011cm-2、7×1011cm-2、
4.9×1011cm-2, injecting the degree of depth is 0.5 μm；
Step b13, silicon carbide is carried out by standard RCA of employing, does the protection of C film after drying.
Then carrying out ion-activated annealing in 1750 DEG C of argon atmospheres, the time is 15min.
Step c1, N+ trap etching is table top, as shown in the c in Fig. 2；
First magnetron sputtering one layerTi film as ICP etch mask, then gluing photoetching,
Carrying out ICP etching, N+ trap is etched into mesa structure, table surface height is equal to N+ well depth.Finally go
Glue, goes etch mask, cleans into mating plate.ICP etch technological condition is: ICP coil power 850W,
Source power 100W, reacting gas SF6And O2It is respectively 48sccm and 12sccm.
Step d1, epitaxial growth P-epitaxial layer, as shown in the d in Fig. 2；
Growing a layer thickness in N-type drift region and heavily doped drift region mesa is 3 μm, aluminium ion
Doping content is 5 × 1017cm-3P-epitaxial layer, its epitaxial growth technology condition is: temperature is 1600
DEG C, pressure is 100mbar, and reacting gas uses silane and propane, and carrier gas uses pure hydrogen,
Doped source uses trimethyl aluminium.
Step e1, epitaxial growth N+ source region layer, as shown in the e in Fig. 2；
Growing a layer thickness on P-epitaxial layer is 0.5 μm, and Nitrogen ion doping content is 5 × 1018cm-3
N-type silicon carbide epitaxial layers, as N+ source region layer, its process conditions are: temperature is 1600 DEG C, pressure
Power is 100mbar, and reacting gas uses silane and propane, and carrier gas uses pure hydrogen, doped source
Use liquid nitrogen.
Step f1, etches grooving, as shown in the f in Fig. 2；
First magnetron sputtering one layerTi film as ICP etch mask, then gluing photoetching,
Carrying out ICP etching, the width etching groove is 6 μm, and the degree of depth is 3 μm, finally removes photoresist, and goes etching
Mask, cleans into mating plate.Process conditions are: ICP coil power 850W, source power 100W, reaction
Gas SF6And O2It is respectively 48sccm and 12sccm.
Step g1, etching forms source region, as shown in the g in Fig. 2；
First magnetron sputtering one layerTi film as ICP etch mask, then gluing photoetching,
Carry out ICP etching, form source contact hole, finally remove photoresist, go etch mask, clean into mating plate.
Process conditions are: ICP coil power 850W, source power 100W, reacting gas SF6And O2It is respectively
48sccm and 12sccm.
Step h1, oxidation forms groove grid, as shown in the h in Fig. 2；
Dry oxygen technique is used to prepare SiO at 1150 DEG C2Grid, thickness is 100nm, then 1050
DEG C, N2Anneal under atmosphere, reduce SiO2The roughness of film surface.
Step i1, depositing polysilicon, as shown in the i in Fig. 2；
Using low pressure hot wall chemical vapor deposition method growth ploySi to fill up groove, deposition temperature is
600～650 DEG C, deposit pressure is 60～80Pa, and reacting gas is silane and hydrogen phosphide, and carrier gas is
Helium, then gluing photoetching, etch ploySi layer, forms polysilicon gate, finally removes photoresist, and cleans.
Step j1, opening contact hole, as shown in the j in Fig. 2；
At device surface one layer of field oxygen of deposit or Si3N4Layer, then gluing photoetching, corrosion and passivation layer is opened
Electrode contact hole, finally removes photoresist, and cleans.
Step k1, prepares electrode, as shown in the k in Fig. 2；
Electron beam evaporation Ti/Ni/Au makes front grid, source electrode, then gluing photoetching, metal erosion
Form front grid, source electrode contact pattern, remove photoresist, clean.
Electron beam evaporation Ti/Ni/Au makes back side drain electrode overleaf, then makes front grid, source electricity
Pole, encloses short annealing 3min the most in an ar atmosphere, and temperature is 1050 DEG C.
Embodiment two:
Step a2, epitaxial growth N-type drift region；
First the silicon carbide substrates sheet to N-type carries out RCA standard cleaning, then on whole substrate slice outside
Epitaxial growth thickness is 25 μm, and Nitrogen ion doping content is 5 × 1015cm-3N-drift layer, its technique
Condition is: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas uses silane and propane, carries
Fortune body uses pure hydrogen, and doped source uses liquid nitrogen.
Step b2, ion implanting forms N+ trap；
Step b21, uses low pressure chemical vapor deposition mode to deposit thick layer at whole silicon carbide
Degree is the SiO of 0.2 μm2, then the A1 that deposition thickness is 1 μm is as the barrier layer of N~+ implantation,
Forming N+ trap injection region by photoetching and etching, N+ trap injection region width is 4 μm；
Step b22, carries out three N~+ implantation, successively Implantation Energies under the environment temperature of 500 DEG C
Being respectively 520keV, 300keV, 150keV, corresponding dosage is 9.8 × 1011cm-2、7×1011cm-2、
4.9×1011cm-2, injecting the degree of depth is 0.5 μm；
Step b23, silicon carbide is carried out by standard RCA of employing, does the protection of C film after drying.
Then carrying out ion-activated annealing in 1750 DEG C of argon atmospheres, the time is 15min.
Step c2 is identical with step c1 of embodiment one；
Step d2, epitaxial growth P-epitaxial layer；
Growing a layer thickness in N-type drift region and heavily doped drift region mesa is 3 μm, aluminium ion
Doping content is 1 × 1018cm-3P-epitaxial layer, its epitaxial growth technology condition is: temperature is 1600
DEG C, pressure is 100mbar, and reacting gas uses silane and propane, and carrier gas uses pure hydrogen,
Doped source uses trimethyl aluminium.
Step e2 is identical with step e1 of embodiment one.
Step f2 is identical with step f1 of embodiment one.
Step g2 is identical with step g1 of embodiment one.
Step h2 is identical with step h1 of embodiment one.
Step i2 is identical with step i1 of embodiment one.
Step j2 is identical with step j1 of embodiment one.
Step k2 is identical with step k1 of embodiment one.
Embodiment three:
Step a3, epitaxial growth N-type drift region；
First the silicon carbide substrates sheet to N-type carries out RCA standard cleaning, then on whole substrate slice outside
Epitaxial growth thickness is 20 μm, and Nitrogen ion doping content is 3 × 1015cm-3N-drift layer, its technique
Condition is: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas uses silane and propane, carries
Fortune body uses pure hydrogen, and doped source uses liquid nitrogen.
Step b3, ion implanting forms N+ trap；
Step b31, uses low pressure chemical vapor deposition mode to deposit thick layer at whole silicon carbide
Degree is the SiO of 0.2 μm2, then the Al that deposition thickness is 1 μm is as the barrier layer of N~+ implantation,
Forming N+ trap injection region by photoetching and etching, N+ trap injection region width is 3.5 μm.
Step b32, carries out three N~+ implantation, successively Implantation Energies under the environment temperature of 500 DEG C
Being respectively 520keV, 300keV, 150keV, corresponding dosage is 9.8 × 1011cm-2、7×1011cm-2、
4.9×1011cm-2, injecting the degree of depth is 0.5 μm；
Step b33, silicon carbide is carried out by standard RCA of employing, does the protection of C film after drying.
Then carrying out ion-activated annealing in 1750 DEG C of argon atmospheres, the time is 15min.
Step c3 is identical with step c1 of embodiment one.
Step d3, epitaxial growth P-epitaxial layer；
Growing a layer thickness in N-type drift region and heavily doped drift region mesa is 3 μm, aluminium ion
Doping content is 8 × 1017cm-3P-epitaxial layer, its epitaxial growth technology condition is: temperature is 1600
DEG C, pressure is 100mbar, and reacting gas uses silane and propane, and carrier gas uses pure hydrogen,
Doped source uses trimethyl aluminium.
Step e3 is identical with step e1 of embodiment one.
Step f3 is identical with step f1 of embodiment one.
Step g3 is identical with step g1 of embodiment one.
Step h3 is identical with step h1 of embodiment one.
Step i3 is identical with step i1 of embodiment one.
Step j3 is identical with step j1 of embodiment one.
Step k3 is identical with step k1 of embodiment one.
The foregoing is only presently preferred embodiments of the present invention, be merely illustrative for invention, and
Nonrestrictive.Those skilled in the art understands, in the spirit and scope that invention claim is limited
In it can be carried out many changes, amendment, even equivalence, but fall within protection scope of the present invention
In.
Claims (10)
1. ion implanting forms a UMOSFET preparation method for N-type heavy doping drift layer table top, its
Being characterised by, this detailed process is:
Step a, epitaxial growth N-type drift region: be at silicon carbide N+substrate print Epitaxial growth thickness
12 μm～25 μm, Nitrogen ion doping content is 1 × 1015cm-3～5 × 1015cm-3N-type drift region；
Step b, ion implanting forms N+ trap: carries out ion implanting in N-type drift region, is formed heavily doped
Miscellaneous N+ trap, N+ trap width is 3 μm～4 μm, and implanted dopant is Nitrogen ion, and the degree of depth is 0.5 μm,
Doping content is 1 × 1017cm-3；
Step c, N+ trap etching is for table top: N+ trap is etched into a table top, table surface height and N+ trap
Deep equality, mesa width is equal with the width of trap；
Step d, epitaxial growth P-epitaxial layer: grow in N-type drift region and N+ drift layer table top
Layer P-epitaxial layer, thickness is 3 μm, and Al-doping concentration is 5 × 1017cm-3～1 × 1018cm-3；
Step e, epitaxial growth N+ source region layer: grow one layer of N+ source region layer, thickness on P-epitaxial layer
Being 0.5 μm, doping content is 5 × 1018cm-3；
Step f, etches grooving: use ICP etching to be formed directly over N-type heavy doping drift layer table top
Groove, width is 6 μm, and the degree of depth is 3 μm, and two base angles of such groove are wrapped up by P-epitaxial layer；
Step g, etching forms source region: use ICP etching to form source contact；
Step h, oxidation forms groove grid: by thermal oxidation technology preparation vessel gate medium SiO2, thickness is
100nm；
Step i, depositing polysilicon: the groove gate medium SiO in groove grid2Upper deposit polySi layer；
Step j, opening contact hole: prepare passivation layer, open electrode contact hole；
Step k, prepares electrode: evaporated metal, prepares electrode.
Ion implanting the most according to claim 1 forms N-type heavy doping drift layer table top
UMOSFET preparation method, it is characterised in that in above-mentioned steps a, first serves as a contrast the carborundum of N-type
Egative film carries out RCA standard cleaning, is then 12 μm～25 μ at whole substrate slice Epitaxial growth thickness
M, Nitrogen ion doping content is 1 × 1015cm-3～5 × 1015cm-3N-drift layer, its process conditions are:
Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas uses silane and propane, and carrier gas is adopted
With pure hydrogen, doped source uses liquid nitrogen.
Ion implanting the most according to claim 1 and 2 forms N-type heavy doping drift layer table top
UMOSFET preparation method, it is characterised in that the detailed process of above-mentioned steps b is:
Step b01, uses low pressure chemical vapor deposition mode to deposit thick layer at whole silicon carbide
Degree is the SiO of 0.2 μm2, then the Al that deposition thickness is 1 μm is as the barrier layer of N~+ implantation,
Forming N+ trap injection region by photoetching and etching, N+ trap injection region width is 3-4 μm；
Step b02, carries out three N~+ implantation, successively Implantation Energies under the environment temperature of 500 DEG C
Being respectively 520keV, 300keV, 150keV, corresponding dosage is 9.8 × 1011cm-2、7×1011cm-2、
4.9×1011cm-2, injecting the degree of depth is 0.5 μm；
Step b03, silicon carbide is carried out by standard RCA of employing, does the protection of C film after drying,
Then carrying out ion-activated annealing in 1750 DEG C of argon atmospheres, the time is 15min.
Ion implanting the most according to claim 3 forms N-type heavy doping drift layer table top
UMOSFET preparation method, it is characterised in that in above-mentioned steps c, N+ trap width is 3 μm～4 μm,
Implanted dopant is Nitrogen ion, and the degree of depth is 0.5 μm, and doping content is 1 × 1017cm-3, its process conditions
For: implantation temperature 500 DEG C, ion-activated annealing temperature 1750 DEG C, annealing time 10min.
Ion implanting the most according to claim 3 forms N-type heavy doping drift layer table top
UMOSFET preparation method, it is characterised in that in above-mentioned steps d, drifts about in N-type drift region and N+
Growing one layer of P-epitaxial layer on layer table top, thickness is 3 μm, and Al-doping concentration is 5 × 1017cm-3～1
×1018cm-3；N+ trap etching is table top, and the height of table top is equal to N+ trap width, and its process conditions are:
ICP coil power 850W, source power 100W, reacting gas SF6And O2Be respectively 48sccm and
12sccm。
Ion implanting the most according to claim 3 forms N-type heavy doping drift layer table top
UMOSFET preparation method, it is characterised in that in above-mentioned steps e, grows one on P-epitaxial layer
Layer thickness is 0.5 μm, and Nitrogen ion doping content is 5 × 1018cm-3N-type silicon carbide epitaxial layers, make
For N+ source region layer, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar, reacting gas
Using silane and propane, carrier gas uses pure hydrogen, and doped source uses liquid nitrogen.
Ion implanting the most according to claim 6 forms N-type heavy doping drift layer table top
UMOSFET preparation method, it is characterised in that in above-mentioned steps f, first magnetron sputtering one layer
Ti film as ICP etch mask, then gluing photoetching, carry out ICP etching, etch the width of groove
Degree is 6 μm, and the degree of depth is 3 μm, finally removes photoresist, goes etch mask, cleans into mating plate；Process conditions
For: ICP coil power 850W, source power 100W, reacting gas SF6And O2It is respectively 48sccm
And 12sccm.
Ion implanting the most according to claim 6 forms N-type heavy doping drift layer table top
UMOSFET preparation method, it is characterised in that in above-mentioned steps g, first magnetron sputtering one layer
Ti film as ICP etch mask, then gluing photoetching, carry out ICP etching, form source contact
Hole, finally removes photoresist, and goes etch mask, cleans into mating plate；Process conditions are: ICP coil power 850W,
Source power 100W, reacting gas SF6And O2It is respectively 48sccm and 12sccm.
Ion implanting the most according to claim 8 forms N-type heavy doping drift layer table top
UMOSFET preparation method, it is characterised in that in above-mentioned steps h, uses dry oxygen technique 1150
SiO is prepared at DEG C2Grid, thickness is 100nm, then at 1050 DEG C, N2Anneal under atmosphere, fall
Low SiO2The roughness of film surface.
Ion implanting the most according to claim 8 forms N-type heavy doping drift layer table top
UMOSFET preparation method, it is characterised in that in above-mentioned steps i, uses low pressure hot wall chemical vapour
Phase sedimentation growth ploySi fills up groove, and deposition temperature is 600～650 DEG C, and deposit pressure is
60～80Pa, reacting gas is silane and hydrogen phosphide, and carrier gas is helium, then gluing photoetching, carves
Erosion ploySi layer, forms polysilicon gate, finally removes photoresist, and cleans.
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