CN104280651A - TEST SYSTEM AND semiconductor DEVICE - Google Patents
TEST SYSTEM AND semiconductor DEVICE Download PDFInfo
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- CN104280651A CN104280651A CN201410327047.9A CN201410327047A CN104280651A CN 104280651 A CN104280651 A CN 104280651A CN 201410327047 A CN201410327047 A CN 201410327047A CN 104280651 A CN104280651 A CN 104280651A
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Abstract
An aspect of the present invention is to provide a test system for detecting whether a continuity fault condition, e.g., a short or open condition, exists in the path between a tester and chips on a wafer during a wafer level burn-in testing. According to one embodiment of the present invention, the test system comprises a probe card and n chips. The probe card comprises m first signal contacts for receiving m test signals from the tester, n second signal contacts for providing n test results to the tester, and a contact array. The probe card is in contact with the chips on the wafer through a plurality of needles. In this manner, the test system can detect whether the continuity fault condition exists in the path between the tester and the chips on the wafer during the wafer level burn-in testing.
Description
Technical field
The present invention relates to a kind of test macro and a kind of semiconductor element being executed in this test macro.
Background technology
In traditional integrated circuit (Integrated Circuit, IC) manufacture process, the IC of multiple dispersion can be formed on semiconductor wafer (wafer) with the form of wafer (chip) or crystal grain (dice).After manufacture process completes, this wafer can cut to be separated into independently wafer.Each wafer is then packaged in module or is incorporated in larger system.
Due to the inborn flaw of wafer, or the defect of single or multiple step in manufacture process, the wafer after some encapsulation possibly cannot operate according to desired design.These defects may manifest in early days or just can may show after wafer operates a period of time.In order to identify the wafer of these defects, one burned (burn-in) step can be executed on wafer.In burned step, wafer can be heated to a high temperature, and a test controller meeting is static or dynamically apply on one group of bias voltage to selected wafer to make selected wafer have electric current to flow through.After burned step, wafer can experience a Wafer probe (Chip Probe, CP) testing procedure to filter out the wafer of defect before packaging.
In traditional wafer scale (wafer level) burned step, wafer only receives one group of bias voltage, and can not returned data to test controller.Therefore, this controller cannot confirm whether burned step positively performs.For example, the state of short circuit or open circuit may be had between controller and wafer to occur, make bias voltage to be sent to wafer.Therefore, burned step does not have actual completing, and controller may judge the wafer of defect by accident in follow-up CP testing procedure.
Summary of the invention
An object of the present invention is to provide a kind of test macro, in order to perform the burned test of a wafer scale.
According to one embodiment of the invention, this test macro comprises a probe and n wafer.Each probe comprises m the first signal contact, n secondary signal contact and a crosspoint array.These m the first signal contacts are in order to receive m test signal of m the first test channel from a tester table, and m is a positive integer.These n secondary signal contacts, in order to provide n test result to n the second test channel of this tester table, n is a positive integer.This crosspoint array comprises (m+1) individual row and n row, every a line has n contact and each row has (m+1) individual contact, wherein, each of n contact in a first row is electrically connected to one corresponding in n secondary signal contact, and each of n contact in one i-th row is electrically connected to one corresponding in m the first signal contact, wherein i is positive integer, and 2≤i≤(m+1).
Another object of the present invention is to provide a kind of semiconductor element, in order to perform an associativity test.
According to one embodiment of the invention, this semiconductor element comprises m input pad, a testing circuit and an inspection pad.Each in these m input pad receives from one corresponding in m test signal of an outside board.This testing circuit outputs signal to produce one in this inspection pad in order to the input signal received from this m input pad.This inspection pad outputs signal to this tester table in order to provide this.
Accompanying drawing explanation
Fig. 1 display is in conjunction with the calcspar of the test macro in order to perform the burned test of a wafer scale of one embodiment of the invention
Fig. 2 display is in conjunction with the planar configuration of the probe of one embodiment of the invention.
Fig. 3 display is in conjunction with the running of this test macro when associativity is tested of one embodiment of the invention.
Fig. 4 display is in conjunction with the circuit diagram of the testing circuit of the wafer of one embodiment of the invention.
Fig. 5 shows sequential chart during this testing circuit running in Fig. 4.
Fig. 6 shows the running of this test macro when associativity is tested.
Fig. 7 shows the running of this test macro when associativity is tested.
Fig. 8 shows the running of this test macro when associativity is tested.
Fig. 9 display is in conjunction with the planar configuration of the probe of another embodiment of the present invention.
Figure 10 display is in conjunction with the part circuit diagram of this wafer of one embodiment of the invention.
Figure 11 shows the sequential chart during enable circuit running of Figure 10.
Embodiment
The present invention discloses a test macro to perform the burned test of a wafer scale (wafer level burn-in test) at this." the burned test of wafer scale " herein refer to wafer can wafer scale state carry out an associativity (continuity) test, then carry out a burned step, finally by a CP testing procedure to filter out defective wafer before packaging.
Fig. 1 display is in conjunction with the calcspar of the test macro 100 in order to perform the burned test of a wafer scale of one embodiment of the invention.As shown in Figure 1, this test macro 100 comprises a Test System Controller 10, and it can be an automatic testing equipment (Automatic Test Equipment, ATE) or a general-use computing machine.This Test System Controller 10 is connected to a measuring head (test head) 14 via a winding displacement of communication 12.
This measuring head 14 may comprise a pedestal 16, connects a probe (probe card) 18 whereby.This probe 18 is as the interface between this measuring head 14 and a wafer 22 to be measured.This probe 18 can contact via the multiple probes 20 be integrated in this probe 18 and this wafer 22 to be measured.
This test macro 100 also comprises a stage 24 to place this wafer 22 to be measured.As shown in Figure 2, this probe 18 comprises multiple pad 18_1 to 18_7.These pads 18_1 to 18_7 is configured to receive the test signal from this Test System Controller 10 of Fig. 1, and passes test result back to this Test System Controller 10.This probe 18 also comprises a crosspoint array 19, and it walks crosswise ROW1 by multiple, ROW2, ROW3, ROW4, and ROW5 and multiple COL1, COL2 in upright arrangement, and COL3 formed.As shown in Figure 2, every a line is made up of three contacts, and each row is made up of five contacts.Contact 19_1 to 19_15 in this crosspoint array 19 is configured to transmit test signal to the wafer 30,32 on the wafer 22 of Fig. 1, and 34, and pass test result back by probe 20 corresponding in Fig. 1.
As shown in Figure 1, in an embodiment of the present invention, before burned step starts, this Test System Controller 10 transmits an instruction to this measuring head 14 to perform an associativity (continuity) test.The test of this associativity determines whether have malfunction to occur between this measuring head 14 and this wafer 22 to be measured.For example, a probe 20 may damage, cause cannot be corresponding on connecting wafer pad; Or the pad on wafer may be short-circuited to a power lead or ground wire.When a short circuit or an open loop state betide on data transfer path, this Test System Controller 10 cannot transmit correct bias voltage to wafer to be measured, also effectively cannot receive test result.Therefore, this associativity test can perform to guarantee to occur without short circuit or open loop state when initial.
Fig. 3 display is in conjunction with this test macro 100 running when associativity is tested of one embodiment of the invention.As shown in Figure 3, this measuring head 14 comprises one group of channel C H1 to CH4, and each passage is responsible for transmitting pad corresponding in data to this probe 18.Illustrate more specifically, this channel C H1 produces the first test signal to the pad 18_1 in this probe 18; This channel C H2 produces the second test signal to the pad 18_2 in this probe 18; This channel C H3 produces the 3rd test signal to the pad 18_3 in this probe 18; And this channel C H4 produces the 4th test signal to the pad 18_4 in this probe 18.
As shown in Figure 3, due to the contact 19_4 in this crosspoint array 19,19_5, and 19_6 is electrically connected to each other via a cabling 191, and the first test signal from this channel C H1 can be sent to contact 19_4,19_5 simultaneously, and 19_6.Similarly, the second test signal from this channel C H2 can be sent to contact 19_7,19_8 simultaneously, and 19_9; The 3rd test signal from this channel C H3 can be sent to contact 19_10,19_11 simultaneously, and 19_12; And simultaneously can be sent to contact 19_13 from the 4th test signal of this channel C H4,19_14, and 19_15.
As shown in Figure 1, this probe 18 be positioned at above this wafer 22 can contact via the multiple probes 20 be integrated in this probe 18 and this wafer 22 to be measured.The configuration pad that these probes 20 are configured to each wafer on wafer 22 to be measured with this contacts.Specifically, as shown in Figure 3, the contact 19_4 of the row COL1 in this crosspoint array 19,19_7,19_10, and 19_13 is via the pad 30_1 on probe corresponding in Fig. 1 and wafer 30,30_2,30_3, and 30_4 is electrically connected; The contact 19_5 of row COL2,19_8,19_11, and 19_14 is via the pad 32_1 on probe corresponding in Fig. 1 and wafer 32,32_2,32_3, and 32_4 is electrically connected; The contact 19_6 of row COL3,19_9,19_12, and 19_15 is via the pad 34_1 on probe corresponding in Fig. 1 and wafer 34,34_2,34_3, and 34_4 is electrically connected.
Referring to Fig. 1 to Fig. 3, this running of test macro 100 when associativity is tested is described.First, this test macro 100 produces parallel test signal to the channel C H1 to CH4 in this measuring head 14 via this winding displacement of communication 12.This probe 18, after receiving the test signal from this measuring head 14, transmits these signals to the wafer 30,32 on this wafer 22 to be measured, and 34.After the test signal of these wafer receipt from this probe 18, operate according to these signals.Under this framework, the pad 30_1 of this wafer 30, the pad 32_1 of this wafer 32, and the pad 34_1 of this wafer 34 can receive the test signal from this channel C H1 simultaneously; The pad 30_2 of this wafer 30, the pad 32_2 of this wafer 32, and the pad 34_2 of this wafer 34 can receive the test signal from this channel C H2 simultaneously; The pad 30_3 of this wafer 30, the pad 32_3 of this wafer 32, and the pad 34_3 of this wafer 34 can receive the test signal from this channel C H3 simultaneously; The pad 30_4 of this wafer 30, the pad 32_4 of this wafer 32, and the pad 34_4 of this wafer 34 can receive the test signal from this channel C H4 simultaneously.
After receiving the test signal from this probe 18, whether a testing circuit can use to detect an associativity disabled status, and such as open circuit or a short-circuit state, betides the transmission path between this measuring head 14 and this wafer 22 to be measured.Fig. 4 shows the testing circuit 301 in conjunction with the wafer 30 of one embodiment of the invention, the testing circuit 321 of wafer 32, and the circuit diagram of the testing circuit 341 of wafer 34.As shown in Figure 4, the testing circuit 301 of this wafer 30 comprises logical circuit 302, PMOS transistor M1, and a nmos pass transistor M2.In the present embodiment, this logical circuit 302 by an AND circuit X1, a phase inverter X2, a NAND gate circuit X3, and an OR-NOT circuit X4 formed.This testing circuit 321 of this wafer 32 is identical with the testing circuit 321 of this wafer 32 with the circuit structure of this testing circuit 341 of this wafer 34, therefore the details of circuit will repeat no more.
As shown in Figure 4, this testing circuit 301 of this wafer 30 is by these pads 30_1,30_2,30_3, and 30_4 receives these signals L1, L2, L3, and after L4, can produce a testing result L5 at remaining pad 30_5.In like manner, this testing circuit 321 of this wafer 32 is by these pads 32_1,32_2,32_3, and 32_4 receives these signals L1, L2, L3, and after L4, can produce a testing result at remaining pad 32_5; This testing circuit 341 of this wafer 34 is by these pads 34_1,34_2,34_3, and 34_4 receives these signals L1, L2, L3, and after L4, can produce a testing result at remaining pad 34_5.
Sequential chart when Fig. 5 this testing circuit 301 shown in Fig. 4 operates.As shown in Figure 5, before time t1, this test signal L1 is positioned at a logical zero level.When signal L1 is positioned at logical zero level, the PMOS transistor M1 in Fig. 4 and nmos pass transistor M2 ends, and makes the signal on this pad 30_5 be suspension joint signal.After time t1, a signal in input signal L2 to L4, is once only had to change its logic level.For example, input signal L2 to L4 is all positioned at logical one level between times ti and ta.Then, input signal L2 can be converted to logical zero level between moments t 2 and t 3, and other signals L3 and L4 remains unchanged.This testing circuit 301 can provide this output signal L5 according to the Different Logic level of input signal L2 to L4.The truth table of this testing circuit 301 is as follows:
Table 1
| L1 | L2 | L3 | L4 | L5 |
| 0 | X | X | X | Hi-Z |
| 1 | 1 | 1 | 1 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 |
By the operation result of table 1, whether this testing circuit 301 can detect has an open circuit or short-circuit state to betide transmission path between this measuring head 14 and this wafer 22 to be measured.For example, when input signal L2 is converted to logical zero level, and when other signals L3 and L4 remains unchanged, the operation result output signal L5 according to table 1 can at logical zero level.Therefore, if the signal that testing circuit 301 produces is positioned at logical one level, but not during logical zero level, represent that the pad 30_2 of this testing circuit 301 may be short-circuited to a power lead, and the signal of pad 30_2 is pulled to logical one level.
As shown in Figure 6, when testing result results from pad 30_5,32_5, and after 34_5, these signals can be sent to the contact 19_1 in the same a line ROW1 in this crosspoint array 19 via the probe in Fig. 1,19_2, and 19_3.Due to these contacts 19_1,19_2, and 19_3 can be electrically connected to individually these pads 18_5,18_6 via cabling, and 18_7.These contacts 19_1,19_2, and the signal on 19_3 can be sent to these pads 18_5,18_6, and 18_7, to the channel C H5 on measuring head 14, CH6, and CH7.Mode according to this, this Test System Controller 10 in Fig. 1 can receive from wafer 30,32 via this measuring head 14 and this winding displacement of communication 12, and the test result of 34.By these test results of analysis, whether this Test System Controller 10 can be learnt just like an associativity disabled status, and such as open circuit or a short-circuit state, betides the transmission path between this measuring head 14 and this wafer 22 to be measured.
For example, as shown in Figure 7, an associativity disabled status results from this wafer 32.In this example, this pad 32_2 in this wafer 32 is short-circuited to a power lead (not illustrating).As shown in Figure 7, at associativity test period, this channel C H1 transmits this first test signal being positioned at logical one level, this channel C H2 transmits this second test signal being positioned at logical zero level, this channel C H3 transmits the 3rd test signal being positioned at logical one level, and this channel C H4 transmits the 4th test signal being positioned at logical one level.Then, this first test signal can via pad 19_4,19_5, and 19_6, corresponding probe, is sent to the pad 30_1 of this wafer 30, the pad 32_1 of this wafer 32, and the pad 34_1 of this wafer 34.According to similar fashion, other test signal can be sent to this wafer 30, this wafer 32, and the correspondence pad of this wafer 34.Therefore, if produce without associativity disabled status, testing circuit 321 meeting output logic 0 level as shown in the truth table of table 1 of this wafer 32.
But in this example because pad 32_2 is short-circuited to this power lead, therefore the signal that testing circuit 321 receives at pad 32_2 is logical one level.Therefore, as shown in Figure 8, this testing circuit 321 can produce the output signal of logical one level at pad 32_5.At pad 30_5,32_5, and the output signal that 34_5 produces then can be sent to corresponding probe, this probe 18, the channel C H5 of this measuring head 14, CH6, and CH7, final this Test System Controller 10 of arrival.Because the output signal padding 32_5 is different from the result that this Test System Controller 10 is predicted, this Test System Controller 10 can learn that an associativity disabled status betides the transmission path between this channel C H2 and this wafer 32.
According to above described function mode, whether this Test System Controller 10 can detect by the logic level of one of them changed in first, second, third and fourth test signal has associativity disabled status to occur.When one of them in first, second, third and fourth test signal has logic level change, three test results can be obtained.Each test result represents wafer 30,32, and whether the configuration pad of 34 receives test signal really.In other words, when this Test System Controller 10 is via channel C H1, CH2, CH3, produce four parallel test signals to wafer 30,32 with CH4, and 34 configuration pad time, have 12 test results via channel C H5, CH6, and CH7 returns to this Test System Controller 10.
As shown in Figure 7 and Figure 8, in 12 test results, wherein four represent whether have one or more associativity disabled status to betide transmission path between the pad 30_1 of this channel C H1 and this wafer 30, transmission path between the pad 30_2 occurring in this channel C H2 and this wafer 30, transmission path between the pad 30_3 occurring in this channel C H3 and this wafer 30, and the transmission path between the pad 30_4 occurring in this channel C H4 and this wafer 30; Wherein four represent whether have one or more associativity disabled status to betide transmission path between the pad 32_1 of this channel C H1 and this wafer 32, transmission path between the pad 32_2 occurring in this channel C H2 and this wafer 32, transmission path between the pad 32_3 occurring in this channel C H3 and this wafer 32, and the transmission path between the pad 32_4 occurring in this channel C H4 and this wafer 32; Remaining four represent whether have one or more associativity disabled status to betide transmission path between the pad 34_1 of this channel C H1 and this wafer 34, transmission path between the pad 34_2 occurring in this channel C H2 and this wafer 34, transmission path between the pad 34_3 occurring in this channel C H3 and this wafer 34, and the transmission path between the pad 34_4 occurring in this channel C H4 and this wafer 34.
As shown in Figure 3, the contact 19_4 in this crosspoint array 19,19_5, and 19_6 is electrically connected to each other via this electrical cabling 191.Because the contact of going together mutually is connected to each other, noise may be coupled mutually.In order to promote vulnerability to jamming, resistance can be arranged to adjacent contact.Fig. 9 display is in conjunction with the planar configuration of the probe 18 of one embodiment of the invention.As shown in Figure 9, a resistance R1 is arranged between this contact 19_4 and this pad 18_1, and a resistance R2 is arranged between this contact 19_5 and this pad 18_1, and a resistance R3 is arranged between this contact 19_6 and this pad 18_1.These resistance R1, R2, and R3 is as current-limiting resistance, to be limited in short-circuit current when one or more contact is short-circuited to ground wire or power lead.In addition, a resistance R4 is arranged between this pad 18_5 and certain voltage source (such as a ground voltage).Therefore, when the PMOS transistor M1 in Fig. 4 and nmos pass transistor M2 ends, this pad 18_5 can avoid suspension joint.
As shown in Figure 1, after completing associativity test, betide this measuring head 14 and these wafers 30,32, and the associativity disabled status on transmission path between 34 can be detected and get rid of, then these wafers 30,32, and 34 can carry out burned step.Burned step relates to these wafers 30,32, and 34 power supplies, and by these wafers 30,32, and 34 heating are with the disable velocity accelerating initial failure wafer.After burned step and follow-up CP testing procedure complete, that is after the burned test of a wafer scale completes, this wafer 22 can be cut into independently wafer.The defective wafer of tool can be dropped, and other good wafer can be assembled into the element of encapsulation.
As shown in Figure 4, this wafer 30 comprises multiple pad 30_1 to 30_6.These pads 30_1 to 30_6 can be categorized as testing cushion or joint sheet.These testing cushion are as being used for the configuration pad of testing wafer in wafer scale, and these joint sheets are intended for the configuration pad that wire connects.As mentioned above, these pads 30_1 to 30_5 is used to test this wafer 30.By these pads 30_1 to 30_5, test signal can input to this wafer 30 and test result can export.
Joint sheet is used to the lead frame (lead frame) being connected to an encapsulation in encapsulation engagement step by a metal wire.Can, simultaneously as testing cushion and joint sheet, after wafer 30 encapsulates, need a logical circuit with this testing circuit 301 of not activation to make most pad 30_1 to 30_5.Figure 10 display is in conjunction with the part circuit diagram of this wafer 30 of one embodiment of the invention.As shown in Figure 10, this wafer 30 also comprises enable circuit 303 and an internal circuit 305.This enable circuit 303 comprises a pull-up element M3 and and fastens (latch) 304.This is fastened 304 and comprises a pair back-to-back phase inverter, and wherein phase inverter X6 send (feed-forward) phase inverter before one, and phase inverter X7 is as feedback (feedback) phase inverter.In order to make the circuit of Figure 10 suitably operate, this phase inverter X7 is the more weak phase inverter of a driving force, therefore has more weak fan-out capability compared with phase inverter X6.
The running of this enable circuit 303 is described below.At the burned test period of wafer scale, this Test System Controller 10 produces parallel test signal to test the wafer 30,32 on this wafer 22 to be measured, and 34, as shown in Figure 1.In this situation, this testing circuit 301 and this enable circuit 303 receive the test signal L1 of self-controller 10 via this pad 30_1 in Fig. 10, and signal L1 has logical one level.Therefore, this testing circuit 301 can perform the logical operation of table 1 in response to the test signal that these pad 30_2 to 30_4.This test result then can send this Test System Controller 10 back to carry out next step analysis by pad 30_5.
After the burned test of wafer scale completes, the defective wafer of tool can be dropped, and other good wafer can carry out encapsulation step.After encapsulation step completes, the joint sheet of wafer can be engaged to packaging conductive wire, and therefore wafer can receive the signal of outer member.As shown in Figure 10, this pad 30_1 is used to as testing cushion, but not joint sheet; These pads 30_2 to 30_5 is used to as testing cushion and joint sheet; And this pad 30_6 is used to as joint sheet, but not testing cushion.Therefore, these pads 30_2 to 30_6 can receive the signal of outer member after packaging, and this internal circuit can operate accordingly.In order to avoid signal disturbing, this testing circuit 301 optionally can operate according to the logic level of the signal on this pad 30_1.
As shown in Figure 10, at the burned test period of wafer scale, because the probe of wafer 30 via correspondence contacts with probe 18, this signal L1 can be pulled to logical one level.After receive logic 1 level, this testing circuit 301 can operate according to the signal of these pads 30_2 to 30_4.Due to the weak output driving force of weak phase inverter X7, the signal on this pad 30_1 can be overdrived the output of this weak phase inverter X7, fastens 304 change states to allow this.But after the encapsulation of this wafer 30, this pad 30_1 can not contact outer member, and the logic level therefore on this pad 30_1 can change and determined by this enable circuit 303.
The sequential chart when enable circuit 303 that Figure 11 shows Figure 10 operates.As shown in figure 11, this encapsulated wafer 30 power when time t0.When time t0, a power supply signal PU at logical zero level, the PMOS transistor M3 conducting therefore in Figure 10.When PMOS transistor M3 conducting, this fastens the output signal L1 meeting of 304 initially to a logical zero level.When time t1, supply power vd D is higher than a critical voltage level, and therefore this power supply signal PU meeting transition is to logical one level.When this power supply signal PU arrives logical one level, PMOS transistor M3 ends, and therefore this bolt 304 keeps lock-out state, and continues to provide signal L1 at this logical zero level.After this signal of reception L1, the generation of this testing circuit 302 has the signal N1 of logical one level and produces the signal N2 with logical zero level, and PMOS transistor M1 and nmos pass transistor M2 is ended.Mode according to this, this testing circuit 301 can not activation after packaging.
Technology contents of the present invention and technical characterstic disclose as above, but those skilled in the art still may make all replacement and the modification that do not deviate from spirit of the present invention based on teaching of the present invention and enlightenment.Therefore, protection scope of the present invention should be not limited to embodiment, and should comprise various do not deviate from replacement of the present invention and modification, and is contained by claim of the present invention.
Claims (14)
1. a test macro, in order to perform the burned test of a wafer scale, comprising:
One probe;
M the first signal contact, in order to receive m test signal of m the first test channel from a tester table, m is a positive integer;
N secondary signal contact, in order to provide n test result to n second test channel of this tester table, n is a positive integer; With
A crosspoint array, comprise (m+1) individual row and n row, every a line has n contact and each row has (m+1) individual contact, wherein, each of n contact in a first row is electrically connected to one corresponding in n secondary signal contact, and each of n contact in one i-th row is electrically connected to one corresponding in m the first signal contact, wherein i is positive integer, and 2≤i≤(m+1); And
N wafer, each wafer comprises:
M input pad, each wherein in these input pads, by m contact of the wherein row in the n in this crosspoint array row, receives one of correspondence in m the test signal from this tester table;
One testing circuit, outputs signal to produce one in an inspection pad in order to the input signal received from this m input pad; With
This inspection pad, by a contact of the wherein row in the n in this crosspoint array row, one of them providing n test result is to this tester table.
2. test macro according to claim 1, wherein this test macro sequentially performs an associativity test before packaging, a burned step and a wafer probe test step.
3. test macro according to claim 2, wherein this test macro by the logic level changing in m test signal one of them to obtain n test result.
4. test macro according to claim 3, wherein whether this tester table determines to have a short circuit to betide transmission path between this probe and these wafers by this n test result.
5. test macro according to claim 3, wherein whether this tester table determines to have an open circuit to betide transmission path between this probe and these wafers by this n test result.
6. test macro according to claim 1, each of n contact wherein in this i-th row is electrically connected to one corresponding in m the first signal contact by a resistance.
7. test macro according to claim 1, each wherein in these secondary signal contacts is electrically connected a fixed voltage source by a resistance.
8. test macro according to claim 1, wherein this testing circuit comprises:
One logical circuit, in order to receive these input signals from this m input pad;
One PMOS transistor, has a grid to receive one first output signal from this logical circuit; And
One nmos pass transistor, has a grid to receive one second output signal from this logical circuit;
Wherein this PMOS transistor and this nmos pass transistor are electrically connected to this inspection pad.
9. test macro according to claim 8, wherein this inspection pad is used to test and engages purposes, and one of them in this m input pad is only in order to test-purpose, and other person in these m input pad is used to test and engages purposes.
10. test macro according to claim 9, wherein this wafer comprises:
One pull-up element, in order to receive an enabling signal to provide a pull-up signal;
One first phase inverter, in order to receive this pull-up signal to provide a not enable signal, cuts out this PMOS transistor and this nmos pass transistor whereby after this wafer package; And
One second phase inverter, in order to receive this not enable signal to produce this pull-up signal;
Wherein this first phase inverter has more weak driving force compared with the second phase inverter.
11. 1 kinds of semiconductor elements, in order to perform an associativity test, comprising:
M input pad, each wherein in these input pads receives from one corresponding in m test signal of an outside board;
One testing circuit, outputs signal to produce one in an inspection pad in order to the input signal received from this m input pad; And
This inspection pad, outputs signal to this outside board in order to provide this.
12. semiconductor elements according to claim 11, wherein this outside board sequentially to change in m test signal one of them logic level to produce this output signal.
13. semiconductor elements according to claim 12, wherein this testing circuit comprises:
One logical circuit, in order to receive these input signals from this m input pad;
One PMOS transistor, has a grid to receive one first output signal from this logical circuit; And
One nmos pass transistor, has a grid to receive one second output signal from this logical circuit;
Wherein this PMOS transistor and this nmos pass transistor are electrically connected to this inspection pad.
14. semiconductor elements according to claim 9, wherein this semiconductor element also comprises:
One pull-up element, in order to receive an enabling signal to provide a pull-up signal;
One first phase inverter, in order to receive this pull-up signal to provide a not enable signal, cuts out this PMOS transistor and this nmos pass transistor whereby; And
One second phase inverter, in order to receive this not enable signal to produce this pull-up signal;
Wherein this first phase inverter has more weak driving force compared with the second phase inverter.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
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| US201361844705P | 2013-07-10 | 2013-07-10 | |
| US61/844,705 | 2013-07-10 | ||
| US14/315,127 | 2014-06-25 | ||
| US14/315,127 US9575114B2 (en) | 2013-07-10 | 2014-06-25 | Test system and device |
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| CN104280651A true CN104280651A (en) | 2015-01-14 |
| CN104280651B CN104280651B (en) | 2018-08-17 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108140590A (en) * | 2015-09-30 | 2018-06-08 | 东京毅力科创株式会社 | Wafer inspection method and wafer inspector |
| CN108417504A (en) * | 2017-02-10 | 2018-08-17 | 爱思开海力士有限公司 | Semiconductor devices |
| CN111044961A (en) * | 2018-10-15 | 2020-04-21 | 吴茂祥 | Test machine self-checking system and test method |
| CN113030535A (en) * | 2019-12-09 | 2021-06-25 | 华邦电子股份有限公司 | Short circuit probe card, wafer test system and fault cause detection method of system |
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| CN114152858A (en) * | 2022-02-08 | 2022-03-08 | 广州粤芯半导体技术有限公司 | Electrical test device and test method for cutting channel device |
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