CN104243330A - Low-density vertical interconnection oriented three-dimensional on-chip network router - Google Patents
Low-density vertical interconnection oriented three-dimensional on-chip network router Download PDFInfo
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Abstract
The invention relates to a low-density vertical interconnection oriented three-dimensional on-chip network router which comprises internal control logic, a crossbar switch, five horizontal ports and two vertical ports; an on-chip network comprises multiple on-chip network nodes, each network node comprises a processing unit provided with a network interface or a storage unit and a router, each processor or the storage unit is in communication with the corresponding router through the network interface, the output channel of the vertical port of router adopts a parallel-in serial-out shifting register circuit, and the input channel adopts a serial-in parallel-out shifting register circuit. The low-density vertical interconnection oriented three-dimensional on-chip network router has the advantages that the output channel and the input channel of the vertical port of the three-dimensional on-chip network router respectively adopt a parallel-in serial-out shifting register and a serial-in parallel-in shifting register, and data can be transmitted effectively and reliably under the condition that vertical connection density of the three-dimensional on-chip network is decreased.
Description
Technical field
The present invention relates to network on three-dimensional chip router, particularly relate to a kind of network on three-dimensional chip router towards low-density perpendicular interconnection.
Background technology
Along with on chip, integration density is increasing, and traditional method for designing based on bus interconnection has to face severe communication performance bottleneck, and network-on-chip is just for addressing this problem and a kind of method for designing of interconnection Network Based newly that puts forward.On the other hand, along with the progress of technique, the long delay of global wires becomes the key factor of limited chip performance, and three-dimensional integration technology arises at the historic moment.The combination of three-dimensional integration technology and network-on-chip, the design for following multi core chip provides a direction.
The advantages such as network on three-dimensional chip has easily extensible, integration density is high, global wires is short, chip area is little, performance is good, but also there are the shortcomings such as manufacturing cost is high, poor heat radiation.
Namely three-dimensional integration technology is that Chip Vertical is stacking, traditional encapsulation technology has system in package (SiP) and laminate packaging (PoP), the many of nearest research is silicon perforation (Through-Silicon-Via, TSV) technology.Then the vertical join line technology be made up of silicon puncturing technique injects electric conducting material by punching on silicon, is interconnected by Chip Vertical.The main drive of development TSV technology is that TSV conductor length is short, and resistance and inductance lower, thus can the transmission speed of promotion signal, under the trend of micro, these are all the performance factors of most critical.Three-dimensional integration technology, compared to some extra treatment steps of the integrated needs of two dimension, comprises the formation of TSV, Wafer Thinning and wafer and engages.Compare with other encapsulation technologies, TSV vertical wires is shorter, transmission speed is faster, power consumption is also lower simultaneously, but the manufacture process of TSV is more complicated also costly, TSV occupies relatively large chip area compared with logical device, reduces the rate of finished products of chip simultaneously, and these all have with the quantity of TSV and contact closely.
Wiring quantity between the router vertical direction port of existing network on three-dimensional chip is identical with the wiring quantity between horizontal direction port, horizontal direction port and vertical direction port adopt identical design, but because vertical direction line adopts the TSV technology that cost is higher, such design makes the area of chip and cost significantly increase.
Summary of the invention
The object of the invention is the deficiency overcoming above prior art, provides a kind of network on three-dimensional chip router towards low-density perpendicular interconnection, specifically has following technical scheme to realize:
The described network on three-dimensional chip router towards low-density perpendicular interconnection, comprise inner control logic, cross bar switch and five horizontal direction ports and two vertical direction ports, five horizontal direction ports, east respectively, west, south, north and local port, two vertical direction ports, on being respectively, lower port, it is characterized in that described network-on-chip comprises some network-on-chip nodes, described each network node comprises a processing unit with network interface or memory cell and a router, described each processing unit or memory cell are by described network interface and corresponding router communication, the upper port of described vertical direction, lower port is connected respectively input channel and output channel, described input channel adopts SI PO shift register circuit, described output channel adopts to be incorporated to goes here and there out shift-register circuit.
The further design of the described network on three-dimensional chip router towards low-density perpendicular interconnection is, described network-on-chip forms by multilayer chiop is stacking, described every one deck chip comprises the network node of equal number, in same layer, network node is connected by horizontal line each other, and arrange by the network topology mode of matrix, between described adjacent two layers, the network node of correspondence position is connected by the vertical join line be made up of silicon puncturing technique.
The further design of the described network on three-dimensional chip router towards low-density perpendicular interconnection is, described being incorporated to is gone here and there out shift-register circuit and is gone here and there out shift register formed by some being incorporated to, describedly be incorporated to that to go here and there out shift register number equal with the vertical join line quantity that vertical direction is made up of silicon puncturing technique, described be incorporated to go here and there out shift register adopt transpostion interval input, the cycle at interval is equal with the vertical join line quantity be made up of silicon puncturing technique.
The further design of the described network on three-dimensional chip router towards low-density perpendicular interconnection is, the output port of router vertical direction port is connected with FIFO memory.
The further design of the described network on three-dimensional chip router towards low-density perpendicular interconnection is, SI PO shift register circuit is made up of some SI PO shift registers, and described SI PO shift register number is equal with the vertical join line quantity be made up of silicon puncturing technique.
Advantage of the present invention is as follows:
In the present invention, the output channel of vertical direction port adopts to be incorporated to goes here and there out shift-register circuit, make the data parallel input from horizontal direction port transmission, Serial output, achieve the conversion from horizontal direction port to the data bit width of vertical direction port.For the transmission of long numeric data, adopt one group to be incorporated to go here and there out shift register, shift register number is equal with the vertical join line quantity be made up of silicon puncturing technique.For be incorporated to go here and there out shift register adopt transpostion interval input, the cycle at interval is equal with the vertical join line quantity be made up of silicon puncturing technique.The present invention goes here and there out shift register and SI PO shift register by adopting respectively in the output channel of network on three-dimensional chip router vertical direction port and input channel to be incorporated to, achieve the object effectively, reliably transmitting data when network on three-dimensional chip vertical join line density reduces, and improve chip rate of finished products, reduce chip area and decrease chip and the three-dimensional cost engaged, have a good application prospect.
Accompanying drawing explanation
Fig. 1 is the three-dimensional grid network-on-chip schematic diagram that the present invention adopts.
Fig. 2 is the end view of the three-dimensional grid network-on-chip schematic diagram shown in Fig. 1.
Fig. 3 is incorporated to and goes here and there out the schematic diagram of shift register described in being.
Fig. 4 (a) is incorporated to and goes here and there out the input of shift register described in being.
Fig. 4 (b) is incorporated to go here and there out the module diagram of shift register.
Fig. 5 (a) is described SI PO shift register cut-away view.
Fig. 5 (b) is the module diagram of SI PO shift register.
Fig. 6 is the schematic diagram of described vertical direction port.
Embodiment
Below in conjunction with accompanying drawing, the present invention program is described in detail.
Embodiment 1
The network on three-dimensional chip router towards low-density perpendicular interconnection that the present embodiment provides, comprises inner control logic, cross bar switch and five horizontal direction ports and two vertical direction ports, see Fig. 1.Above-mentioned five horizontal direction ports are East, West, South, North and local port respectively; Two vertical direction ports are upper and lower port respectively.
The network-on-chip that the present embodiment provides comprises some network-on-chip nodes, each network node comprises a processing unit with network interface and a router, each processing unit is by network interface and corresponding router communication, the output channel of the vertical direction port of router adopts to be incorporated to goes here and there out shift-register circuit, and input channel adopts SI PO shift register circuit.Network-on-chip node is altogether 32, two-layerly stackingly to be formed by upper and lower, described every one deck comprises 16 network nodes, in same layer, network node is connected by horizontal line each other, and arrange by the network topology mode of 4*4 matrix, described two-layer between the network node of correspondence position connected by the vertical join line be made up of silicon puncturing technique.The end view of network on three-dimensional chip as shown in Figure 2, in this example, horizontal line (Wire) quantity between horizontal direction routing node is 128, vertical join line (TSV) quantity be made up of silicon puncturing technique between vertical direction routing node is 64, therefore data in the vertical direction port transmission time need to be divided into two parts serial transmission.
In order to address this problem, the port of the present embodiment routers vertical direction redesigns.Fig. 3 is the design of the output channel of router vertical direction port, and elementary cell is that being incorporated to of two inputs goes here and there out (Parallel In Serial Out, PISO) shift register.Basic function is exported by the data serial of two parallel inputs.
The output channel of router vertical direction port adopts 64 identical being incorporated to go here and there out shift register.Be incorporated to and go here and there out 64, interval between two of shift register inputs, such as: the 0th and the 64th input first are incorporated to goes here and there out shift register, 1st and the 65th input second are incorporated to goes here and there out shift register, by that analogy, 63rd and the 127th input the 64th register, as shown in Fig. 4 (a).Such design achieves the parallel input of 128 bit data, and high 64 and low 64 order Serial output, effectively achieve the conversion of horizontal direction port to vertical direction port data bit wide.Fig. 4 (b) is incorporated to go here and there out the modularization sketch of shift register.
Fig. 5 (a) is the design of the input channel of router vertical direction port, and elementary cell is that two inputs seal in and go out (Serial In Parallel Out, SIPO) shift register.Basic function is that the data parallel inputted by dual serial exports.The input channel of router vertical direction port adopts 64 identical SI PO shift registers, to realize two 64 bit data serial inputs, the function of 128 bit data parallel outputs, and from vertical direction port to the conversion of the data bit width of horizontal direction port.The modularization sketch of SI PO shift register, see Fig. 5 (b).
As the simplified schematic diagram that Fig. 6 is the master-plan of router vertical direction port.128 bit data, by the parallel input of output channel, are then divided into two 64 bit data by TSV serial transmission, and data need 4 all after dates accepting passage parallel output simultaneously.The present embodiment adopts streamline can realize the film flying (flit) that every 2 cycles export 128, so input data need temporary transient depositing, therefore add at the output of route vertical direction port the FIFO memory that a degree of depth is 4, width is 128.
The present invention goes here and there out shift register and SI PO shift register by adopting respectively in the output channel of network on three-dimensional chip router vertical direction port and input channel to be incorporated to, achieve the object effectively, reliably transmitting data when network on three-dimensional chip vertical join line density reduces, and improve chip rate of finished products, reduce chip area and decrease chip and the three-dimensional cost engaged, have a good application prospect.
Embodiment 2
The network on three-dimensional chip router towards low-density perpendicular interconnection that the present embodiment provides, comprises inner control logic, cross bar switch and five horizontal direction ports and two vertical direction ports, see Fig. 1.Above-mentioned five horizontal direction ports are East, West, South, North and local port respectively; Two vertical direction ports are upper and lower port respectively.
The network-on-chip that the present embodiment provides comprises some network-on-chip nodes, each network node comprises a memory cell with network interface and a router, each memory cell is by network interface and corresponding router communication, the output channel of the vertical direction port of router adopts to be incorporated to goes here and there out shift-register circuit, and input channel adopts SI PO shift register circuit.Network-on-chip node is altogether 32, two-layerly stackingly to be formed by upper and lower, described every one deck comprises 16 network nodes, in same layer, network node is connected by horizontal line each other, and arrange by the network topology mode of 4*4 matrix, described two-layer between the network node of correspondence position connected by the vertical join line be made up of silicon puncturing technique.The end view of network on three-dimensional chip as shown in Figure 2, in this example, horizontal line (Wire) quantity between horizontal direction routing node is 128, vertical join line (TSV) quantity be made up of silicon puncturing technique between vertical direction routing node is 64, therefore data in the vertical direction port transmission time need to be divided into two parts serial transmission.All the other technical schemes of this enforcement do not repeat them here as described in Example 1.
Claims (5)
1. the network on three-dimensional chip router towards low-density perpendicular interconnection, comprise inner control logic, cross bar switch and five horizontal direction ports and two vertical direction ports, five horizontal direction ports, east respectively, west, south, north and local port, two vertical direction ports, on being respectively, lower port, it is characterized in that described network-on-chip comprises some network-on-chip nodes, described each network node comprises a processing unit with network interface or memory cell and a router, described each processing unit or memory cell are by described network interface and corresponding router communication, the upper port of described vertical direction, lower port is connected respectively input channel and output channel, described input channel adopts SI PO shift register circuit, described output channel adopts to be incorporated to goes here and there out shift-register circuit.
2. the network on three-dimensional chip router towards low-density perpendicular interconnection according to claim 1, it is characterized in that described network-on-chip forms by multilayer chiop is stacking, described every one deck chip comprises the network node of equal number, in same layer, network node is connected by horizontal line each other, and arrange by the network topology mode of matrix, between described adjacent two layers, the network node of correspondence position is connected by the vertical join line be made up of silicon puncturing technique.
3. the network on three-dimensional chip router towards low-density perpendicular interconnection according to claim 2, be incorporated to described in it is characterized in that and go here and there out shift-register circuit and gone here and there out shift register formed by some being incorporated to, describedly be incorporated to that to go here and there out shift register number equal with the vertical join line quantity that vertical direction is made up of silicon puncturing technique, described be incorporated to go here and there out shift register adopt transpostion interval input, the cycle at interval is equal with the vertical join line quantity be made up of silicon puncturing technique.
4. the network on three-dimensional chip router towards low-density perpendicular interconnection according to claim 3, is characterized in that the output channel of described router vertical direction port is connected with FIFO memory.
5. the network on three-dimensional chip router towards low-density perpendicular interconnection according to claim 2, it is characterized in that SI PO shift register circuit is made up of some SI PO shift registers, described SI PO shift register number is equal with the vertical join line quantity be made up of silicon puncturing technique.
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| CN105095148B (en) * | 2015-08-14 | 2018-07-13 | 浪潮(北京)电子信息产业有限公司 | A kind of mixed type network on three-dimensional chip |
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