CN104241374B - Deep-energy-level impurity tunneling field-effect transistor (TFET) and preparation method thereof - Google Patents
Deep-energy-level impurity tunneling field-effect transistor (TFET) and preparation method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
Abstract
The invention discloses a deep-energy-level impurity tunneling field-effect transistor (TFET) and a preparation method of the deep-energy-level impurity TFET. The deep-energy-level impurity TFET comprises a tunneling source region, a deep-energy-level impurity doping region, a channel region, a drain region and a control grid. The control grid is located on the channel region. The deep-energy-level impurity doping region is located at the interface between the tunneling source region and the channel region. The doping type of deep-energy-level impurities is different from that of the tunneling source region. The deep-energy-level impurity TFET can be an N-type device or a P-type device; the device structure of the deep-energy-level impurity TFET can remarkably increase on-state currents of the tunneling transistor while maintaining the TFET at a steep subthreshold slope; moreover, the preparation process is simple, the preparation method is completely based on the standard CMOS IC process, a TFET device can be effectively integrated in a CMOS integrated circuit, the production cost is greatly lowered, and the technological process is simplified.
Description
Technical field
The invention belongs to field-effect transistor logical device field in cmos vlsi (ULSI), specifically relates to
And a kind of deep-level impurity doping tunneling field-effect transistor and preparation method thereof.
Background technology
Since being born from integrated circuit, microelectronics integrated technology constantly develops always according to " Moore's Law ", semiconductor device
Part size constantly reduces.As semiconductor device enters deep sub-micron range, existing MOSFET element is due to by self-propagating
The conduction mechanism of drift is limited, and sub-threshold slope is limited by thermoelectrical potential kT/q and cannot be same with the diminution of device size
Step reduces.This results in MOSFET element leakage current and reduces the requirement for being unable to reach device dimensions shrink, the energy of whole chip
Consumption constantly rises, and chip power-consumption density is increased dramatically, and seriously hinders the integrated development of chip system.In order to adapt to integrated circuit
Development trend, the R and D work of novel super-low power consuming devices just seems particular importance.Tunneling field-effect transistor
(TFET, Tunneling Field-Effect Transistor), using the new conduction mechanism of band-to-band-tunneling (BTBT), is a kind of non-
Often there is the Novel low power consumption device for being suitable to system integration application development of development potentiality.TFET controls source and ditch by gate electrode
The tunnelling width of tunnel junctions at road interface so that source valence-band electrons are tunneling to channel conduction band (or raceway groove valence-band electrons tunnelling
To source conduction band) form tunnelling current.This new conduction mechanism breaks through heat in conventional MOS FET sub-threshold slope theoretical limit
The restriction of potential kT/q, it is possible to achieve the super steep sub-threshold slope less than 60mV/dec, reduces device static leakage current further
Reduce device quiescent dissipation.
But, due to quasiconductor band-to-band-tunneling efficiency it is low, the ON state current of TFET compared with existing MOSFET than relatively low,
The requirement in system integration application can not be met.Therefore, while more steep sub-threshold slope is kept, TFET ON states are improved
Electric current, is a very important problem for needing to solve in TFET device applications.
The content of the invention
It is an object of the invention to provide a kind of deep-level impurity tunneling field-effect transistor.The device architecture can keep
While tunneling field-effect transistor more steep sub-threshold slope, the ON state current of tunneling transistor is significantly improved.
The deep-level impurity tunneling field-effect transistor that the present invention is provided, its structure is as shown in Figure 1.The tunneling field-effect is brilliant
Body pipe includes tunnelling source region, deep-level impurity doped region, channel region, drain region and control gate；Control gate is located at the top of channel region；
Deep-level impurity doped region at tunnelling source region and channel region interface, the doping type and tunnelling of the deep-level impurity doped region
The doping type of source region is contrary.If the doping type of tunnelling source region is p-type doping, the doping type of deep-level impurity doped region
For N-type；If the doping type of tunnelling source region is n-type doping, the doping type of deep energy level doped region is p-type；
Above-mentioned deep-level impurity tunneling field-effect transistor can be N-type device or P-type device.In embodiments of the invention
In, for N-type device, tunnelling source region be p-type heavy doping, concentration about 1E19cm-3-1E21cm-3；Drain region is that N-type is heavily doped
It is miscellaneous, concentration about 1E18cm-3-1E19cm-3；Channel region is lightly doped for p-type, concentration about 1E13cm-3-1E15cm-3；Deep-level impurity
Doped region is n-type doping, using donor-type deep-level impurity, concentration about 1E16cm-3-1E18cm-3.And for P-type device comes
Say, tunnelling source region be N-type heavy doping, concentration about 1E19cm-3-1E21cm-3；, drain region be p-type heavy doping, concentration about 1E18cm-3-
1E19cm-3；Channel region is lightly doped for N-type, concentration about 1E13cm-3-1E15cm-3；Deep-level impurity doped region is p-type doping, adopts
Use acceptor type deep-level impurity, concentration about 1E16cm-3-1E18cm-3。
Above-mentioned deep-level impurity is the alms giver that electronics can be ionized out under high electric field or the acceptor's depth energy for ionizing out hole
Level impurity, the electric field is 104The order of magnitude of V/cm.The deep-level impurity can be being introduced using ion implanting mode, it is also possible to is adopted
It is designed with the substrate with deep-level impurity.
For silicon substrate N-type deep-level impurity tunneling transistor, the donor-type deep-level impurity of correspondence doping can be deep energy
Level donor impurity gold or silver.
For silicon substrate p-type deep-level impurity tunneling transistor, the acceptor type deep-level impurity of correspondence doping can be deep energy
Level acceptor impurity nickel or zinc.
The deep-level impurity tunneling field-effect transistor that the present invention is provided can apply to Si or Ge semi-conducting materials, also may be used
To be applied to III-V compound semiconductor material.
The preparation method of above-mentioned deep-level impurity TFET device architectures, specifically includes following steps：
1) initial thermal oxide on a semiconductor substrate, and deposit one layer of nitride；
2) shallow trench isolation (Shallow Trench Isolation, STI) etching is carried out after photoetching, and deposits isolation material
Chemical-mechanical planarization (Chemical Mechanical Polishing, CMP) is carried out after material filling deep hole；
3) regrow gate dielectric layer, deposits grid material, and by carrying out photoetching and etching gate figure is formed；
4) with photoresist and grid material as mask, drain region is formed by ion implanting；
5) with photoresist and grid material as mask, tunnelling source region is formed by ion implanting；
6) annealed activator impurity by quick high-temp；
7) inject to form deep-level impurity doped region by angle-tilt ion；
8) by later process, including deposit passivation layer, opening contact hole and metallization, you can deep-level impurity tunnelling is obtained
Field-effect transistor.
In the preparation method of above-mentioned deep-level impurity TFET device architectures, step 1) in Semiconductor substrate be lightly doped or
Unadulterated Semiconductor substrate；The material of Semiconductor substrate can selected from Si, Ge, SiGe, GaAs, other II-VI, III-V or
Silicon SOI or the one kind in the germanium GOI on insulator in the binary or ternary semiconductor of IV-IV races, insulator.Step
3) material of the gate dielectric layer in is selected from SiO2、Si3N4With the one kind in high-K gate dielectric material；Wherein regrow gate dielectric layer
Method be conventional thermal oxidation, nitriding thermal oxidation, chemical vapor deposition or physical vapor deposition.Step 3) in grid material to mix
The silicide of miscellaneous polysilicon, metallic cobalt, metallic nickel, the silicide of metallic cobalt or metallic nickel.
Step 4) drain region is formed by ion implanting, inject the concentration about 1E18cm of ion-3-1E19cm-3；Step 5) it is logical
Cross ion implanting and form tunnelling source region, inject the concentration about 1E19cm of ion-3-1E21cm-3；Step 7) noted by angle-tilt ion
Enter to be formed deep-level impurity doped region, inject the concentration about 1E16cm of ion-3-1E18cm-3。
The method have the benefit that：
Compared with existing TFET, the device architecture of the deep-level impurity tunneling field-effect transistor that the present invention is provided can have
Effect increase device conducting electric current, while keeping steep sub-threshold slope.By taking N-type device as an example, have and tunnel at the knot of tunnelling source
The contrary donor-type deep-level impurity doped region of source region doping type is worn, and the deep-level impurity energy level is located in channel region forbidden band
Centre is following, the top of valence band of close channel region.When device is in OFF state, these deep-level impurities are not ionized or drawn
The shallow level impurity compensation for entering.When gate electrode plus positive voltage, raceway groove can be with drop-down, electric-field enhancing at the knot of tunnelling source, in tunnelling source
Bind up one's hair raw band-to-band-tunneling, device is opened.It is main that source region valence-band electrons occur to channel conduction band sky electronic state when grid voltage is less
Band-to-band-tunneling, with more steep subthreshold swing；As grid voltage increases, electric-field enhancing is to deep-level impurity at the knot of tunnelling source
Ionization critical electric field, the electronics moment in the deep energy level in deep-level impurity doped region is ionized, at deep-level impurity energy level
Empty electronic state is formed, so as to the band-to-band-tunneling that the empty electronic state from tunnelling source region valence-band electrons to deep-level impurity energy level occurs, and
The electronics and moment being tunneling on deep-level impurity energy level is ionized to channel conduction band and forms extra supplementary tunnelling current, so as to
Effectively increase the ON state current of tunneling transistor.
The deep-level impurity tunneling field-effect transistor preparation process is simple that the present invention is provided, preparation method is based entirely on mark
Accurate CMOS IC techniques, can effectively integrated TFET devices in CMOS integrated circuits, significantly reduce production cost, letter
Technological process is changed.
Description of the drawings
Fig. 1 is the structural representation of deep-level impurity tunneling field-effect transistor of the present invention；
Fig. 2 is to be formed to remove the device profile map after nitride after STI isolation on a semiconductor substrate；
Fig. 3 is by photoetching and etching forms the device profile map after grid material；
Fig. 4 is to expose the drain region of TFET devices by photoetching and form the device profile behind drain region by ion implanting
Figure；
Fig. 5 is to expose TFET device tunnelling source regions by photoetching and form the device after tunnelling source region by ion implanting
Profile；
Fig. 6 is to inject the device profile map to be formed after deep-level impurity doped region by angle-tilt ion；
In Fig. 1～Fig. 6,1-Semiconductor substrate；2-STI sealing coats；3-gate dielectric layer；4-grid material；5-photoetching
Glue；6-drain region；7-tunnelling source region；8-deep-level impurity doped region；The passivation layer of 9-later process；10-later process
Metal.
Specific embodiment
Below in conjunction with accompanying drawing, by specific embodiment, the present invention is described further.
The deep-level impurity tunneling field-effect transistor that the present invention is provided, its structure is as shown in Figure 1.The tunneling field-effect is brilliant
Body pipe includes tunnelling source region, channel region, drain region and control gate；Wherein, control gate is located at the top of channel region；Tunnelling source region with
Also include a deep-level impurity doped region at channel region interface, and the doping type of deep-level impurity and tunnelling source region are mixed
Miscellany type is contrary.For N-type device, tunnelling source region is p-type heavy doping (about 1E19cm-3-1E21cm-3), drain region is N-type
Heavy doping (about 1E18cm-3-1E19cm-3), channel region is lightly doped (about 1E13cm for p-type-3-1E15cm-3)；Deep-level impurity is mixed
Miscellaneous area is n-type doping, using donor-type deep-level impurity (about 1E16cm-3-1E18cm-3).And for P-type device, tunnelling
Source region is N-type heavy doping (about 1E19cm-3-1E21cm-3), drain region is p-type heavy doping (about 1E18cm-3-1E19cm-3), channel region
(about 1E13cm is lightly doped for N-type-3-1E15cm-3)；Deep-level impurity doped region is p-type doping, miscellaneous using acceptor type deep energy level
Matter (about 1E16cm-3-1E18cm-3)。
Above-mentioned deep-level impurity is the alms giver that electronics can be ionized out under High-Field or the acceptor's deep energy level for ionizing out hole
Impurity, this electric field is 104The order of magnitude of V/cm.The deep-level impurity can be being introduced using ion implanting mode, it is also possible to is adopted
It is designed with the substrate with deep-level impurity.
For silicon substrate N-type deep-level impurity tunneling transistor, the donor-type deep-level impurity of correspondence doping can be deep energy
Level donor impurity gold or silver.
For silicon substrate p-type deep-level impurity tunneling transistor, the acceptor type deep-level impurity of correspondence doping can be deep energy
Level acceptor impurity nickel or zinc.
The deep-level impurity tunneling field-effect transistor that the present invention is provided can apply to Si or Ge semi-conducting materials, also may be used
To be applied to III-V compound semiconductor material.
Below by taking N-type device as an example, the preparation method of above-mentioned deep-level impurity tunneling field-effect transistor, p-type depth are illustrated
The preparation of level impurities tunneling field-effect transistor device is similar to therewith.The system of above-mentioned deep-level impurity tunneling field-effect transistor
The implementation steps of Preparation Method as shown in Fig. 2～Fig. 6, the structure of the N-type deep-level impurity tunneling field-effect transistor for preparing
As shown in figure 1, concrete steps include：
1) substrate doping to be lightly doped, crystal orientation is<100>Silicon substrate 1 on initial one layer of titanium dioxide of thermal oxide
Silicon, thickness about 10nm, and deposit one layer of silicon nitride (Si3N4), thickness about 100nm is active using shallow-trench isolation fabrication techniques afterwards
Area STI sealing coats 2, then carry out CMP, as shown in Figure 2；
2) silicon dioxide of surface initial growth is removed in drift, then thermally grown one layer of gate dielectric layer 3, and gate dielectric layer is SiO2,
Thickness is 1～5nm；Grid material 4 is deposited using LPCVD, grid material is doped polysilicon layer, and thickness is 50～200nm.Make by lithography
Gate figure, etching grid material 4 until gate dielectric layer 3, as shown in Figure 3；
3) with photoresist 5 and grid 4 as mask, (As, dosage is 1E14/cm to carry out the ion implanting of drain region 6-2, energy is
40keV, injection ion concentration is about 3E18/cm-3) as shown in Figure 4；
4) with photoresist 5 and grid 4 as mask, the ion implanting (BF of tunnelling source region 7 is carried out2, dosage is 1E15/cm-2, energy
For 20keV, inject ion concentration and be about 2E20/cm-3), as shown in Figure 5.A quick high-temp annealing is carried out, and to implanted dopant
Enter line activating (temperature is 1050 DEG C, and the time is 10s)；
5) with grid 4 as mask, inclining about 30 ° of angles carries out donor-type deep-level impurity doped region 8 ion implanting (Au, agent
Measure as 1E12/cm-2, energy is 90keV, and injection ion concentration is about 1E17/cm-3), as shown in Figure 6；
6) conventional later process, including deposit passivation layer 9, opening contact hole and metallization 10 etc., above-mentioned base are finally entered
The structure of the N-type deep-level impurity tunneling field-effect transistor prepared in standard CMOS IC techniques is as shown in Figure 1.
For above-mentioned preparation method, in step 1) in, substrate can be lightly doped or unadulterated Semiconductor substrate；Partly lead
The material of body substrate can be Si, Ge, SiGe, GaAs, other II-VI, the binary or ternary compound of III-V and IV-IV races
The germanium (GOI) on silicon (SOI) or insulator on quasiconductor, insulator.Step 2) in the material of gate dielectric layer may be selected from
SiO2、Si3N4With the one kind in high-K gate dielectric material；Wherein regrow gate dielectric layer method be conventional thermal oxidation, nitrating
Thermal oxide, chemical vapor deposition or physical vapor deposition.Step 2) in grid material can be DOPOS doped polycrystalline silicon, metallic cobalt, gold
The silicide of category nickel, the silicide of metallic cobalt or metallic nickel.
Although the present invention is disclosed as above with preferred embodiment, but is not limited to the present invention.It is any to be familiar with ability
The technical staff in domain, under without departing from technical solution of the present invention ambit, all using in the methods and techniques of the disclosure above
Appearance makes many possible variations and modification, or the Equivalent embodiments for being revised as equivalent variations to technical solution of the present invention.Therefore,
Every content without departing from technical solution of the present invention, according to the technical spirit of the present invention to made for any of the above embodiments any simple
Modification, equivalent variations and modification, still fall within the range of technical solution of the present invention protection.
Claims (12)
1. a kind of deep-level impurity tunneling field-effect transistor, is characterized in that, including tunnelling source region, deep-level impurity doped region,
Channel region, drain region and control gate；The control gate is located at the top of the channel region；The deep-level impurity doped region is in tunnelling
At source region and channel region interface, the doping type phase of the doping type of the deep-level impurity doped region and the tunnelling source region
Instead.
2. deep-level impurity tunneling field-effect transistor as claimed in claim 1, is characterized in that, the deep-level impurity tunnelling field
Effect transistor is N-type device or P-type device.
3. deep-level impurity tunneling field-effect transistor as claimed in claim 1, is characterized in that, the deep-level impurity tunnelling field
Effect transistor is N-type device, and the tunnelling source region is p-type heavy doping, and the drain region is N-type heavy doping, and the channel region is P
Type is lightly doped, and the deep-level impurity doped region is n-type doping.
4. deep-level impurity tunneling field-effect transistor as claimed in claim 3, is characterized in that, the deep-level impurity tunnelling field
Effect transistor is silicon substrate N-type deep-level impurity tunneling transistor, and the deep-level impurity of the deep-level impurity doped region is to apply
Principal mode deep-level impurity gold or silver.
5. deep-level impurity tunneling field-effect transistor as claimed in claim 1, is characterized in that, the deep-level impurity tunnelling field
Effect transistor is P-type device, and the tunnelling source region is N-type heavy doping, and the drain region is p-type heavy doping, and the channel region is N
Type is lightly doped, and the deep-level impurity doped region is p-type doping.
6. deep-level impurity tunneling field-effect transistor as claimed in claim 5, is characterized in that, the deep-level impurity tunnelling field
Effect transistor is silicon substrate p-type deep-level impurity tunneling transistor, the deep-level impurity of the deep-level impurity doped region be by
Principal mode deep-level impurity nickel or zinc.
7. deep-level impurity tunneling field-effect transistor as claimed in claim 1, is characterized in that, the deep-level impurity is to pass through
Ion injection method is introduced and obtained, or by being obtained using the substrate with deep-level impurity.
8. the preparation method of deep-level impurity tunneling field-effect transistor described in claim 1, comprises the following steps：
1) initial thermal oxide on a semiconductor substrate, and deposit one layer of nitride；
2) carry out shallow groove isolation etching after photoetching, and to deposit and carry out chemical-mechanical planarization after isolated material filling deep hole；
3) regrow gate dielectric layer, deposits grid material, and by carrying out photoetching and etching gate figure is formed；
4) with photoresist and grid material as mask, drain region is formed by ion implanting；
5) with photoresist and grid material as mask, tunnelling source region is formed by ion implanting；
6) annealed activator impurity by quick high-temp；
7) inject to form deep-level impurity doped region by angle-tilt ion；
8) by later process, including deposit passivation layer, opening contact hole and metallization, you can deep-level impurity tunnelling field effect is obtained
Answer transistor.
9. the preparation method of deep-level impurity tunneling field-effect transistor as claimed in claim 8, is characterized in that, step 1) it is described
Semiconductor substrate is to be lightly doped or unadulterated Semiconductor substrate；The material of the Semiconductor substrate is Si, Ge, II-VI, III-
Silicon or the one kind in the germanium on insulator in the binary or ternary semiconductor of V or IV-IV races, insulator.
10. the preparation method of deep-level impurity tunneling field-effect transistor as claimed in claim 8, is characterized in that, step 3) institute
The material for stating gate dielectric layer is SiO2、Si3N4With the one kind in high-K gate dielectric material；The method of the gate dielectric layer that regrows
For conventional thermal oxidation, nitriding thermal oxidation, chemical vapor deposition or physical vapor deposition.
The preparation method of 11. deep-level impurity tunneling field-effect transistors as claimed in claim 8, is characterized in that, step 3) in
Grid material for DOPOS doped polycrystalline silicon, metallic cobalt, metallic nickel, the silicide of metallic cobalt or metallic nickel silicide.
The preparation method of 12. deep-level impurity tunneling field-effect transistors as claimed in claim 8, is characterized in that, step 4) it is logical
Cross ion implanting and form drain region, concentration is 1E18cm-3～1E19cm-3；Step 5) tunnelling source region is formed by ion implanting, it is dense
Spend for 1E19cm-3～1E21cm-3；Step 7) to inject to form deep-level impurity doped region by angle-tilt ion, concentration is 1E16cm-3～1E18cm-3。
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