CN104241121A - Method of fabricating diodes - Google Patents
Method of fabricating diodes Download PDFInfo
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- CN104241121A CN104241121A CN201410260435.XA CN201410260435A CN104241121A CN 104241121 A CN104241121 A CN 104241121A CN 201410260435 A CN201410260435 A CN 201410260435A CN 104241121 A CN104241121 A CN 104241121A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000005224 laser annealing Methods 0.000 claims abstract description 15
- 238000000227 grinding Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 30
- 238000002513 implantation Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 19
- 239000012535 impurity Substances 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 11
- 230000004913 activation Effects 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000000630 rising effect Effects 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 4
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 1
- 239000007943 implant Substances 0.000 abstract 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 abstract 1
- 230000003139 buffering effect Effects 0.000 description 27
- 235000012431 wafers Nutrition 0.000 description 26
- 238000011084 recovery Methods 0.000 description 18
- 239000002019 doping agent Substances 0.000 description 12
- 238000001994 activation Methods 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 206010019133 Hangover Diseases 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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Abstract
The invention discloses a method of fabricating diodes. A large diameter wafer is thinned by grinding a back surface and a laser annealed n+ phosphorous implant region is used to form a cathode contact. Multiple back side proton implants are used to fabricate a field stop layer. The proton implanted region is annealed by preheating in an oven combined with laser annealing. The cathode and field stop layer structure may also be used in an IGBT.
Description
Technical field
The present invention relates to a kind of method manufacturing diode, described diode such as power diode, particularly the power diode of quick recovery-type.
Background technology
Fast quick-recovery power diode is usually by p-n
--n-n
+doped region is formed, and is namely respectively p-type anode layer, n
-voltage blocking layer, the buffering area of N-shaped doping increased gradually and shallow but heavily doped n
+back side cathode layer.N
-the thickness in district depends on the diodes nominal voltage for its application, n
-the thickness in district represents the major part of device gross thickness.The stationarity of the dopant profiles determination diode recovery characteristic of N-shaped buffering area.Demonstrated the importance [see reference document 1 to reference literature 3] of N-shaped buffering area for the intensity of diode recovery before.Therefore, present most of power diode is made up of long diffusion n-type buffering area, and it can be combined in substrate level place by high annealing.For centre to low rated voltage diode (< 1700V), n
-the thickness in district is less than 150 μm usually, and comprises all four district (p-n
--n-n
+) gross thickness can be only about 200 μm or even less.
At present, the Si substrate for diode manufacture starts from prediffusion N-shaped buffering area overleaf usually, therefore, and n
-thickness or the device rated voltage in district are also determined in advance.Therefore, different Si substrates is used for the manufacture of the diode of different rated voltage.But due in order to mechanical stability, the thickness of substrate must increase along with wafer diameter, in order to keep n
-district's (that is, device rated voltage) is constant, and the thickness of prediffusion N-shaped buffering area also increases.
Such as, for the wafer manufacture line of 6 inches of (150mm) diameters, substrate thickness for diode production is about 320 μm, wherein for 1700V rated voltage diode, the thickness of N-shaped prediffusion buffering area is about 170 μm, and thicker for the thickness of the diode N-shaped prediffusion buffering area of 1200V or lower rated voltage.Manufacturing long buffering area by diffusion is quite consuming time and costliness.Substrate thickness 8 inches of these problems of (200mm) wafer manufacture line become worse, this is because must significantly increase for mechanical strength during photoetching process.Typical substrate thickness for 8 inches of (200mm) wafers is about 700 μm, and the diode for 1700V or lower rated voltage needs the diffusion n-type buffering area thicker than 500 μm.8 inches of wafer manufacture lines are required that so thick prediffusion N-shaped buffering substrate is very difficult and very expensive.An object of the present invention is to provide a kind of alternative method manufactured for LED reverse mounting type fast recovery diode and IGBT.
List of references [4] and list of references [5] disclose the injection of proton.Proton is not very effective dopant, this is because proton itself is not dopant.They must react to form n-type dopant with other materials (oxygen as in silicon).
Summary of the invention
According to the present invention, provide a kind of method manufacturing diode, wherein process substrate wafer to produce doped layer structure, this wafer doping has n
-impurity and there is front surface and back surface, the method comprises: form anode on the front surface; Grinding back surface is to reduce the thickness of wafer; Utilize n
+impurity adulterates to back surface and by laser anneal activation n
+impurity is to form cathode layer; Utilize repeatedly N-shaped H+implantation through back surface and H+implantation is annealed at the inside of cathode layer formation resilient coating.
Substrate wafer is generally silicon, but also can use other substrates such as carborundum.
Can by being heated to lower than 500 DEG C and being about 450 DEG C suitably anneal to H+implantation in stove, but can be annealed by laser annealing alternatively, preferably before laser annealing or period wafer is heated to the temperature of the rising lower than annealing temperature, make it possible to thus more effectively realize carrying out differential annealing in the position expected in the thickness of wafer.According to the position at inner wafer H+implantation, find that being used for effective pre-warmed temperature is about 300 DEG C to 350 DEG C, but lower temperature can be adopted.
Boron injection and thermal diffusion can be utilized to form anode on the front surface.Also or photoetching process can be performed on the front surface before the grinding alternatively.Can on cathode layer deposition of thin Ti layer and being annealed by laser annealing.
Present invention also offers a kind of method manufacturing semiconductor device, comprise and in wafer, form doped layer by impurity being injected into substrate wafer inside, then laser annealing is carried out to impurity, it is characterized in that temperature wafer being preheated to the rising lower than annealing temperature before applying laser annealing.
Accompanying drawing explanation
In the accompanying drawings:
Fig. 1 shows the schematic diagram according to the critical process step related in the manufacture of LED reverse mounting type diode of the present invention;
Fig. 2 shows the typical dopant profiles utilizing repeatedly H+implantation for 1700V quick recovery-type diode;
Fig. 3 is the curve chart of the forward I-V characteristic for three different buffer structure simulations;
Fig. 4 is the curve chart of the reverse BV (blocking voltage) for three different buffer structure simulations;
Fig. 5 is the curve chart for the instantaneous Reverse recovery waveform of cathode current and voltage under the initial current condition of 300A and di/dt=1000A/ μ s;
Fig. 6 is under three different conditions for the curve chart of Dynamic-Recovery waveform of diode measurement with prediffusion N-shaped buffering area;
Fig. 7 is under three different conditions for the curve chart of Dynamic-Recovery waveform of diode measurement of buffering area with Proton Implantation; And
Fig. 8 be by the diode with conventional diffusing, buffering district with according to the curve chart compared relative to the recovery energy loss of operating current with the diode of the buffering area of Proton Implantation of the present invention.
Embodiment
Fig. 1 a shows the even n of standard as initial substrate
-the Si wafer of doping.P-type positive contact layer is formed in the front of wafer by boron injection and thermal diffusion.Also all lithographic process steps are applied to front in this stage, require that wafer has required mechanical strength for some meticulous steps (such as the stepper (stepper) of feature calibration), be therefore greater than the thickness of the rated voltage being suitable for resulting devices at the thickness of this stage substrate.
Then standard wafer milling apparatus is utilized to grind to reduce thickness to the thickness of rated voltage being suitable for diode to substrate.This stage is represented by Fig. 1 b.
Then injected by the phosphorus of high dose and form N-shaped cathode contact layer on the back side, result is illustrated by Fig. 1 c.Once be completely processed front, chip temperature must be limited in lower than 500 DEG C to protect the treated pattern on front.The formation of such temperature limiting to N-shaped buffering area and both the impurity activations for back contact layer all have a negative impact.Impurity Diffusion for buffering area formation and both the activation for low contact resistance all need the temperature higher than 1000 DEG C usually, and high annealing is improper here with the conventional method realizing being used for the Impurity Diffusion of buffering area formation and the activation at cathode contacts place for low contact resistance.
On the contrary, laser annealing is used for back side impurity activation to realize good ohmic contact, as shown in Figure 1 d.The key advantage of laser annealing is that this annealing is highly confined to the fact in the degree of depth very shallow apart from back surface.Temperature only under LASER SPECKLE very high (> 1400 DEG C) and its can melt below Si.And sharply decline away from the temperature of Direct Laser spot, and also decline quickly along the vertical direction of silicon inside.It can melt the thickness that back surface is up to hundreds of nm, and therefore activates the dopant in fusion zone completely.Then in short distance, temperature sharply declines to reach lower than 100 DEG C apart from back surface 50 μm of places.At front surface place, expect to keep at ambient temperature at During Annealing.Therefore, when front surface place exists temperature limiting, laser annealing is ideally suited for back surface n
+inject activation.
In order to improve the contact resistance being used for back side cathode contacts further, can at n
+the thin layer of depositing Ti on contact layer, and then utilize laser carry out annealing and form TiSi layer.This is because at n
+layer forms ohmic contact, and Ti is the intrinsic better metal of ratio aluminium.For using the p-type doping positive contact of metallic aluminium, vice versa.
Buffering area, the back side is formed, uses repeatedly N-shaped H+implantation, as shown in fig. le.The reason of H+implantation is selected to be at least two at this for N-shaped buffering area.
First, proton can inject enough dark (tens microns) for cushioning the unique available material of object.Such as, according to the analog result of SRIM program, having ion energy is that the proton of 1.5MeV can penetrate the degree of depth of about 30 μm in silicon inside, and carbon only penetrates the degree of depth of about 2 μm, and phosphorus only penetrates the degree of depth of about 1.4 μm.Need the dopant profiles repeatedly injecting to realize causing smooth counter to be recovered.But, need relative high dose to realize the doped level for the needs of voltage block object.Very low to the conversion efficiency of n-type dopant from proton, be usually less than one of percentage.In other words, 1e13cm
-2proton dose produce be less than 1e11cm
-2n-type dopant.Describe in US6482681B1 and US7514750B2 and utilized repeatedly Proton Implantation to form buffering area or cut-off region, field (field stop zone) in the semiconductor device.
Secondly, the activation temperature of H+implantation at about 450 DEG C, in the temperature limiting of 500 DEG C that we discuss before.The activation of H+implantation can be realized by the conventional Thermal Annealing in such as stove at 450 DEG C, also can be combined in by laser annealing the temperature raised in wafer holders and realize.The method of laser annealing has the advantage temperature of the front half of wafer being remained on less than 350 DEG C.
The Typical dopant that Fig. 2 shows for specified 1700V diode distributes, wherein complete front process, then, after obtaining N-shaped buffering area by the utilization series connection repeatedly H+implantation of accelerator and the subsequent anneal at 450 DEG C, wafer is from thinning back side to expectation thickness.Utilization has three kinds of different-energies and dosage (such as 350KeV and 8e13cm
-2; 700KeV and 6e13cm
-2; 1.2MeV and 4e13cm
-2) H+implantation to be to realize shown dopant profiles in triplicate.Independent SRP measurement confirms the dopant profiles of this simulation.Most high proton Implantation Energy is lower than 2MeV as used herein.
Fig. 3 shows the forward current feature of the simulation of three kinds of different buffer structures, and the number of times wherein injected is respectively 2 times, 3 times and 4 times.For 2 times, 3 times and 4 H+implantation under 100A current condition, forward voltage V
fbe calculated as 1.63V, 1.58V and 1.56V respectively.V
fdecline can be explained by the beneficial effect of electron injection along with the increase of injecting number of times.Figure 4 illustrates reverse blocking feature, wherein all three kinds of injection conditions are achieved to the blocking ability of 1950V.Fig. 5 shows the Reverse recovery performance under di/dt condition is 1000A/ μ s and initial forward current is 300A.Level and smooth recovery is obtained for all three kinds of situations, and for all three kinds of buffer structures, recovery curve is almost identical.
Fig. 6 and Fig. 7 compares the Dynamic-Recovery feature of the combined substrate be made up of two diodes.Fig. 6 represents the recovery waveform obtained from the wafer with prediffusion N-shaped buffering area, and Fig. 7 represents never prediffusion N-shaped buffering area but the recovery waveform that obtains of the wafer with the buffering area realized by three H+implantation of determined different energy before utilizing in this article and dosage.Show three kinds of test conditions: initial voltage is 900V, electric current 600A (being equivalent to each diode 300A); Then electric current is reduced to 56A, keeps voltage in 900V level simultaneously; And last voltage is increased to 1100V, current indication is 66A.The nominal current condition (each chip is about 30A) of latter two condition representative about 10%.Well-known diode is easier momentary recovery under low current conditions.But the recovery waveform that the diode for two types obtains under all these test conditions is very level and smooth.Than the diode having H+implantation wafer to manufacture (Fig. 7), longer restoring current hangover is observed for the produced diode of prediffusion wafer (Fig. 6).
With reference to Fig. 8, show relative to the recovery energy loss (Erec) measured by operating current, find that the diode with prediffusion buffering area is higher than the energy loss (Erec) during restoration of the diode manufactured by H+implantation.Usually, for a kind of situation, observe more than 100mJ under 600A current condition, about 40mJ is observed for another kind of situation.Higher energy loss can be explained by the during restoration longer current tail mentioned before.But, for the buffering diode of H+implantation, find that the quiescent losses (VF) under forward current condition is about 2.6V under the electric current (each diode 300A) of 600A, but about 1.82V is only for the VF loss that other diodes are same.So at this clearly, lose at forward VF and there is balance between reverse recovery loss (Erec).Wide coverage similar balance [list of references 7] before.
List of references
[1] Felsl H.P., Heinze B. and Lutz J., " Effects of Different Buffer Structures on the Avalanche Behaviour of High Voltage Diodes Under High Reverse Current Conditions " IEE Proc.-Circuits Devices Syst., vol.153, No.1, p.11-15 (2006)
[2]Heinzea?B.,Lutza?J.,Felslb?H.P.,Schulze?H.J.,“Ruggedness?Analysis?of3.3kV?High?Voltage?Diodes?Considering?Various?Buffer?Structures?and?Edge?Terminations”,Microelectronics?Journal?Vol.39,p.868-877(2008)
[3] Lutz J., Baburske R., Chen R.M., Heinze B., Domeij M., Felsl H.P., and Schulze H.J., " The nn+-Junction as the Key to Improved Ruggedness and Soft Recovery of Power Diodes ", IEEE Transactions on Electron Devices, Vol.56, No.11, p.2825-2832 (2009)
[4]Mauder?A.,Schulze?H.J.,Hille?F.,Schulze?H.,Pfaffenlehner?M.,Schaffer?C.,Niedernostheide?F.J.,“Semiconductor?Device?and?Fabrication?Method?Suitable?Therefor”US?Patent?No:US7514750B2(2009)
[5]Klug?J.N.,Lutz?J.,Meijer?J.B.,“n-type?doping?of?silicon?by?proton?Implantation”Proceedings?of?the14th?European?conference?on?Power?Electronics?and?Applications(EPE2011),p.1-7(2011)
[6]Rahimo?M.,Corvasce?C.,Vobecky?J.,Otani?Y.,Huet?K.,“Thin-wafer?silicon?IGBT?with?advanced?laser?annealing?and?sintering?process”IEEE?Electron?Device?Letters,vol.33,No.11,p.1601-1603(2012)
[7] Siemieniec R. and Lutz J. " Axial lifetime control by radiation induced centers in fast recovery diodes " Proc.ISPSD-2002, p.83-90 (Prague2002)
Claims (14)
1. manufacture a method for diode, wherein process substrate wafer to produce doped layer structure, described wafer doping has n
-impurity and there is front surface and back surface, described method comprises: on described front surface, form anode; Grind described back surface to reduce the thickness of described wafer; Utilize n
+impurity adulterates to described back surface and by n described in laser anneal activation
+impurity is to form cathode layer; Utilize repeatedly N-shaped H+implantation through described back surface and described H+implantation is annealed at the inside of described cathode layer formation resilient coating.
2. method according to claim 1, wherein said substrate wafer is silicon wafer.
3. method according to claim 1 and 2, wherein said H+implantation is annealed by laser.
4. method according to claim 3, comprises the described wafer of heating to the temperature lower than temperature required rising of annealing, and uses laser annealing to the wafer through heating.
5. method according to claim 4, comprises the described wafer to 300 of heating DEG C to 350 DEG C.
6. method according to claim 1 and 2, is included in stove and anneals to described H+implantation at lower than the temperature of 500 DEG C.
7. method according to claim 6, wherein said temperature is 450 DEG C.
8. the method according to the aforementioned claim of any one, comprises and utilizes boron injection and thermal diffusion to form described anode on described front surface.
9. the method according to the aforementioned claim of any one, comprises and utilizes arsenic or phosphorus to inject to form described n to described back surface
+impurity.
10. the method according to the aforementioned claim of any one, comprises and on described front surface, performs photoetching process before the grinding.
11. methods according to the aforementioned claim of any one, are included in deposition of thin Ti layer on described cathode layer and carry out laser annealing to described Ti layer.
12. 1 kinds of methods manufacturing semiconductor device, comprise by impurity being injected in substrate wafer to form doped layer in described wafer, then laser annealing is carried out to described impurity, it is characterized in that the temperature described wafer being preheated to the rising lower than annealing temperature before applying described laser annealing.
13. methods according to claim 12, comprise the described wafer to 300 of heating DEG C to 350 DEG C.
14. methods according to claim 12 or 13, wherein form described doped layer by repeatedly H+implantation.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GBGB1310471.6A GB201310471D0 (en) | 2013-06-12 | 2013-06-12 | Method of fabricating diodes |
| GB1310471.6 | 2013-06-12 | ||
| GB1407633.5 | 2014-04-30 | ||
| GB1407633.5A GB2515631B (en) | 2013-06-12 | 2014-04-30 | Method of fabricating diodes |
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| CN104241121A true CN104241121A (en) | 2014-12-24 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105321817A (en) * | 2015-10-26 | 2016-02-10 | 株洲南车时代电气股份有限公司 | Diode and cathode metallization method therefor |
| CN107564806A (en) * | 2016-07-01 | 2018-01-09 | 英飞凌科技股份有限公司 | Reduce the impurity concentration in semiconductor body |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6482681B1 (en) * | 2000-05-05 | 2002-11-19 | International Rectifier Corporation | Hydrogen implant for buffer zone of punch-through non epi IGBT |
| DE102004047749B4 (en) * | 2004-09-30 | 2008-12-04 | Infineon Technologies Austria Ag | Semiconductor device diode and IGBT as well as suitable manufacturing process |
| US7728409B2 (en) * | 2005-11-10 | 2010-06-01 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device and method of manufacturing the same |
| WO2009034699A1 (en) * | 2007-09-10 | 2009-03-19 | Panasonic Corporation | Semiconductor device manufacturing method |
| WO2013073623A1 (en) * | 2011-11-15 | 2013-05-23 | 富士電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
-
2013
- 2013-06-12 GB GBGB1310471.6A patent/GB201310471D0/en not_active Ceased
-
2014
- 2014-04-30 GB GB1407633.5A patent/GB2515631B/en active Active
- 2014-06-12 CN CN201410260435.XA patent/CN104241121A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105321817A (en) * | 2015-10-26 | 2016-02-10 | 株洲南车时代电气股份有限公司 | Diode and cathode metallization method therefor |
| CN107564806A (en) * | 2016-07-01 | 2018-01-09 | 英飞凌科技股份有限公司 | Reduce the impurity concentration in semiconductor body |
Also Published As
| Publication number | Publication date |
|---|---|
| GB201310471D0 (en) | 2013-07-24 |
| GB2515631A (en) | 2014-12-31 |
| GB2515631B (en) | 2018-01-03 |
| GB201407633D0 (en) | 2014-06-11 |
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