CN104221129A - 基于外延生长来制造半导体设备的方法 - Google Patents

基于外延生长来制造半导体设备的方法 Download PDF

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CN104221129A
CN104221129A CN201380019784.6A CN201380019784A CN104221129A CN 104221129 A CN104221129 A CN 104221129A CN 201380019784 A CN201380019784 A CN 201380019784A CN 104221129 A CN104221129 A CN 104221129A
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semiconductor
layer
substrate
crystal seed
growth
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孙燕亭
塞巴斯蒂安·卢尔杜多斯
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TANDEM SUN AB
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TANDEM SUN AB
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Abstract

制造半导体设备的方法以及通过其制造的半导体，包括使具备具有非常少晶体缺陷的半导体晶体的突变异质结在异质衬底(50)上从种晶岛状台面上生长，以用作发光和光伏设备。

Description

基于外延生长来制造半导体设备的方法
技术领域
本发明涉及半导体设备和其制造，本发明尤其涉及制造具有异质结构的半导体设备的方法。本发明也涉及由该方法制造的半导体设备。
背景技术
半导体设备可通过例如所谓的“晶片键合”制造。晶片键合是在晶片量级的包装技术，适于例如微机电***(MEMS)、纳米机电***(NEMS)、微电子学和光电子学的制造。典型地，晶片键合确保机械稳定和气密密封封装。典型地，制造的晶片(包括半导体)对于MEMS/NEMS可具有范围从100mm至200mm(从4英寸至8英寸)的直径和至多300mm(12英寸)，用于生产比如微电子学和光电子学的半导体设备。
不幸地，对于一些应用，通过晶片键合制造的半导体设备的成本高并且制造该设备的方法的产率低，原因是在衬底(比如异质衬底)上键合的半导体的有限的可用晶片尺寸。晶片键合也受限于衬底可用的有效晶片尺寸，其通常比常规尺寸的异质衬底更小。半导体材料和异质衬底之间的合适性存在疑问，并且在最坏的情况下可导致材料结合问题。在半导体设备运行期间两个材料之间的结合故障可能是灾难性的。
而且，其他技术已经用于制造半导体设备，比如使用外延技术和尤其的“选择性外延生长”的技术。这在例如“由选择性外延生长制造多层绝缘硅(MultipleLayers of Silicon-on-Insulator Islands Fabrication by Selective Epitaxial Growth),S.Pae,等.IEEE ELECTRON DEVICE LETTERS，VOL.20,NO.5,1999年5月”，IEEE。
发明内容
根据本发明的一方面，提供基于外延生长制造半导体设备的方法。可使用根据本发明方法制造的半导体设备的尺寸仅仅由异质衬底的可用的晶片尺寸决定，其通常对于硅(Si)衬底可以是12英寸大小。而且，由于外延生长固有的特征，半导体材料和异质衬底之间的合适性优于现有技术方法。
本文中，术语“半导体设备”包括任何半导体设备前体，比如半导体衬底，一直到并且包括半导体设备比如准备使用的半导体激光器。
本文中，术语“异质”意思是生长的半导体和衬底由不同的材料制成。
根据本发明的实施方式，提供制造半导体设备，比如半导体衬底的方法。该方法包括下述步骤：在异质半导体衬底的前侧上形成缓冲层和晶种层，随后处理以提供一个或多个晶种岛状台面，其通常在异质半导体衬底上具有特定取向。然后在至少一个晶种岛状台面上形成绝缘掩模层。绝缘掩模层具有设置在晶种岛状台面上的开孔。如果没有，则在绝缘掩模层中设置开孔。然后从绝缘掩模层的开孔使具有彼此生长为一体的连续半导体区域的半导体生长层生长。该生长是选择性的：外延、垂直和横向，其中具有高缺陷密度的第一区域仅仅从开孔垂直生长，同时其他区域生长直到至少一个具有低缺陷密度的半导体区域与半导体衬底的前侧聚结(coalesce)。可通过蚀刻去除半导体生长层的具有高缺陷密度的第一区域和第二区域并且不蚀刻具有低缺陷密度的第三区域，通常制备半导体层来避免被蚀刻以用于半导体设备制造。
这样，可在异质衬底上制造具有异质结构，例如具有低缺陷密度的半导体衬底的半导体设备。
一般而言，台面是具有平台的陆地升高的区域，其所有侧壁由陡峭的悬崖围绕。本文中，术语“台面”意思是半导体衬底上半导体没有被蚀刻的区域。典型地，台面上升高于围绕的半导体衬底，并且升高区域的高度通常是数微米。
这样，提供处理异质衬底的方法，其中半导体材料的晶种岛状台面被绝缘掩模层覆盖，通常绝缘掩模覆盖晶种岛状台面的暴露的表面。在绝缘掩模层中制造开孔。半导体材料的过度生长结晶层生长，填充孔，覆盖晶种岛状台面上的掩模，并且然后横向和向下生长以覆盖异质衬底的围绕晶种岛的暴露的表面。通常通过蚀刻去除生长的半导体层中具有高缺陷密度的区域(一个或多个)并且在蚀刻时留下具有低缺陷密度的区域(一个或多个)，或换句话说，它们不被蚀刻，并且在异质衬底上制造包括具有低缺陷密度的半导体材料模板的半导体设备。
本文中，术语“模板”意思是具有制备的用于制造半导体设备比如半导体激光器二极管设备的半导体层的任何种类的半导体前体。
根据本发明的另一实施方式，提供制造半导体设备的方法，其中在其上形成绝缘掩模层，并且在绝缘掩模层中制造开孔，就是说，在台面岛的顶部。然后具有彼此生长为一体的连续半导体区域的半导体生长层从绝缘掩模层的开孔，外延、垂直和横向地生长，其中具有高缺陷密度的第一区域仅仅从开孔垂直生长，同时其他区域生长直到至少一个具有低缺陷密度的半导体区域与绝缘掩模层72聚结。
典型地，方法中一直到晶种岛状台面形成，缓冲层、晶种层和晶种岛状台面形成的步骤对于根据本发明方法的各种实施方式是相同的。
根据本发明的另一实施方式，提供通过上面公开的方法制备的半导体设备。
根据本发明的另一方面，具有低缺陷密度的半导体异质结构包括在通过上面公开的方法制造的异质衬底上的半导体层。该衬底可以是具有间接带隙的半导体。所述半导体层可具有直接带隙。异质衬底半导体材料的导带和价带边缘能量比半导体层的更高。组件半导体材料形成II型异质结，其中电子限制在具有直接带隙的半导体层侧并且空穴限制在具有间接带隙的异质衬底侧。电子和空穴由于隧道效应在异质结的界面辐射复合(recombine radiatively)并且可发射比两种异质结成分材料的带隙更低能量的光。该II型异质结可用于吸收具有比组件半导体的带隙更低能量的光子。间接半导体价带中的电子被激发至直接半导体的导带。
本文中，术语“异质结”意思是在异质晶体半导体的两个层或区域之间出现的界面。这些半导体材料具有不同的带隙。多个异质结在设备中组合在一起称为“异质结构”，尽管两个术语通常交换使用。本文中，两个术语适用于本发明而不缩减保护范围。本文中，术语“异质结”的另一定义是任何两个固态材料，包括晶体和无定形结构的金属、绝缘体、快离子传导和半导体材料之间的界面。
根据本发明的另一方面，提供多结太阳能电池，其包括硅子电池和具有与太阳光谱匹配的带隙的半导体的子电池，例如GaAs、GaInP、GaP和Si子电池。电串联连接子电池并且两个电极用于连接多结太阳能电池至负荷。Si子电池被加工进入Si衬底。在具有Si子电池的Si衬底的顶部，通过本发明的方法来生长半导体模板。由具有适当的带隙半导体制造的子电池在Si上的半导体模板上生长。为了进一步增加效率，可提供具有不同带隙的更多的子电池。
根据本发明的另一方面，提供多结太阳能电池，其包括硅子电池和具有与太阳光谱匹配的带隙的半导体子电池，例如GaAs、GaInP、GaP和Si子电池。Si子电池和其他子电池是电隔离的并且以分开的电极对连接至负荷。Si子电池被加工进入Si衬底。在具有Si子电池的Si衬底顶部，通过本发明的方法使半导体的异质结构生长。由具有适当的带隙的半导体制造的子电池在Si上的半导体异质结构上生长。
附图说明
现参考附图详细描述本发明的实施方式，其中：
图1a是被加工的半导体衬底的示意性截面图，用于图解根据本发明的实施方式制造半导体设备的方法；图1b是图1a中显示的半导体衬底的俯视图；
图2a至2j是图1a-b中显示的半导体衬底的示意性截面图，用于图解根据本发明实施方式的方法；
图3a至3f是半导体衬底的示意性截面图，用于图解根据本发明的另一实施方式制造半导体设备的方法；
图4是图解通过图1a-b中显示和描述的方法制造的包括具有直接/间接带隙的异质结的包括半导体设备的半导体激光器二极管的示意性截面图；
图5是图4包括GaxIn1-xAsyP1-y和Si之间II型带阶(band lineup)的半导体异质结的带图；
图6示意性图解在具有II型带阶并且包括n-型GaxIn1-xAsyP1-y和p-型Si异质结在正向偏压下的发光机制；
图7是示意性图解多结太阳能电池的截面图，所述多结太阳能电池包括在用根据本发明实施方式的方法制造的GaAs/Si设备上支撑的GaInP、GaAs和Si子电池；
图8a至8b是显示按照步骤顺序形成Si太阳能子电池的方法的示意性截面图；
图9图解根据图1a-b和2a-j显示的实施方式的方法的流程图；
图10图解根据图3a-f显示的实施方式的方法的流程图；和
图11是示意性图解多结太阳能电池的截面图，所述多结太阳能电池包括在根据本发明的另一实施方式的方法制造的GaAs/Si衬底上支撑的GaInP、GaAs和Si子电池。
具体实施方式
下面将参考附图描述本发明。遍及附图，相同或类似部分主要由相同的参考数值标注。
图1a图解通过根据本发明实施方式的方法制造的半导体设备，这里为衬底的示意性截面图。本文中，也参考在流程图中一步一步图解该方法的图9。首先，提供由例如Si制造的异质衬底50(图9中未显示)。在100a，形成由例如GaAs制造的缓冲层52，例如在低温下通过分子束外延(MBE)或MOVPE在衬底50的前侧50a上生长。本文中，术语“MOVPE”是金属有机化学气相沉外延(MOVPE)的首字母缩写，也称为有机金属气相外延或金属有机化学气相沉积(MOCVD)。然后在100a，在缓冲层52的顶部，形成通过例如MOVPE生长由例如InP制造的晶种层54。缓冲层52的厚度可为100nm或更厚并且晶种层54的厚度可为1μm或更厚。因为Si和InP之间大的晶格失配，晶种层54可具有高的缺陷密度，包括缺陷比如贯穿位错和堆垛层错。在100b，通过常规的光刻和蚀刻处理晶种层54和缓冲层52至一个或多个晶种岛状台面51，仅仅显示了其一个台面51。然后，在101，例如通过PECVD(等离子体增强的化学气相沉积)沉积形成绝缘掩模层62，比如选择性生长掩模层，其由例如具有或更大厚度的SiO2层制造。处理绝缘掩模层62以覆盖台面51的顶面(参考图2b更详细地显示)和侧壁(参考图2b更详细地显示)，其中暴露未被台面51或绝缘掩模层62覆盖的衬底50的表面部分50a。然后，在102，在绝缘掩模层62中制造开孔58并且晶种层54的表面部分54a暴露在开孔58中。然后，在103，使由例如InP制造的半导体生长层80从开孔58，即从台面51上晶种层54暴露的表面部分54a生长，例如通过使用气态III和V族元素源。半导体生长层80首先垂直生长，以形成第一半导体区域80I。晶种层54中的位错将生长进入第一半导体区域80I并且延伸至生长的半导体生长层80生长的外表面。当生长的半导体生长层80比绝缘掩模层62的厚度更厚时，生长在绝缘掩模层62上横向延伸并且形成第二半导体区域80II。第二半导体区域80II中的缺陷密度比晶种层54中的缺陷密度更低。尤其，紧邻绝缘掩模层62的半导体生长层80的第三半导体区域80III比靠近第二生长区域80II中的晶种层54的表面部分54a的第一生长区域80I具有更高的晶体质量。这由整个的第一半导体区域(80I，和部分第二区域80II指示，而不被倾斜划线的第三半导体区域80III指示，并且标记的“位错”旨在显示位错不存在第三半导体区域80III中，而是仅仅存在第一和第二半导体区域80I和80II中。当半导体生长层80继续横向生长并且超过绝缘掩模层62覆盖的台面51的边缘时，半导体层80将横向和垂直生长，并且朝着衬底50的前侧50a，其将形成半导体生长层80的第三半导体区域80III。第三半导体区域80III中的生长可视为从紧邻第二生长区域80II中绝缘掩模层62的半导体生长层80的接种，其具有高晶体质量。另外，第三生长区域80III中半导体生长层80的生长方向与源自晶种层54的贯穿位错的方向相反。在第三半导体区域80III中的半导体生长层80的生长所以具有非常低的缺陷密度。当半导体生长层80继续生长，在紧邻台面51的半导体层81中产生半导体生长层80和衬底50之间的接触，并且半导体生长层80的生长在衬底50上横向延伸。这将如下更详细描述和显示。
典型地，由多个台面提供多个接触。因为半导体生长层80不直接沉积在衬底50上，而是通过同质外延机制，在衬底50和半导体生长层80中的第三半导体区域80III之间的界面50a没有出现位错，比如错配位错和相关的贯穿位错。
在图1至6中，仅仅显示多个台面51的一个作为例子，但是本发明绝不仅仅限于一个台面51。
异质衬底50不具体限于上述例子，只要其由与生长的半导体生长层80不同的材料制造。例如，由Si制造的衬底50可用于在III-V半导体上生长；绝缘衬底，如具有C平面((0001)平面)、R平面((1)平面)或A平面((11)平面)作为主表面的蓝宝石衬底或尖晶石(MgAl2O4)，以及SiC(包括6H、4H和3C)、ZnS衬底、GaAs衬底或Si衬底可用于氮化物半导体的生长。
如在图1b的左侧图可见，为了半导体生长层80在垂直生长速度和横向生长速度之间具有高纵横比，根据本发明的实施方式需要仔细选择晶种层54和缓冲层52的台面51的取向角α至特定的取向角α。
例如，为了GaxIn1-xAsyP1-y(0<x<1；0<y<1)在(001)Si衬底上的生长，台面51必须沿着从晶体方向<110>偏离的取向角α来取向。根据实施方式，取向角α可在0至±45度之间。典型地，根据衬底的晶面和生长参数，比如温度、掺杂剂、压力等选择取向角α。根据本发明的实施方式，在晶种岛状台面51顶部60的绝缘掩模层62中的孔58与台面51以相同方向取向。
图2a至2g是根据本发明的实施方式基本上一步一步进一步显示制造半导体方法的原理的截面图，其中少数步骤组合显示。在图2a至2g中，显示如何制造包括半导体衬底50和在半导体层上生长的具有非常低缺陷密度的失配晶格的异质结构的工艺流程。如图2a中可见，在100a，形成由例如GaAs制造的缓冲层52，例如通过MOPVE在低温下生长，或已经生长在衬底50，比如(001)Si衬底上。由例如InP制造的晶种层54通过MOVPE生长，或已经连续生长并且厚度可为约2μm。由例如SiO2或SiNx制造的保护性台面掩模56通过PECVD沉积或已经沉积并且通过光刻图案化为多个条纹。典型地，保护性台面掩模56的厚度可大于并且宽度对应于期望的台面宽度。
如图2b中显示，在100b，通常通过干法蚀刻将晶种层54和缓冲层52处理或已经处理为多个台面51，这里为两个。由例如Si3N4制造的绝缘掩模层62已经在衬底50和保护性台面掩模56上形成，并且通常通过PECVD沉积。绝缘掩模层62的厚度可大于
如图2c中所显示，通过活性离子蚀刻反应器中的SF6和CH4蚀刻，或已经蚀刻绝缘掩模层62。化学物质CHF3可也用于在活性离子蚀刻反应器中来蚀刻绝缘掩模层62。绝缘掩模层62被从台面51的顶面60和衬底50完全蚀刻，然而通过例如在蚀刻期间形成的聚合物保护在台面51的侧壁60a、b的绝缘掩模层62并且在蚀刻之后是完整的。因此，台面51的顶面60和衬底50的前侧50a可被暴露。衬底50的前侧50a可通过比如用绝缘掩模层62的光刻胶回流和化学蚀刻或干法蚀刻的光刻方法而被暴露。
如图2d中所显示，在102通过光刻和蚀刻在绝缘掩模层62中产生或已经产生多个孔58。如图2e中所显示，在103，在氢化物气相外延(HVPE)中进行由例如InP制造的外延半导体生长层80的生长。在衬底50进入HVPE生长室之前适当清洁由例如Si制造的衬底50的前侧50a。H2SO4:H2:O2和NH4OH:H2O2的溶液用于移除有机杂质和颗粒。在湿化学非原位清洁方法之后，由Si制造的衬底50浸渍在1HF:10H2O的溶液中10秒以移除氧化物。作为例子，HVPE生长室中的生长温度是620℃并且压力是20mBar。利用对于本领域技术人员显而易见的充分生长时间，来自紧邻台面51的选择性生长将产生宽的第三半导体区域80III，其将聚结，以在衬底50的前侧50a上形成连续生长的半导体层81。
如图2f中所显示，通过例如化学机械蚀刻，半导体生长层80的垂直和横向生长部分被蚀刻。蚀刻过程在生长层的顶面60停止。生长的半导体层81的表面81a，其是半导体生长层80的第三半导体区域80III的垂直生长，进一步抛光成适于外延生长的表面，通过本领域技术人员本身已知的抛光方法，该抛光方法提供低的来自抛光的金属污染并且表面粗糙度为本文中，适于外延生长的意思是适于外延生长的表面上的碳和天然氧化物层可通过MOVPE反应器中的原位清洁去除。
如图2g中可见，根据本发明的实施方式，在生长的半导体层81已经被光刻胶保护之后，晶种层54和缓冲层52的台面51以及绝缘掩模层62通过化学蚀刻被蚀刻，或已经被蚀刻。生长的半导体层81具有非常低的缺陷密度并且在半导体层81和衬底50的前侧50a之间形成突变异质结105。该异质结105可用于半导体设备来为活性结构，例如作为激光二极管或发光二极管的发光区域和光敏半导体设备(比如光电二极管、太阳能电池或光检测器)的光子的吸收区域(吸收具有比组件半导体更低能量的光子)。该异质结105可可选地用于制造雪崩光电二极管，其中生长的半导体层81配置为用于光吸收并且异质衬底50用于电子碰撞电离。生长的半导体层81可也用作衬底用于制造半导体设备制造，例如由III-V半导体在硅衬底50上制造的激光器二极管、光电二极管、高速场效应晶体管(FET)。其他例子是用于电子器件的高功率电子设备，其在硅上具有宽带隙GaN材料。
图2h至2j是旨在显示根据本发明的实施方式在波纹异质衬底表面50上制造半导体方法应用截面图。如图2h中所显示，在异质衬底50的前侧50a上制造多个波纹70，然后制造生长的半导体层81。波纹70可具有任何种类的形状、维度和深度。波纹70可以以任何种类的方式在异质衬底的前侧50a上重复。图2i图解沿着提供波纹表面波纹70的异质衬底的线A-A’的横截面。制造在图2e至2g中显示的半导体层81的方法步骤可也在异质衬底50的波纹表面上进行。生长的半导体层81然后将填充异质衬底50上的波纹70，如图2j中所显示。
图3a至3f是显示可选的根据本发明的另一实施方式制造半导体设备的方法的截面图。在此，也参考图10，其是图解该方法步骤的流程图。显示制造异质结构的工艺流程，所述异质结构包括异质衬底50、绝缘掩模层72和以低的缺陷密度生长的半导体层91。
如图3a中所显示，在100a，通过MOPVE在低温下在衬底50，比如(001)Si衬底上形成由例如GaAs制造的缓冲层52。通过MOVPE使由例如InP制造的晶种层54连续生长并且厚度可为约2μm。在101，通过PECVD沉积由例如SiO2制造的保护性台面掩模56并且通过光刻图案化为条纹，显示了其中两个。台面掩模56的厚度可大于
如图3b中所显示，在100b，在缓冲层52和晶种层54通过光刻和蚀刻方法，例如，活性离子蚀刻处理成台面51之后，在101b，在整个衬底50上通过PECVD沉积绝缘掩模层，或绝缘体72，例如Si3N4。如图3c中所显示，在102，在缓冲层52和晶种层54顶部的绝缘掩模层72中产生孔58b，以暴露晶种层54的表面区域54a。
如图3d中所显示，在103，通过氢化物气相外延(HVPE)生长由例如InP制造的半导体层90。在充分的生长时间之后，来自紧邻台面51的选择性生长将结合，以形成均匀生长的半导体层90。
如图3e中可见，半导体层90的垂直和横向生长部分通过例如化学机械蚀刻被蚀刻。蚀刻在绝缘掩模层72的表面72a停止。生长的半导体层91的表面91a被抛光至适于外延生长。
如图3f中可见，晶种层54和缓冲层52的台面51以及绝缘掩模层72的侧壁70a、b在生长的半导体层91被光刻胶保护，或已经被光刻胶保护之后被蚀刻并且通过光刻处理。从而制造了异质结构，其包括异质衬底50、绝缘掩模层72和具有非常低缺陷密度的生长的半导体层91。
从上面的说明显而易见，通过本发明的方法生长的半导体层91具有非常少的缺陷，并且可有效用作半导体设备，比如衬底用于在其上支撑预定的半导体设备，提供“绝缘体结构上的半导体”。例如，“绝缘体结构上的半导体”具有低寄生电容的优势，其与现有技术结构相比提供优异的结构用于高速电子设备。
不具体限制在本发明的半导体结构上支撑的预定的半导体设备，只要其具有预定的设备功能，典型地如异质结，并且包括激光器二极管设备结构、多结太阳能电池设备等。但是，设备不限于任何提及的这些例子。
图4是示意性截面图，其显示在根据本发明制造的半导体设备上形成的激光器二极管(LD)设备。如图4中所显示，半导体衬底50在室温下由退化掺杂的p-型Si制造。生长的半导体层81由硫掺杂或未掺杂的GaxIn1-xAsyP1-y(0<x<1；0<y<1)构成并且通过根据本发明实施方式的方法制造。GaxIn1-xAsyP1-y半导体层81的厚度<2μm。未掺杂的GaxIn1-xAsyP1-y层81进一步通过n型杂质(例如S)的扩散或注入来掺杂，以在室温下具有退化的掺杂剂浓度。在半导体层81上形成优选地由掺杂n-型杂质(例如S)的n-型InP制造的n-侧接触层27。在n-侧接触层27的整个表面上形成n-电极8。衬底50变薄至100μm。衬底50的后侧50b用p-型掺杂剂(比如B或Ga)较浅地注入，以当退火和掺杂剂活化时形成重掺杂的后侧接触区域6。在后侧接触区域6上形成p-侧电极2。通过切割形成激光器二极管的小面并且从设备的边缘发射光。如图4中所显示，在前侧50a上在衬底50和生长的半导体层81之间形成突变异质结105。
如图5中所显示，异质结105可具有II型错列的带阶(staggered band lineup)，如果衬底50由Si制造并且生长的半导体层81由GaxIn1-xAsyP1-y制造，其中选择合金组合物比x和y以使生长的半导体层81的电子亲和性高于Si的电子亲和性4.01eV。这样的材料的组合使得Si的导带和价带边缘相对于GaxIn1-xAsyP1-y向上移动，并且在异质结105界面处的残留隙被标记为“Er”。如图6中所显示，n-型GaxIn1-xAsyP1-y半导体层81和p-型Si衬底50都是退化掺杂的。在正向偏压Vapp下，在异质结105界面出现带隙弯曲。在界面的两侧形成两种类型的载流子约束阱。与阱形成相关，游离的电子和空穴在阱中积聚。通过本发明获得的GaxIn1-xAsyP1-y/Si异质结的界面充分突变。因为横跨界面的隧道效应，电子和空穴的波函数将强烈重叠。空间上分开的阱中的高浓度的积聚电子-空穴对可具有有效的辐射复合，尽管Si是间接-带隙半导体。
图7示意性图解根据本发明的实施方式在半导体衬底上形成的多结太阳能电池设备的横截面，其包括Si子电池180、GaAs子电池202和InGaP子电池206。在如图2b中显示的缓冲层52和晶种层54在MOVPE中生长之前，将Si衬底50处理成Si子电池，如图8a和8b中显示。如图8a中所显示，正面300a由n-型掺杂剂比如P或As的束310来注入。通过在升高温度下的退火和掺杂剂活化形成n-型发射器区域300。其他可选方式可包括扩散而不是注入和退火。发射器区域300的深度较薄并且不大于1μm。Si衬底的正面300a进一步用更高剂量的n-型掺杂剂束320通过用退火和掺杂剂活化或扩散来注入掺杂，以形成重掺杂表面区域305以利于电接触，如图8b中显示。重掺杂表面区域305的厚度较薄并且不大于100nm。因此，形成硅p-n太阳能子电池180。通过参考图1a、b和2a-g描述的本发明的方法，在由p-型Si制造的具有p-n太阳能子电池180的衬底50的顶部生长p+-GaAs半导体层81。在通过根据本发明的实施方式的方法生长p+-GaAs半导体层81之后，GaAs子电池202和InGaP子电池206可在p+-GaAs半导体层81上制造，就如在常规的三重结太阳能电池中一样。通过由重掺杂n+和p+InGaP制造的隧道结204连接GaAs子电池和InGaP子电池。由n+-InAlP制造的窗口层208和由n+-GaAs制造的接触层210在InGaP子电池的顶部生长。n+-GaAs接触层210处理为具有孔(灰色区域)，其中沉积抗反射涂层211。在n+-GaAs接触层210的顶部，形成n触点212。在使Si衬底50变薄小于100μm之后，p-型Si衬底50的后侧50b用p-型掺杂剂比如B或Ga较浅地注入，以当退火和掺杂剂活化时形成重掺杂后侧接触区域6。在后侧接触区域6上形成p-侧电极6a。
图11示意性显示根据本发明的实施方式的多结太阳能电池设备的横截面，其包括在半导体设备50上形成的Si子电池180、GaAs子电池202和InGaP子电池206，这里，参考图3a-3f显示和描述的本发明第二种实施方式的衬底。在缓冲层52和晶种层54在MOVPE中生长之前，如图2b中显示，Si衬底50处理成Si子电池，如图8a和8b中显示。如图8a中所显示，正面300a通过束310用n-型掺杂剂比如P或As来注入。通过在升高的温度下退火和掺杂剂活化形成n-型发射器区域300。其他可选方式可包括扩散而不是注入和退火。n-型发射器区域300的深度较薄并且不大于1μm。Si衬底的正面300a进一步用更高剂量的n-型掺杂剂束320通过用退火和掺杂剂活化或扩散来注入掺杂，以形成重掺杂表面区域305以利于电接触，如图8b中显示。重掺杂表面区域305的厚度较薄并且不大于100nm。这样，形成硅p-n太阳能子电池180，在其上提供绝缘层，或绝缘体72。通过参考图1a-b和2a-g描述的本发明的方法使p+-GaAs半导体层91在具有p-n太阳能子电池180的由p-型Si制造的衬底50的顶部生长。在p+-GaAs半导体层91通过根据本发明的实施方式的方法生长之后，可在p+-GaAs半导体层91上制造GaAs子电池202和InGaP子电池206，就像常规的三重结太阳能电池一样。通过由重掺杂n+和p+InGaP制造的隧道结连接GaAs子电池和InGaP子电池204。由n+-InAlP制造的窗口层208和由n+-GaAs制造的接触层210，在InGaP子电池204的顶部生长。n+-GaAs接触层210处理为具有孔211，其中沉积抗反射涂层。在n+-GaAs接触层210的顶部，形成n-触点IIIV212。通过堆叠外延层至p+-GaAs半导体层91的表面形成开孔并且从而暴露重掺杂表面区域n+-Si305。在p+-GaAs半导体91的顶部形成p触点IIIV213并且在表面区域n+-Si305的顶部形成n-触点Si214。在使Si衬底50变薄小于100μm之后，p-型Si衬底50的后侧215用p-型掺杂剂比如B或Ga较浅地注入，以当退火和掺杂剂活化时形成重掺杂后侧接触区域6。在后侧接触区域6上形成p-侧电极p触点Si216。将n/p触点Si214、216和n/p触点IIIV212、213分别连接至负荷。所谓“化合物半导体”的硅底部电池和子电池之间的电流匹配不是必要的。硅子电池的高短路电流将有助于总体转化效率更有效。
尽管本发明前述的说明书能够使得本领域技术人员利用和使用其目前认为最佳的模式，本领域技术人员将理解和认识存在本文具体实施方式、方法和实施例的变型、组合和等价物。所以本发明不应被上述实施方式、方法和实施例限制，而是仅仅由权利要求的范围限定。
该方法可用于在硅衬底上制造化合物半导体发光设备和光伏设备。

Claims (13)

1.制造具有异质结构的半导体设备的方法，所述方法包括下述步骤：
-在异质半导体衬底(50)的前侧(50a)上形成(100a)缓冲层(52)和晶种层(54)，
-处理(100b)以提供所述缓冲层(52)和所述晶种层(54)的至少一个晶种岛状台面(51)，
-在所述至少一个晶种岛状台面(51)上形成(101)绝缘掩模层(62、72)，具有开孔(58、58b)的所述绝缘掩模层(62、72)设置在所述晶种岛状台面(51)上，特征在于，
-使具有彼此生长为一体的连续半导体区域(80I、80II、80III)的半导体生长层(80)从所述开孔(58、58b)外延、垂直和横向生长(103)，其中具有高缺陷密度的第一区域(80I)仅仅从开孔(58、58b)垂直生长，同时其他区域(80II、80III)生长直到至少一个具有低缺陷密度的半导体区域(80III)与所述半导体衬底(50)的所述前侧(50a)或所述绝缘掩模层(72)聚结。
2.根据权利要求1所述的方法，包括处理(100b)以在所述衬底(50)上提供具有特定取向(α)的晶种岛状台面(51)。
3.根据权利要求1所述的方法，其中形成(101)所述绝缘掩模层(62、72)以覆盖所述晶种岛状台面(51)的顶面(60)和侧壁(60a、60b)。
4.根据权利要求1或2所述的方法，其中所述半导体生长层(80)在气相中生长(103)。
5.根据权利要求2所述的方法，其中基于衬底的晶面和生长参数选择所述取向(α)，例如在所述衬底的(001)表面上从<110>方向的0至±45°的范围。
6.根据权利要求1所述的方法，其中通过蚀刻去除所述半导体生长层(80)的具有高缺陷密度的第一区域(80I)和第二区域(80II)，并且蚀刻时留下具有低缺陷密度的第三区域(80III)以制备半导体层(81)用于半导体设备制造。
7.根据权利要求6所述的方法，其中所述衬底(50)具有波纹(70)并且所述半导体层(81)填充上述波纹(70)。
8.根据权利要求1所述的方法，所述方法包括下述步骤：
-在半导体衬底(50)的前侧(50a)上形成(101b)绝缘掩模层(72)。
9.根据权利要求8所述的方法，其中通过蚀刻去除具有高缺陷密度的所述第一区域(80I)和第二区域(80II)，并且蚀刻时留下具有低缺陷密度的第三区域(80III)以在上述绝缘掩模层(72)上制备半导体层(91)用于半导体设备制造。
10.由一种方法制造的半导体设备，该方法包括下述步骤：
-在异质半导体衬底(50)的前侧(50a)上形成(100a)缓冲层(52)和晶种层(54)，
-处理(100b)以提供缓冲层(52)和晶种层(54)的至少一个晶种岛状台面(51)，
-在至少一个晶种岛状台面(51)上形成(101)绝缘掩模层(62、72)，具有开孔(58、58b)的绝缘掩模层(62、72)设置在晶种岛状台面(51)上，特征在于，
-使具有彼此生长为一体的连续半导体区域(80I、80II、80III)的半导体生长层(80)从所述开孔(58、58b)外延、垂直和横向生长(103)，其中具有高缺陷密度的第一区域(80I)仅仅从开孔(58、58b)垂直生长，同时其他区域(80II、80III)生长直到至少一个具有低缺陷密度的半导体区域(80III)与所述半导体衬底(50)的所述前侧(50a)或所述绝缘掩模层(72)聚结，其中通过蚀刻去除具有高缺陷密度的第一区域(80I)和第二区域(80II)，并且蚀刻时留下具有低缺陷密度的第三区域(80III)以制备半导体层(81、91)用于半导体设备制造。
11.根据权利要求10所述的半导体设备，其中所述半导体层(81)掺杂n-型杂质，其中所述半导体层(81)设置n-侧接触层(27)和堆叠在所述n-侧接触层(27)上的n-电极(8)，其中衬底(50)的后侧(50b)设置后侧接触区域(6)和堆叠在所述后侧接触区域(6)上的p-侧电极(2)。
12.根据权利要求10所述的半导体设备，其中：
所述衬底(50)具有n-型发射器区域(300)和重掺杂表面区域(305)，其中衬底(50)的后侧(50b)设置后侧接触区域(6)和堆叠在后侧接触区域(6)上的p-侧电极(60a)，且其中所述半导体层(81)是p+-GaAs层，其设置以连续顺序堆叠的层：
-GaAs子电池(202)，
-隧道结(204)，
-InGaP子电池(206)，
-窗口层(208)，
-接触层(210)，
-抗反射涂层(211)，和
-n-触点(212)。
13.根据权利要求10所述的半导体设备，其中
所述衬底(50)具有n-型发射器区域(300)和重掺杂表面区域(305)，并且其中所述衬底(50)在其上设置以连续顺序堆叠的层：
-绝缘掩模层(72)和n-触点(214)，
-p+-GaAs层(91)和p触点(213)，
-GaAs子电池(202)，
-隧道结(204)，
-InGaP子电池(206)，
-窗口层(208)，
-接触层(210)，
-抗反射涂层(211)，和
-n-触点(212)。
CN201380019784.6A 2012-04-13 2013-03-28 基于外延生长来制造半导体设备的方法 Pending CN104221129A (zh)

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