CN104199795A - Bus framework - Google Patents
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- CN104199795A CN104199795A CN201410467523.7A CN201410467523A CN104199795A CN 104199795 A CN104199795 A CN 104199795A CN 201410467523 A CN201410467523 A CN 201410467523A CN 104199795 A CN104199795 A CN 104199795A
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Abstract
The invention provides a bus framework, relates to the technical field of communication buses, and particularly belongs to a high-performance serial bus supporting various main engines. The bus framework is characterized in that the bus framework is provided with three bidirectional signal lines comprising a bus occupation marker line EN, a data line DATA and a clock line CLK; a bus is connected with a positive power source through a pull-up resistor; a signal line hanging connection bus module is provided with a plurality of types of interfaces; and user ends can be in hanging connection with various devices through the bus module. Various types of buses are not required to be mounted when the bus framework is used; the wiring cost is saved; and the bus framework is simple in later maintenance and high in reliability.
Description
Technical field
The present invention relates to communication bus technical field, particularly belong to a kind of high performance serial bus that many main frames are supported that possesses.
Background technology
At present mostly the connection that generally uses is the bus of simple function as SPI order wire, I2C line, Serial Port Line etc. present stage, can not realize plurality of devices carries out work simultaneously, articulates the functions such as multiple bus module simultaneously, in actual use, if need to articulate sensor, realize again serial communication, also will realize the work such as SPI communication time, can only according to circumstances use simultaneously dissimilar bus is installed, just can finish the work, have and install and maintenance complexity, the defects such as maintenance cost height.
Summary of the invention
Object of the present invention is to provide a kind of bus architecture, articulates the equipment of different communication speed, the compatible multiple object that articulates mode, highly versatile to reach realization simultaneously.
A kind of bus architecture disclosed in this invention, is characterized in that, has three bidirectional signal lines, and one is bus busy flag line EN, and one is data line DATA, and also having one is clock line CLK, and bus connects positive supply by pull-up resistor; Above-mentioned signal wire articulates bus module, and the interface of number of different types is set on bus module; User side articulates various such as equipment such as sensor, main frame, timers by bus module.
In the time that bus is idle, EN line is high level, and DATA line and CLK line are also given tacit consent to and be set to high level, now, are articulated to the low level that the arbitrary equipment in bus is exported, and all will make corresponding bus signals step-down, and bus module and respective bus are wired AND relations; Each equipment of receiving in bus has unique 8 bit address.
The data mode of above-mentioned bus architecture:
1, send opening flag: bus, sending before data, first drags down EN line, makes bus in " doing " state, and now other main process equipment in bus cannot use bus;
2, transmit data:, during high level state data bit is put on DATA line at CLK, maintains the data in DATA bus, until after CLK high level arrives next time, again another one data are put in DATA bus, so repeatedly, until by all Data Transfer Dones; After Data Transfer Done, DATA line and CLK line are all drawn high;
3, end-of-data mark: when after Data Transfer Done, before next CLK clock negative edge arrives, EN bus is drawn high, CLK keeps 1-2 clock period, wait in the meantime the ack signal that DATA line returns simultaneously, if do not wait until ack signal, data send unsuccessfully, juxtaposition respective bus error flag;
4, the packet sending contains following components: destination host address+source host address+valid data+checking data;
5, the order that data send is:
<1> first sends the low level of byte, then sends a high position for byte;
<2> first sends low byte data, then sends high byte data.
The data receive mode of above-mentioned bus:
1, be articulated in all other main frames in non-transmission state in bus, receive bus data at bus clock CLK negative edge, and judge whether address conforms to self address, if conformed to, receive remaining data, if do not conformed to, the data that removing has received automatically, empty reception buffer zone;
2, when judging that address conforms to, and receive after remaining data, to carry out immediately data check, if check results is correct, in the time that upper once clock negative edge arrives, to drag down immediately one or several bus clock semiperiod of DATA line, as the correct ack signal receiving of data, transmit leg judges according to this signal whether data are successfully sent completely.
Seizing and arbitration mechanism of above-mentioned bus:
1, need to use the main frame of bus first to detect EN line, if bus " is hurried ", random wait very short time testbus again again, so repeatedly, until bus " free time " detected or reach the upper limit of the detection number of times of setting, till automatically abandoning this bus request;
If 2 successfully detect bus " free time ", testbus again and then, if still " free time ", one or several bus clock semiperiod of time delay, testbus again, if now bus is still " free time " state, drag down EN line, seize bus success;
If 3 do not detect all the time bus " free time " in 1, bus request failure, abandons this bus request, juxtaposition respective bus error flag automatically;
If 4 detect the bus being no less than the once signal that " does " in 2, bus request failure, abandons this bus request juxtaposition respective bus error flag automatically;
The length of the packet that 5, any main frame transmits is all conditional, can not exceed the maximum length that allows;
6, any main frame, completing after the transmission of a packet, must be abdicated bus, as need continue to send data, must again participate in the competition of bus.
The MODE pin of bus module is pulled to low level, can be configured the mode of operation of bus, directly MODE pin is set to high level, bus module enters data penetration transmission pattern, and the data between transmit leg and take over party transmit complete transparence transmission; Bus module can access at any time and remove bus, without the moving process of power-off restarting, the access of bus with remove the just normal work of the miscellaneous equipment in communication that do not affect.
The invention has the beneficial effects as follows and realized the advantage compatibility to of the bus of current different communication mode above common bus, overcome its intrinsic deficiency simultaneously, the bus module being articulated in bus can have difference in functionality, different transmission speed requirements, the different modes that articulates, do not limit to single communication speed, the single mode that articulates, highly versatile, have avoided that various types of buses are installed while use, saved wiring cost, later maintenance is simple, reliability is high good effect.
Brief description of the drawings
Accompanying drawing part further discloses the specific embodiment of the present invention, below in conjunction with accompanying drawing, the present invention is described in further detail,
Fig. 1 is bus structure schematic diagram of the present invention;
Fig. 2 is bus timing figure of the present invention.
Embodiment
As shown in Figure 1, a kind of bus architecture provided by the present invention, has three bidirectional signal lines, and one is bus busy flag line EN, and one is data line DATA, and also having one is clock line CLK, and bus connects positive supply by pull-up resistor; Above-mentioned signal wire articulates bus module, and the interface of number of different types is set on bus module; User side articulates various such as equipment such as sensor, main frame, timers by bus module.
As shown in Figure 2, camber line is the signal that data receiver module is sent with a left side, camber line the right is that the ack signal that feeds back of take over party is in the time of the bus free time, EN line is high level, DATA line and CLK line are also given tacit consent to and are set to high level, now, are articulated to the low level of the arbitrary device output in bus, all will make corresponding bus signals step-down, bus module and respective bus are wired AND relations.
The data mode of above-mentioned bus architecture:
1, send opening flag: bus, sending before data, first drags down EN line, makes bus in " doing " state, and now other main process equipment in bus cannot use bus;
2, transmit data:, during high level state data bit is put on DATA line at CLK, maintains the data in DATA bus, until after CLK high level arrives next time, again another one data are put in DATA bus, so repeatedly, until by all Data Transfer Dones; After Data Transfer Done, DATA line and CLK line are all drawn high;
3, end-of-data mark: when after Data Transfer Done, before next CLK clock negative edge arrives, EN bus is drawn high, keep 1-2 clock period, wait in the meantime the ack signal that DATA line returns simultaneously, if do not wait until ack signal, data send unsuccessfully, juxtaposition respective bus error flag;
4, the packet sending contains following components: destination host address+source host address+valid data+checking data;
5, the order that data send is:
<1> first sends the low level of byte, then sends a high position for byte;
<2> first sends low byte data, then sends high byte data;
6, verification type can be: CRC16, CRC32 or verification and mode etc. all can, do not limit to this type of verification mode, can select arbitrarily as required;
After data send successfully, serial ports can return to SUCCESS immediately, represents that data send successfully;
After data send unsuccessfully, serial ports can return to ERROR immediately, represents that data send unsuccessfully.
As shown in Figure 2, the data receive mode of bus adopts:
1, be articulated in all other main frames in non-transmission state in bus, receive bus data at bus clock CLK negative edge, and judge whether address conforms to self address, if conformed to, receive remaining data, if do not conformed to, the data that removing has received automatically, empty reception buffer zone;
2, when judging that address conforms to, and receive after remaining data, to carry out immediately data check, if check results is correct, in the time that upper once clock negative edge arrives, to drag down immediately one or several bus clock semiperiod of DATA line, as the correct ack signal receiving of data, transmit leg judges according to this signal whether data are successfully sent completely.
Described ack signal, refer to send data transmit leg by send data when bus is available free, the data that will send send in bus, take over party receives after the clock signal of bus, after comparison finds that address is take over party's address, can feed back an ack signal to bus, bus can send the data to take over party.
Each device of receiving in bus has unique 8 bit address, can articulate altogether and can reach at most 256 main process equipments in bus; Can free communication between each main frame, regardless of main frame and slave, between them, be equality to the use of bus, bus arbitration is by completing by competition between each main frame.
Seizing with arbitration mechanism of bus comprises the steps:
1, need to use the main frame of bus first to detect EN line, if bus " is hurried ", random wait very short time testbus again again, so repeatedly, until bus " free time " detected or reach the upper limit of the detection number of times of setting, till automatically abandoning this bus request;
If 2 successfully detect bus " free time ", testbus again and then, if still " free time ", one or several bus clock semiperiod of time delay, testbus again, if now bus is still " free time " state, drag down EN line, seize bus success;
If 3 do not detect all the time bus " free time " in 1, bus request failure, abandons this bus request, juxtaposition respective bus error flag automatically;
If 4 detect the bus being no less than the once signal that " does " in 2, bus request failure, abandons this bus request juxtaposition respective bus error flag automatically;
The length of the packet that 5, any main frame transmits is all conditional, can not exceed the maximum length that allows; The maximum length that allows is set according to the speed of bus and actual needs, does not limit to a certain value, affects other equipment use buses to prevent from being connected to the packet of the equipment transmission overlength above bus; When having the packets need transmission of overlength, need to be divided into little packet and send data;
6, any main frame, completing after the transmission of a packet, must be abdicated bus, as need continue to send data, must again participate in the competition of bus.
Bus module carries data check function, can support the verification modes such as 8,16,32 CRC check or cumulative sum verification, and for the incorrect data of verification, bus module can abandon misdata automatically, and notifies transmit leg.
The external IO interface of bus is standard asynchronous serial ports, and equipment is connected with bus module by serial ports; The default configuration of standard asynchronous serial ports is: speed: 115200bps; Check bit: nothing; Data bit: 8; Position of rest: 1.As need manual configuration bus module parameter, must first MODE pin be pulled to low level.
The default setting of bus: serial ports speed: 115200bps; Bus Speed 10us/P; Verification mode: 16 cumulative sums; Data transfer mode: transparent transmission; The packet stand-by period: 1ms.
The MODE pin of bus module is pulled to low level, can be configured the mode of operation of bus, the order of supporting at present comprises:
<1>HELP helps and supports
<2>SET ADDRESS arranges local device address
<3>GET ADDRESS obtains local device address
<4>SET BUSRATE arranges local bus speed
<5>SET USARTRATE arranges local serial ports speed
<6>SET TIMEOUT arranges the packet stand-by period
<7>SET DATACHECK arranges data check mode.
After setting completes, MODE pin is set to high level, bus module is by the configuration operation according to new in transparent transmission mode, and the data between transmit leg and take over party transmit complete transparence transmission.Bus module can access at any time and remove bus, without the moving process of power-off restarting; The access of bus with remove the just normal work of the miscellaneous equipment in communication that do not affect.
Serial ports utility command configuration address can, by the toggle switch configuration address being positioned on bus module, also can be passed through in the address of bus.If used toggle switch, bus module can detect toggle switch automatically, and preferentially uses toggle switch.
Each device of receiving in bus has unique 8 bit address, can articulate altogether and can reach at most 256 main process equipments in bus.
Claims (4)
1. a bus architecture, is characterized in that, has three bidirectional signal lines, and one is bus busy flag line EN, and one is data line DATA, and also having one is clock line CLK, and bus connects positive supply by pull-up resistor; Above-mentioned signal wire articulates bus module, and the interface of number of different types is set on bus module; User side articulates various device by bus module;
In the time that bus is idle, EN line is high level, and DATA line and CLK line are also given tacit consent to and be set to high level, now, are articulated to the low level of the arbitrary equipment output in bus, all will make corresponding bus signals step-down, i.e. " line and " relation; Each equipment of receiving in bus has unique 8 bit address.
2. the data mode of bus architecture according to claim 1, is characterized in that,
1), send opening flag: bus, sending before data, first drags down EN line, makes bus in " doing " state, and now other main process equipment in bus cannot use bus;
2), transmit data:, during high level state data bit is put on DATA line at CLK, maintains the data in DATA bus, until after CLK high level arrives next time, again another one data are put in DATA bus, so repeatedly, until by all Data Transfer Dones; After Data Transfer Done, DATA line and CLK line are all drawn high;
3), end-of-data mark: when after Data Transfer Done, before next CLK clock negative edge arrives, EN bus is drawn high, CLK keeps 1-2 clock period, wait at this ack signal that DATA line returns therebetween simultaneously, if do not wait until ack signal, data send unsuccessfully, juxtaposition respective bus error flag;
4) packet, sending contains following components: destination host address+source host address+valid data+checking data;
5) order that, data send is:
<1> first sends the low level of byte, then sends a high position for byte;
<2> first sends low byte data, then sends high byte data.
3. the data receive mode of bus architecture according to claim 1, is characterized in that,
1), be articulated in all other main frames in non-transmission state in bus, receive bus data at bus clock CLK negative edge, and judge whether address conforms to self address, if conformed to, receive remaining data, if do not conformed to, the data that removing has received automatically, empty reception buffer zone;
2), when judging that address conforms to, and receive after remaining data, to carry out immediately data check, if check results is correct, in the time that upper once clock negative edge arrives, to drag down immediately one or several bus clock semiperiod of DATA line, as the correct ack signal receiving of data, transmit leg judges according to this signal whether data are successfully sent completely.
4. seizing and arbitration mechanism of bus architecture according to claim 1, is characterized in that,
1), need to use the main frame of bus first to detect EN line, if bus " is hurried ", random wait very short time testbus again again, so repeatedly, until bus " free time " detected or reach the upper limit of the detection number of times of setting, till automatically abandoning this bus request;
2), if bus " free time " successfully detected, testbus again and then, if still " free time ", one or several bus clock semiperiod of time delay, testbus again, if now bus is still " free time " state, drag down EN line, seize bus success;
3), if bus " free time " do not detected all the time in 1, bus request failure, abandons this bus request, juxtaposition respective bus error flag automatically;
4) if the bus being no less than the once signal that " does " detected in 2, bus request failure, abandons this bus request juxtaposition respective bus error flag automatically;
5), the length of packet that transmits of any main frame is all conditional, can not exceed the maximum length that allows;
6), any main frame is completing after the transmission of a packet, must abdicate bus, as need continue to send data, must again participate in the competition of bus;
The MODE pin of bus module is pulled to low level, can be configured the mode of operation of bus, directly MODE pin is set to high level, bus module enters data penetration transmission pattern, and the data between transmit leg and take over party transmit complete transparence transmission; Bus module can access at any time and remove bus, without the moving process of power-off restarting, the access of bus with remove the just normal work of the miscellaneous equipment in communication that do not affect.
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| CN201410467523.7A CN104199795B (en) | 2014-09-15 | 2014-09-15 | Data transferring and receiving method of bus framework |
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| CN201410467523.7A CN104199795B (en) | 2014-09-15 | 2014-09-15 | Data transferring and receiving method of bus framework |
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Cited By (9)
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| CN105634894A (en) * | 2015-12-31 | 2016-06-01 | 深圳市科陆电源技术有限公司 | Enhanced type CAN bus data resending method and device |
| CN105955905A (en) * | 2016-04-18 | 2016-09-21 | 合肥工业大学 | Interface circuit based on serial bus structure and communication protocol |
| CN106528483A (en) * | 2016-10-24 | 2017-03-22 | 北京爱其科技有限公司 | Data communication protocol structure and method |
| CN107505873A (en) * | 2017-08-31 | 2017-12-22 | 西安永固铁路器材有限公司 | A kind of intelligent material allocation cabinet and delivery system shown with quantity |
| CN107505874A (en) * | 2017-08-31 | 2017-12-22 | 西安永固铁路器材有限公司 | A kind of control system of intelligent material allocation cabinet |
| CN109582616A (en) * | 2018-12-05 | 2019-04-05 | 张洋 | Communication system and method based on universal serial bus |
| CN111324559A (en) * | 2020-02-27 | 2020-06-23 | 南通琅润达大数据科技有限公司 | Serial port shunting device with independent request |
| CN111444124A (en) * | 2020-03-25 | 2020-07-24 | 苏州琅润达检测科技有限公司 | Serial port shunting device with high-frequency autonomous request |
| CN114500156A (en) * | 2022-03-18 | 2022-05-13 | 西安超越申泰信息科技有限公司 | Flexibly configurable bus type communication system and communication method |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634894A (en) * | 2015-12-31 | 2016-06-01 | 深圳市科陆电源技术有限公司 | Enhanced type CAN bus data resending method and device |
| CN105634894B (en) * | 2015-12-31 | 2019-08-13 | 深圳市科陆智慧工业有限公司 | A kind of enhanced CAN bus data re-transmitting method and device |
| CN105955905A (en) * | 2016-04-18 | 2016-09-21 | 合肥工业大学 | Interface circuit based on serial bus structure and communication protocol |
| CN105955905B (en) * | 2016-04-18 | 2018-11-06 | 合肥工业大学 | A kind of interface circuit and communication protocol based on serial bus structure |
| CN106528483A (en) * | 2016-10-24 | 2017-03-22 | 北京爱其科技有限公司 | Data communication protocol structure and method |
| CN107505873B (en) * | 2017-08-31 | 2024-05-14 | 西安永固智能装备有限公司 | Intelligent material distribution cabinet with quantity display and distribution system |
| CN107505873A (en) * | 2017-08-31 | 2017-12-22 | 西安永固铁路器材有限公司 | A kind of intelligent material allocation cabinet and delivery system shown with quantity |
| CN107505874A (en) * | 2017-08-31 | 2017-12-22 | 西安永固铁路器材有限公司 | A kind of control system of intelligent material allocation cabinet |
| CN107505874B (en) * | 2017-08-31 | 2024-05-17 | 西安永固智能装备有限公司 | Control system of intelligent material distribution cabinet |
| CN109582616A (en) * | 2018-12-05 | 2019-04-05 | 张洋 | Communication system and method based on universal serial bus |
| CN109582616B (en) * | 2018-12-05 | 2020-07-17 | 北京爱其科技有限公司 | Communication system and method based on serial bus |
| CN111324559A (en) * | 2020-02-27 | 2020-06-23 | 南通琅润达大数据科技有限公司 | Serial port shunting device with independent request |
| CN111444124A (en) * | 2020-03-25 | 2020-07-24 | 苏州琅润达检测科技有限公司 | Serial port shunting device with high-frequency autonomous request |
| CN114500156A (en) * | 2022-03-18 | 2022-05-13 | 西安超越申泰信息科技有限公司 | Flexibly configurable bus type communication system and communication method |
| CN114500156B (en) * | 2022-03-18 | 2024-04-30 | 超越科技股份有限公司 | Flexibly configurable bus type communication system and communication method |
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