CN104184687B - A kind of flow control method and hardware accelerator circuit of communications baseband processing - Google Patents
A kind of flow control method and hardware accelerator circuit of communications baseband processing Download PDFInfo
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- CN104184687B CN104184687B CN201310195204.0A CN201310195204A CN104184687B CN 104184687 B CN104184687 B CN 104184687B CN 201310195204 A CN201310195204 A CN 201310195204A CN 104184687 B CN104184687 B CN 104184687B
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Abstract
The present invention proposes a kind of flow control method of communications baseband processing, and this method includes：The control instruction of physical layer process flow is converted into the control parameter chained list in units of frame by DSP/MCU processors, the linked list units of the chained list include head pointer, information load area and tail pointer, it is connected with each other between linked list units by pointer, the information load area of each linked list units contains all control parameters of a frame；Hardware accelerator is read and parses control parameter chained list automatically, and performing corresponding physical layer procedures according to the control parameter that parses is handled, and to DSP/MCU processor feedback processing results.The present invention also proposes a kind of hardware accelerator circuit of communications baseband processing, comprising：One dma module, a chained list parsing module, an instruction scheduler module, a central controller and multiple physical layer processing units.
Description
Technical field
The present invention relates to wireless communication field, more particularly to a kind of flow control method of communications baseband processing and hardware to add
Fast device circuit.
Background technology
Communications baseband processor（Usually baseband chip or FPGA circuitry）Generally comprise DSP or MCU processor groups into
Control section, and hardware accelerator composition data path calculating section.BBP is above and below processing baseband communication
During row data, typically defined according to communication network, be divided into Layer1（Physical layer）Processing, Layer2（Data link layer）Place
Reason, Layer3（Internet）Processing, MMI（Man-machine interface）Processing and application layer software processing.BBP uses DSP/MCU
Realize Layer2 and Layer3 processing；In Layer1 handling process, it is responsible for algorithm flow control using DSP/MCU, firmly
Part accelerator is responsible for algorithm calculating.
Communications baseband processor realizes that Layer1 processing usually relies on DSP/MCU and hardware accelerator frequency in the prior art
The information exchange of numerous instruction-level, there are following two common methods：Method one, hardware is controlled to add by DSP/MCU execute instructions
Fast device, and by interrupting the intermediateness and result of acquisition hardware accelerator, adjustment algorithm flow.This method needs DSP/
The MCU accurate control participated in the overall process and instructed, the information exchange of interface between software and hardware is excessively frequent, turns into the main of DSP/MCU
One of load.Due to taking more DSP/MCU resources, so as to the disposal ability for lifting DSP/MCU of having to, cause processor
Power consumption and cost are larger.Method two, using fixed order caching area（buffer）, will by DSP/MCU according to fixed form
Control command is inserted, and hardware accelerator is read automatically to order caching area, is parsed and is performed, by interrupt report intermediateness and
Result, and wait new command sequence to insert.This method again results in the frequency of interaction of DSP/MCU and hardware accelerator
It is higher, and the order in buffer area can not be changed, flexible row is poor, and DSP/MCU computing resources are also larger.
The content of the invention
Interacted excessively to solve above-mentioned DSP/MCU with hardware accelerator, DSP/MCU processor resource exorbitant expenditures are asked
Topic, the present invention propose a kind of flow control method of communications baseband processing, and this method is：
The control instruction of physical layer process flow is converted into the control parameter chain in units of frame by DSP/MCU processors
Table, the linked list units of the chained list include head pointer, information load area and tail pointer, mutually interconnected by pointer between linked list units
Connect, the information load area of each linked list units contains all control parameters of a frame；Hardware accelerator reads and solved automatically
Control parameter chained list is analysed, performing corresponding physical layer procedures according to the control parameter that parses is handled, and to DSP/MCU processors
Feedback processing result.
Preferably, as shown in figure 1, above-mentioned DSP/MCU processors by the control instruction of physical layer process flow be converted into
Frame is that the control parameter chained list of unit is specially：Number is passed to after Internet, DSP/MCU processors processing applied business information
According to link layer；In data link layer, business separation is generated the control parameter chained list in units of frame by DSP/MCU processors, and
Pass to physical layer；In physical layer, the result that DSP/MCU processors feed back according to hardware accelerator changes control parameter chain
Relevant field information in table.
Further, all control parameters of a frame in the information load area of above-mentioned linked list units can be tied by four floor
Structure is formed：First layer is one group of control parameter of a sub- carrier wave set, corresponding to the physical layer process of single sub-carrier group；Second
Layer is made up of the control parameter of the control parameter related to coding and multiple subcarrier groups, at the physical layer of type of coding
Reason；Third layer is made up of the control parameter of multiple business modules, corresponding to the physical layer process based on time slot or based on frequency range；The
Four layers of control parameter by multiple frames is formed, corresponding to the physical layer process based on frame.Accordingly, the processing of hardware accelerator can
To be specially：
Hardware accelerator reads the chain of each frame according to the linked list units position of chain table pointer successively Automatic-searching next frame
Information load area in table unit simultaneously parses, and according to the four-layer structure of the control parameter parsed, configures single in hardware accelerator
The physical layer processing unit of individual sub- carrier wave set, the physical layer processing unit of type of coding, the thing based on time slot or based on frequency range
Manage layer processing unit, the physical layer processing unit based on frame, then by each physical layer processing unit according to configuration to the frame
Data perform the links processing of physical layer process flow, most backward DSP/MCU processors feedback processing result successively automatically.
Preferably, for uplink baseband processing, gone back in the information load area of the linked list units of upload control parameter chained list
Including a data pointer area, pending data area is pointed to, hardware accelerator loads the data pointer and pointed to automatically
Data, perform upstream physical layer handling process after, will handle successfully or failure by interrupt notification DSP/MCU at
Manage device.
Preferably, for downgoing baseband processing, gone back in the information load area of the linked list units of descending control parameter chained list
Including a data pointer area, after hardware accelerator performs down physical layer handling process, the downlink reception data that will obtain
It is stored in data pointer address, the content of data pointer address is then read by interrupt notification DSP/MCU processors.
Preferably, as shown in Fig. 2 DSP/MCU processors and hardware accelerator are realized synchronously by semaphore：The signal
Measure to be stored in the variable of particular memory space, the linked list units that DSP/MCU processors often generate a frame then increase semaphore
Value, after then hardware accelerator inquiry semaphore learns that it is written over, then read automatically and parse the linked list units of the frame, perform
Corresponding physical layer process flow, and reduce the value of semaphore.
The present invention also proposes a kind of hardware accelerator circuit of communications baseband processing, and the circuit is as shown in figure 3, comprising following
Part：One DMA（Direct Memory Access）Module, a chained list parsing module, one instruction scheduler module, one
Central controller and multiple physical layer processing units；
Dma module is used to read linked list units, and reads the data for needing to carry out upstream physical layer processing or storage
The data that down physical layer is disposed；Chained list parsing module is used to parse control parameter chained list；Instructing scheduler module to be used for will
The control parameter that chained list parsing module is resolved to passes to central controller；Central controller is used to be controlled according to control parameter
Dma module and physical layer processing unit；Each physical layer processing unit is used for each ring for performing physical layer process flow successively
Section processing.
Preferably, foregoing circuit includes for upstream physical layer processing, the multiple physical layer processing unit：Scrambling is single
Member, coding unit, interleave unit, modulating unit, code expand unit, carrier wave map unit, antenna processing unit, IFFT units.
Preferably, foregoing circuit includes for down physical layer processing, the multiple physical layer processing unit：FFT unit,
Carrier demapping unit, aerial signal estimation unit, channel estimating unit, symbol detection, decoding expand unit, deinterleave list
Member, decoding unit, Descrambling unit.
The present invention realizes that DSP/MCU accelerates with physical layer hardware in baseband communication processing by way of control parameter chained list
The interactive controlling of device, it is not necessary to which DSP/MCU directly controls hardware accelerator, and hardware accelerator can be by controlling the control in chained list
Parameter information processed automatically process with timing receipt and send communication data, substantially reduce between DSP/MCU and hardware accelerator
Information exchange frequency so that DSP/MCU can discharge carry out Layer2 and Layer3 processing, reach reduction processing work(
The purpose of consumption and cost, while instruction amount of storage is reduced, the software development cost of communication protocol is reduced, improves communication base
The real-time of tape handling Row control.In addition, the control parameter chained list of the present invention is unrelated with specific physical store zone position, storage
Area has more flexibility.
Brief description of the drawings
Fig. 1 is that control instruction is converted into the schematic diagram of control parameter chained list by the DSP/MCU processors of the present invention；
Fig. 2 is that the DSP/MCU processors of the present invention and hardware accelerator realize synchronous schematic diagram by semaphore；
Fig. 3 is the structural representation of the hardware accelerator circuit using control parameter chained list of the present invention；
Fig. 4 is the structural representation of the control parameter chained list of the up processing of the embodiment of the present invention one；
Fig. 5 is the structural representation of the control parameter chained list of the downlink processing of the embodiment of the present invention one；
Fig. 6 is the circuit structure diagram of the hardware accelerator of the uplink baseband processing of the embodiment of the present invention two；
Fig. 7 is the circuit structure diagram of the hardware accelerator of the downgoing baseband processing of the embodiment of the present invention three.
Embodiment
The embodiment of the present invention is described in detail below in conjunction with the accompanying drawings.
Embodiment one：The flow control method handled using the communications baseband of control parameter chained list
The communications baseband chip of the present embodiment devises control parameter chained list, and in Internet, the processing of DSP/MCU processors should
With passing to data link layer after business information；In data link layer, DSP/MCU processors by business separation, generate using frame as
The control parameter chained list of unit, and pass to physical layer；In physical layer, DSP/MCU processors feed back according to hardware accelerator
Relevant field information in result modification control parameter chained list.
The present embodiment is handled according to the uplink and downlink of physical layer, and control parameter chained list is divided into up transmission control parameter
Chained list and downlink reception control parameter chained list, list structure difference is as shown in Figure 4 and Figure 5.The linked list units of control parameter chained list
Including head pointer, information load area and tail pointer.It is connected with each other, can be looked into forward or a backward by pointer between linked list units
Look for, the interconnected relationship between linked list units can also be changed by changing pointer end to end.During hardware performs
It the operation such as can flexibly be edited, be deleted, be inserted according to actual conditions.Because chained list uses the Data-Link that software is commonly used
Table structure, software programmers can carry out data modeling to control parameter chained list according to the concrete structure of chained list, and encapsulation is various
Function is searched, changed and created, facilitates the establishment and modification of chained list.
In Fig. 4, the up control parameter chained list for sending frame includes head pointer（The chain table address of former frame）, synchronizing information,
Frame configuration information, tail pointer（The chain table address of next frame）, business information, business pointer（Referred between multiple business by business
Pin connects）, the field such as service configuration information.It is effective that synchronizing information includes current linked list units validity flag, data and parameter
Property mark, debugging mark etc. information, for control hardware whether perform present frame send.Frame configuration information contains transmission mould
Information such as formula, antenna mode, time slot proportion etc..Business information includes the letter such as type of coding, weave type, coded data length
Breath.Service configuration information includes modulation type, the configuration of channel resource, sub-carrier configuration parameter, etc..The linked list units of uplink frame
The storage pointer of uplink data sending is also add, points to business datum that is pending and sending, hardware accelerator loads automatically
The data that pointer points to, perform upstream physical layer handling process.
Visible by epimere word description, the control parameter of a frame of the present embodiment is made up of four-layer structure：First layer
For one group of control parameter of a sub- carrier wave set（Sub-carrier configuration parameter i.e. in service configuration information etc.）, corresponding to single son
The physical layer process of carrier wave set；The second layer is by the control parameter related to coding（Modulation type letter i.e. in service configuration information
Breath etc.）Formed with the control parameter of multiple subcarrier groups（Channel configuration information i.e. in service configuration information etc.）, corresponding to volume
The physical layer process of code type；Third layer by multiple business modules control parameter（That is business information）Form, corresponding to based on when
Gap or the physical layer process based on frequency range, every kind of business module can be different type of codings；The 4th layer of control by multiple frames
Parameter processed（That is frame configuration information）Form, corresponding to the physical layer process based on frame, multiple time slots or multiple frequency ranges composition one
Individual complete frame structure.By such layered shaping, different configurations and control are completed according to different time points in traditional approach
The Complicated Flow of system is transformed into establishment and modification simply to chained list, and the complex control mode in conventional operation mode changes
For hardware circuit according to chained list parameter complete, greatly reduce the demand to processor disposal ability, simplify software programming and
Debugging cycle.
The control parameter chained list of Fig. 5 downlink reception frame is similar with the list structure of uplink frame, the linked list units of downlink frame
The storage pointer of downlink reception data is also add, hardware accelerator is deposited after downlink processing in corresponding pointer address
Service data information, then pass through the content of interrupt notification DSP/MCU processor reading pointers address.
After the present embodiment uses list structure, the control process of Base-Band Processing includes, and control parameter chain is generated by DSP/MCU
Table is simultaneously write in memory, while hardware accelerator reads and performs control chained list instruction, and the execution of the two flows is relatively only
It is vertical, reduce resource and time loss caused by flow synchronization in traditional approach.The present embodiment DSP/MCU configuration chained list with
The synchronous method of hardware accelerator execution chained list can only by way of semaphore is realized synchronous：Deposited in shared memory
Semaphore data structure, the quantity for whether being ready to and preparing for indicating linked list units are stored up, DSP/MCU processors often generate
The linked list units of one frame then make semaphore add 1, and notify hardware accelerator.Then hardware accelerator inquiry semaphore, if non-zero,
Then read and parse the linked list units of the frame, perform the communication process processing sent and received, notification signal amount subtracts 1；Hardware adds
Fast device inquires about semaphore, if semaphore is 0, stops reading chained list, into wait state.
Above-mentioned hardware accelerator reads and performed the flow for controlling chained list to instruct, and specifically processing is：Hardware accelerator is pressed first
The root node of control parameter chained list is found according to the chain table address of software merit rating, it is then next according to chain table pointer successively Automatic-searching
The linked list units position of frame, read the information load area in the linked list units of each frame and parse, joined according to the control parsed
Several four-layer structures automatically configures the physical layer processing unit of single sub-carrier group in hardware accelerator, the physical layer of type of coding
Processing unit, the physical layer processing unit based on time slot or based on frequency range, the physical layer processing unit based on frame, then by each
Individual physical layer processing unit performs the links of physical layer process flow according to the configuration successively automatically to the data of the frame
Processing（For up, hardware accelerator loads the upstream data of data pointer sensing automatically, performs coding and modulation, and send
Symbol data；For descending, hardware accelerator receives descending carrier automatically, demodulates and decodes downlink service data）, last hardware
Accelerator is to DSP/MCU processor feedback processing results（For up, it will handle successfully or failure be open close in
Know DSP/MCU processors；For descending, the content in data pointer address is read by interrupt notification DSP/MCU processors）.
Embodiment two：Circuit for the hardware accelerator of uplink baseband processing
The present embodiment for it is a kind of for uplink baseband processing hardware accelerator, its structure as shown in fig. 6, including：Chained list
Parsing module LinkList CTRL, instruct scheduler module CMD CTRL, central controller TX CTRL, upstream physical layer processing list
Member includes scrambling unit, coding unit, interleave unit, modulating unit, code and expands unit, subchannel mappings unit, multiple antennas processing
Unit, subcarrier mapping unit, IFFT units etc., and up dma module.The handling process of the hardware accelerator is as follows：
DSP generates the configuration parameter of the up transmission of physical layer, and generate according to the station information of Layer2/3 layer transmission
Row control parameter chained list, it is written in memory LinkList Memory, then notifies upstream hardware accelerator.Upstream hardware
Accelerator reads the chained list parameter in the linked list units of a frame by dma module, and parsing chained list by LinkList CTRL joins
Number, command sequence is generated by CMD CTRL and passes to central controller, central controller is joined according to command sequence and chained list
Number configures each physical layer processing units, including scramble, encode, interweaving, modulating, code expansions, subchannel mappings, multiple antennas are handled,
The up transmission algorithm such as IFFT, and control dma module to read pending data, then performed by each physical layer processing unit
The transmission flow of multiple business in one frame.After a frame, which is sent, to be terminated, pointer of the hardware accelerator in chained list is automatic to read
Next linked list units for sending frame, send next frame data.
Embodiment three：Hardware accelerator circuit for downgoing baseband processing
The present embodiment is a kind of hardware accelerator for downgoing baseband processing, its hardware configuration and handling process and implementation
The hardware accelerator circuit for being used for uplink baseband processing of example two is similar.The circuit hardware structure as shown in fig. 7, comprises：Chained list
Parsing module LinkList CTRL, instruct scheduler module CMD CTRL, central controller RX CTRL, down physical layer processing list
Member includes Descrambling unit, decoding unit, deinterleaves unit, demodulating unit, decoding expansion unit, symbol detection, multiple antennas letter
Road estimation unit, subcarrier de-mapping unit, FFT unit etc., and descending dma module.The handling process of the hardware accelerator
It is as follows：
DSP generates the configuration parameter of physical layer downlink reception according to the station information of Layer2/3 layer transmission, and under generating
Row control parameter chained list, it is written in memory LinkList Memory, then notifies downstream hardware accelerator.Downstream hardware
Accelerator reads the chained list parameter in the linked list units of a frame by dma module, and parsing chained list by LinkList CTRL joins
Number, command sequence is generated by CMD CTRL and passes to central controller, central controller is joined according to command sequence and chained list
Number configures each physical layer processing units, including FFT, subcarrier demapping, multi-antenna channel estimation, symbol detection, decoding expansion,
The downlink reception algorithms such as demodulation, deinterleaving, decoding, descrambling, then perform multiple industry in a frame by each physical layer processing unit
The reception flow of business.The data for receiving and being disposed are deposited into memory by dma module, are connect by descending in chained list
The storage pointer instruction storage address of data is received, and is read by interrupt notification DSP.It is hardware-accelerated after a frame, which receives, to be terminated
Pointer of the device in chained list, the linked list units of next receiving frame are read automatically, prepare to receive and demodulate next frame data.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should be included in the scope of the protection.
Claims (10)
1. the flow control method of a kind of communications baseband processing, it is characterised in that methods described is：
The control instruction of physical layer process flow is converted into the control parameter chained list in units of frame, institute by DSP/MCU processors
Stating the linked list units of chained list includes head pointer, information load area and tail pointer, is connected with each other between linked list units by pointer, often
The information load area of individual linked list units contains all control parameters of a frame；
Hardware accelerator is read and parses control parameter chained list automatically, and corresponding physical layer is performed according to the control parameter parsed
Flow processing, and to DSP/MCU processor feedback processing results.
2. method according to claim 1, it is characterised in that the DSP/MCU processors are by the control of physical layer process flow
Instruction morphing is that the control parameter chained list in units of frame is specially：
Data link layer is passed to after Internet, DSP/MCU processors processing applied business information；In data link layer,
Business separation is generated the control parameter chained list in units of frame, and pass to physical layer by DSP/MCU processors；In physical layer,
The result that DSP/MCU processors feed back according to hardware accelerator changes the relevant field information in control parameter chained list.
3. method according to claim 2, it is characterised in that all controls of a frame in the information load area of linked list units
Parameter is made up of four-layer structure：First layer is one group of control parameter of a sub- carrier wave set, corresponding to the thing of single sub-carrier group
Manage layer processing；The second layer is made up of the control parameter of the control parameter related to coding and multiple subcarrier groups, corresponding to coding
The physical layer process of type；Third layer is made up of the control parameter of multiple business modules, corresponding to based on time slot or based on frequency range
Physical layer process；4th layer is made up of the control parameter of multiple frames, corresponding to the physical layer process based on frame.
4. method according to claim 3, it is characterised in that the processing of hardware accelerator is specially：
Hardware accelerator reads the chain list of each frame according to the linked list units position of chain table pointer successively Automatic-searching next frame
Information load area in member simultaneously parses, and according to the four-layer structure of the control parameter parsed, configures single son in hardware accelerator
The physical layer processing unit of carrier wave set, the physical layer processing unit of type of coding, the physical layer based on time slot or based on frequency range
Processing unit, the physical layer processing unit based on frame, then by each physical layer processing unit according to the data configured to the frame
Automatically the links processing of physical layer process flow, most backward DSP/MCU processors feedback processing result are performed successively.
5. method according to claim 1, it is characterised in that：For uplink baseband processing, in the chain of upload control parameter chained list
Also include a data pointer area in the information load area of table unit, point to pending data area, hardware accelerator is certainly
The data that the dynamic loading data pointer points to, after performing upstream physical layer handling process, it will handle successfully or what is failed disappear
Breath passes through interrupt notification DSP/MCU processors.
6. method according to claim 1, it is characterised in that：For downgoing baseband processing, in the chain of descending control parameter chained list
Also include a data pointer area in the information load area of table unit, hardware accelerator performs down physical layer handling process
Afterwards, obtained downlink reception data are stored in data pointer address, number is then read by interrupt notification DSP/MCU processors
According to the content of pointer address.
7. method according to claim 1, it is characterised in that DSP/MCU processors and hardware accelerator are realized by semaphore
It is synchronous：The semaphore is the variable for being stored in particular memory space, and DSP/MCU processors often generate the linked list units of a frame then
Increase the value of semaphore, after then hardware accelerator inquiry semaphore learns that it is written over, then read automatically and parse the frame
Linked list units, corresponding physical layer process flow is performed, and reduce the value of semaphore.
8. a kind of hardware accelerator circuit for claim 1 methods described, it is characterised in that the circuit is included with bottom
Point：One dma module, a chained list parsing module, an instruction scheduler module, at a central controller and multiple physical layers
Manage unit；
Dma module is used to read linked list units, and reads the data for needing to carry out upstream physical layer processing or store descending
The data that physical layer process finishes；Chained list parsing module is used to parse control parameter chained list；Scheduler module is instructed to be used for chained list
The control parameter that parsing module is resolved to passes to central controller；Central controller is used to control DMA moulds according to control parameter
Block and physical layer processing unit；Each physical layer processing unit is used to perform successively at the links of physical layer process flow
Reason.
9. circuit according to claim 8, it is characterised in that the circuit is for upstream physical layer processing, the multiple physics
Layer processing unit includes：Scrambling unit, coding unit, interleave unit, modulating unit, code expand unit, carrier wave map unit, antenna
Processing unit, IFFT units.
10. circuit according to claim 8, it is characterised in that the circuit is for down physical layer processing, the multiple physics
Layer processing unit includes：FFT unit, carrier demapping unit, aerial signal estimation unit, channel estimating unit, symbol detection
Unit, decoding expand unit, deinterleave unit, decoding unit, Descrambling unit.
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| CN106888271B (en) * | 2017-03-30 | 2020-06-02 | 桃芯科技(苏州)有限公司 | BLE5.0 protocol system |
| CN110808908B (en) * | 2019-09-27 | 2021-09-21 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | System and method for switching redundant network in real time across platforms |
| CN111160546B (en) * | 2019-12-31 | 2023-06-13 | 深圳云天励飞技术有限公司 | Data processing system |
| CN113721972B (en) * | 2020-05-25 | 2024-04-16 | Oppo广东移动通信有限公司 | Configuration method, device and storage medium of hardware accelerator configuration information |
| CN112395464A (en) * | 2020-11-18 | 2021-02-23 | 扬州船用电子仪器研究所(中国船舶重工集团公司第七二三研究所) | Electronic information intermediate frequency data processing method based on openmp acceleration |
| CN114116557B (en) * | 2021-11-15 | 2024-02-27 | 同济大学 | Channel estimation device and method based on hardware accelerator and digital signal processor |
| CN114285703B (en) * | 2022-03-03 | 2022-06-21 | 广州慧睿思通科技股份有限公司 | Method, chip, device and storage medium for estimating physical uplink shared channel |
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