CN104183499B - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN104183499B CN104183499B CN201410397812.4A CN201410397812A CN104183499B CN 104183499 B CN104183499 B CN 104183499B CN 201410397812 A CN201410397812 A CN 201410397812A CN 104183499 B CN104183499 B CN 104183499B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 98
- 238000002360 preparation method Methods 0.000 title claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 130
- 239000004020 conductor Substances 0.000 claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 22
- 230000004888 barrier function Effects 0.000 claims description 17
- 229910021332 silicide Inorganic materials 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 239000002305 electric material Substances 0.000 claims 2
- 241000190022 Pilea cadierei Species 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229920000297 Rayon Polymers 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- ZNKMCMOJCDFGFT-UHFFFAOYSA-N gold titanium Chemical compound [Ti].[Au] ZNKMCMOJCDFGFT-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910001258 titanium gold Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Present invention is disclosed a kind of preparation method of semiconductor devices, including：A substrate is provided, the side of the substrate is formed with an epitaxial layer, and the epitaxial layer is formed with least source region away from the surface of the substrate side, and the source area is formed with source electrode away from the side of the substrate；At least one first is formed in the substrate away from the side of the epitaxial layer to be open, first opening exposes the source area；Conductive material is filled in being open described first, conductive plug is formed.Meanwhile, the present invention also provides a kind of semiconductor devices.Semiconductor devices of the invention and preparation method avoid repeatedly carrying out high dose, the ion implantation technology of high-energy and high-temperature diffusion process, improve the Performance And Reliability of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of semiconductor devices and preparation method thereof.
Background technology
Radio frequency LDMOS (lateral diffusion metal oxide semiconductor, horizontal proliferation metal oxygen
Compound semiconductor) it is a kind of device for having good market.In particular with the extensive use of the communication technology, radio frequency LDMOS does
For a kind of New Type Power Devices will more and more be paid attention to.
As shown in figure 1, this rough schematic for existing radio frequency LDMOS device.The side of substrate 10 is formed with outside one
Prolong layer 20, the epitaxial layer 20 is formed with least source region 21, drain region 22, body area away from the surface of the side of the substrate 10
23rd, drift region 24, the source area 21 is formed with source electrode 31, grid 32 and drain electrode 33, source away from the side of the substrate 10
Pole 31, grid 32 and drain electrode 33 are isolated by dielectric layer 30.Substrate 10 is formed with the back of the body away from the side of the epitaxial layer 20
Face electrode 41.In order to realize conducting for substrate 10 and source area 21, the radio frequency LDMOS device of prior art is in substrate 10 and source
A sinking layer 25 is formed between polar region 21, the sinking layer 25 is formed using ion implanting and diffusion technique, with high concentration
Ion doping.
Because radio frequency LDMOS device needs to carry out high-voltage applications, it is therefore desirable to thicker epitaxial layer 20.In order to prepare radio frequency
LDMOS device is, it is necessary to using the technique of one or many epitaxial growth, ion implanting and high-temperature thermal annealing so that existing to penetrate
The manufacturing process of frequency LDMOS is complex.Also, in order that the depth of sinking layer 25 reaches requirement, it is necessary to carry out high dose, height
The ion implanting of energy, this is very high for the requirement of ion injection machine table.In order to obtain the sinking layer 25 of break-through epitaxial layer 20, from
High temperature is often carried out after son injection to spread for a long time, so cause sinking layer 25 to have larger lateral dimension, result in radio frequency
The lateral dimension of LDMOS device is larger, so as to increased device area, increased ghost effect, and limiting device performance includes
The lifting of power and efficiency；Simultaneously as this high-temperature diffusion process is formed after the formation of epitaxial layer 20, these high temperature
Diffusion process can cause the dopant redistribution close to the region of substrate 10 in epitaxial layer, further the performance of influence device.It is right
For the LDMOS of N-shaped or p-type, the carrier type in sinking layer 25 is different, in addition it is also necessary to carries out ion implanting respectively and carries out
Corresponding High temperature diffusion so that manufacturing process is more complicated..
The content of the invention
It is an object of the present invention to provide a kind of semiconductor devices and preparation method thereof, it is to avoid repeatedly carry out high dose, height
The ion implantation technology of energy, improves the Performance And Reliability of semiconductor devices.
In order to solve the above technical problems, the present invention provides a kind of preparation method of semiconductor devices, including：
A substrate is provided, the side of the substrate is formed with an epitaxial layer, and the epitaxial layer is away from the substrate side
Surface is formed with least source region, and the source area is formed with source electrode away from the side of the substrate；
At least one first is formed in the substrate away from the side of the epitaxial layer to be open, first opening exposes institute
State source area；And
Conductive material is filled in being open described first, conductive plug is formed.
Optionally, in the preparation method of the semiconductor devices, the preparation method of the semiconductor devices also includes：
Second is formed in the substrate away from the side of the epitaxial layer to be open, the characteristic size of second opening is more than
The characteristic size of first opening, the depth of the depth less than the described first opening of second opening, second opening
Expose first opening；
The conductive material is filled in being open described second.
Optionally, in the preparation method of the semiconductor devices, the step of a substrate is provided and in the substrate back of the body
Between the step of forming at least one first opening from the side of the epitaxial layer, also include：
The substrate is carried out away from the side of the epitaxial layer thinning.
Optionally, in the preparation method of the semiconductor devices, the substrate is fixed on a substrate, to the lining
Bottom carries out thinning away from the side of the epitaxial layer.
Optionally, in the preparation method of the semiconductor devices, the thickness of the thinning rear substrate is 0.2 μm~20 μ
m。
Optionally, in the preparation method of the semiconductor devices, the step of conductive material is filled in being open described first
Suddenly include：
Successively a barrier layer and the conductive material, the resistance are deposited in the substrate away from the side of the epitaxial layer
The surface of barrier and conductive material covering first opening and the substrate.
Optionally, in the preparation method of the semiconductor devices, the step of conductive material is filled in being open described first
Suddenly include：
In the substrate barrier layer is deposited away from the side of the epitaxial layer；
The barrier layer is ground, the barrier layer of the epi-layer surface is removed；
In the substrate conductive material is deposited away from the side of the epitaxial layer；
The conductive material is ground, the conductive material of the epi-layer surface is removed.
Optionally, in the preparation method of the semiconductor devices, the preparation method of the semiconductor devices also includes：
In the substrate metal layer on back is deposited away from the side of the epitaxial layer.
Optionally, in the preparation method of the semiconductor devices, the material of the metal layer on back is gold.
Optionally, in the preparation method of the semiconductor devices, the conductive material be copper, tungsten or aluminium in one kind or
Several combinations.
Optionally, in the preparation method of the semiconductor devices, first opening is groove or through hole.
Optionally, in the preparation method of the semiconductor devices, autoregistration is formed between the source area and source electrode
Silicide, first opening exposes the self-aligned silicide.
Another side of the invention, also provides a kind of semiconductor devices, including：
Substrate, the side of the substrate is formed with an epitaxial layer, surface shape of the epitaxial layer away from the substrate side
Into there is at least source region, the source area is formed with source electrode away from the side of the substrate；
First opening, is formed at the substrate away from the side of the epitaxial layer, and first opening exposes the source
Polar region；And
Conductive material, is filled in first opening, forms conductive plug.
Optionally, in the semiconductor devices, the substrate is also formed with second and opens away from the side of the epitaxial layer
Mouthful, the characteristic size of the characteristic size more than the described first opening of second opening, the depth of second opening is less than institute
The depth of the first opening is stated, second opening exposure, first opening is filled with the conduction material in second opening
Material.
Optionally, in the semiconductor devices, conductive material covering first opening and the substrate
Surface.
Optionally, in the semiconductor devices, conductive material covering first opening does not cover the substrate
Surface.
Optionally, in the semiconductor devices, the semiconductor devices also includes a metal layer on back, the back-side gold
Category layer is formed at the substrate away from the side of the epitaxial layer.
Optionally, in the semiconductor devices, the material of the metal layer on back is gold.
Optionally, in the semiconductor devices, the thickness of the substrate is 0.2 μm~20 μm.
Optionally, in the semiconductor devices, the conductive material is the group of one or more in copper, tungsten or aluminium
Close.
Optionally, in the semiconductor devices, first opening is groove or through hole.
Optionally, in the semiconductor devices, self-aligned silicide is formed between the source area and source electrode, it is described
First opening exposes the self-aligned silicide.
Compared with prior art, semiconductor devices that the present invention is provided and preparation method thereof has advantages below：
1. in described semiconductor devices and preparation method thereof, the substrate away from the epitaxial layer side formed to
Few one first opening, first opening exposes the source area, and conductive material, shape are filled in being open described first afterwards
Into the conductive plug for turning on the substrate and source area.Preparation method of the invention avoid repeatedly carrying out high dose, high-energy from
Sub- injection technology, can be effectively reduced the horizontal area of semiconductor devices；Also, the resistance of the conductive plug is less than existing skill
The resistance of lower open caisson, can improve the Performance And Reliability of semiconductor devices in art.
2. in described semiconductor devices and preparation method thereof, also including to the substrate away from the epitaxial layer side
Carry out thinning step, it is thinning after device most minimal thickness can only than epitaxial layer thickness more than 0.2 micron, so as to be greatly reduced
The thickness of semiconductor devices, improves the heat-sinking capability of device, reduces junction temperature of the semiconductor devices in high power work,
Further increase the Performance And Reliability of device.
Brief description of the drawings
Fig. 1 is the schematic diagram of radio frequency LDMOS device of the prior art；
Fig. 2 is the flow chart of the preparation method of semiconductor devices in one embodiment of the invention；
Fig. 3 to Fig. 9 is the schematic diagram of device architecture in the preparation method of semiconductor devices in first embodiment of the invention；
Figure 10 to Figure 13 is the schematic diagram of device architecture in the preparation method of semiconductor devices in second embodiment of the invention；
Figure 14 to Figure 17 is the schematic diagram of device architecture in the preparation method of semiconductor devices in third embodiment of the invention.
Specific embodiment
Semiconductor devices of the invention and preparation method thereof is described in more detail below in conjunction with schematic diagram, wherein
Illustrate the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and still
So realize advantageous effects of the invention.Therefore, description below be appreciated that it is widely known for those skilled in the art,
And it is not intended as limitation of the present invention.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to relevant system or relevant business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expends
Time, but it is only to those skilled in the art routine work.
The present invention is more specifically described by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is in the form of simplifying very much and using non-
Accurately ratio, is only used to conveniently, lucidly aid in illustrating the purpose of the embodiment of the present invention.
Core concept of the invention is, there is provided a kind of preparation method of semiconductor devices, comprises the following steps：
Step S11 a, there is provided substrate, the side of the substrate is formed with an epitaxial layer, and the epitaxial layer deviates from the lining
The surface of bottom side is formed with least source region, and the source area is formed with source electrode away from the side of the substrate；
Step S12, forms at least one first and is open in the substrate away from the side of the epitaxial layer, first opening
Expose the source area；
Step S13, conductive material is filled in being open described first, forms conductive plug.
Using above-mentioned preparation method, can avoid repeatedly carrying out the ion implantation technology of high dose, high-energy, can be effective
Ground reduces the horizontal area of semiconductor devices；Also, the resistance of the conductive plug is less than the resistance for descending open caisson in the prior art, can
To improve the Performance And Reliability of semiconductor devices..
Core concept of the invention, also provides a kind of semiconductor devices, including：
Substrate, the side of the substrate is formed with an epitaxial layer, surface shape of the epitaxial layer away from the substrate side
Into there is at least source region, the source area is formed with source electrode away from the side of the substrate；
First opening, is formed at the substrate away from the side of the epitaxial layer, and first opening exposes the source
Polar region；And
Conductive material, is filled in first opening, forms conductive plug.
Several embodiments of the semiconductor devices and preparation method thereof are exemplified below, it is of the invention interior with clear explanation
Hold, it is understood that, present disclosure is not restricted to following examples, and other are by those of ordinary skill in the art's
The improvement of conventional technical means is also within thought range of the invention.
First embodiment
In the present embodiment, illustrated as a example by preparing radio frequency LDMOS device.Refer to Fig. 2-Fig. 8 and illustrate this
The first embodiment of invention, wherein, Fig. 2 is the flow chart of the preparation method of semiconductor devices in one embodiment of the invention；Fig. 3 is extremely
Fig. 9 is the schematic diagram of device architecture in the preparation method of semiconductor devices in first embodiment of the invention.
As shown in Fig. 2 carrying out step S11 first, as shown in Figure 3, there is provided a substrate 110, the substrate 110 can be silicon
The Semiconductor substrates such as substrate, germanium substrate, in the present embodiment, the Doped ions with the first kind, described in the substrate 110
Substrate 110 is heavy doping.The side of the substrate 110 is formed with an epitaxial layer 120, and the epitaxial layer 120 is the first kind
It is lightly doped.The epitaxial layer 120 is formed with least source region 121, drain region 122 away from the surface of the side of the substrate 110
And the drift region 124 between source area 121 and drain region 122, the source area 121 is formed in body area 123.At this
In embodiment, the source area 121 and drain region 122 are the heavy doping of the first kind, and the drift region 124 is the first kind
It is lightly doped, the body area 123 is lightly doped for Second Type.Wherein, the first kind is p-type doping, and Second Type can be N-type
Doping；Or, the first kind is n-type doping, Second Type can adulterate for p-type.
The source area 121 is formed with source electrode 131 away from the side of the substrate 110, and the drain region 122 is away from described
The side of substrate 110 is formed with drain electrode 133, additionally, the side of substrate 110 is also formed with grid described in the epitaxial layer 120
132, wherein, the source electrode 131, grid 132, drain electrode 133 are isolated by dielectric layer 130.Preferably, the source area 121
Self-aligned silicide 135 is formed between source electrode 131, autoregistration silication is formed between the drain region 122 and drain electrode 133
Thing 136, is formed with gate dielectric layer 134 between the grid 132 and body area 123.Additionally, can also be wrapped in the dielectric layer 130
Include interconnection structure etc., this be it will be appreciated by those skilled in the art that, therefore not to repeat here.
Preferably, it is thinning also to include that the side for deviating from the epitaxial layer 120 to the substrate 110 is carried out, in the present embodiment
In, the thinning step is between the step S11 and step S12.As shown in figure 4, the substrate 110 is fixed on into a base
On plate 150, in the present embodiment, by the front of wafer, i.e., the substrate 150, Ke Yitong is pasted on the surface of described dielectric layer 130
Cross together with viscose 151 pastes the dielectric layer 130 with the substrate 150, so as to the substrate 110 is fixed on into the base
On plate 150.Wherein, the substrate 150 can be bare silicon wafer (Bare Wafer) etc..
As shown in figure 5, after the substrate 110 is fixed, entering away from the side of the epitaxial layer 120 to the substrate 110
Row is thinning.The thickness H1 of the thinning rear substrate 110 is preferably 0.2 μm~20 μm, such as 1 μm, 2 μm, 5 μm, 10 μm, 15 μm
Etc..When the thickness H1 of the substrate 110 is 0.2 μm~20 μm, preferable Ohmic contact can be formed, can effectively dropped again
The thickness of low final semiconductor devices, reduces junction temperature of the semiconductor devices in high power work, and semiconductor improves device
The Performance And Reliability of part.
Then carry out step S12, as shown in fig. 6, the substrate 110 away from the epitaxial layer 120 side formed to
The substrate 110 is run through in few one first opening 160, first opening 160, and exposes the source area 121.Preferably,
First opening 121 exposes the self-aligned silicide 135, is easily controlled when first opening 160 is prepared described
The depth of the first opening 160, and be conducive to improving the electric conductivity between the source electrode 131 and substrate 110.First opening
160 can be prepared using photo etching process.First opening 121 can be groove or through hole, open when described first
When mouth 121 is groove, the critical size of first opening 121 is the width of groove, when the described first opening 121 is through hole
When, the critical size of first opening 121 is the diameter of through hole.
Then step S13 is carried out, conductive material is filled in the described first opening 160, form conductive plug.In the present embodiment
In, as shown in Figure 7 and Figure 8, successively the substrate 110 away from the epitaxial layer 120 side deposit a barrier layer 161 and
The conductive material 162, the barrier layer 161 and conductive material 162 cover first opening 160 and the substrate 110
Surface.It is, of course, also possible to a Seed Layer is prepared between the barrier layer 161 and conductive material 162, in order in the resistance
The conductive material 162 is prepared in barrier 161, part of the conductive material 162 in the described first opening 160 forms conduction
Plug.Preferably, the conductive material 162 is the metal or alloy materials such as copper, tungsten or aluminium, the resistance of the conductive material 162 is low
In the resistance for descending open caisson in the prior art, be conducive to improving the performance of semiconductor devices.Preferably, the conductive material 162 is
Copper, can reduce stress of the conductive plug to the epitaxial layer 120.
Afterwards, the substrate 150 is peeled off with the substrate 110, has been obtained the semiconductor devices 1 of the present embodiment,
As shown in figure 9, the semiconductor devices 1 includes substrate 110, the side of the substrate 110 is formed with an epitaxial layer 120, described
Epitaxial layer 120 is formed with least source region 121 away from the surface of the side of the substrate 110, and the source area 121 is away from described
The side of substrate 110 is formed with source electrode 131, and self-aligned silicide 135 is formed between the source area 121 and source electrode 131.Institute
State the first opening 160 and be formed at the substrate 110 away from the side of the epitaxial layer 120, first opening 160 exposes institute
Self-aligned silicide 135 is stated, the conductive material 162 is filled in first opening 160, forms the conductive plug.Additionally,
The conductive material 162 also covers the surface of the substrate 110, forms backplate.The conductive plug turns on the substrate 110
With source area 121, the conductive communication between the substrate 110 and source area 121 is realized.
Second embodiment
Figure 10-Figure 13 is referred to, to illustrate the second embodiment of invention.In Figure 10-Figure 13, reference number is represented and schemed
3- Fig. 9 identicals are stated and first embodiment identical structure.The preparation method of the second embodiment is real with described first
The preparation method for applying example is essentially identical, and its difference is：As shown in Figure 10, in the substrate 110 away from the epitaxial layer 120
Side forms the second opening 170, the characteristic sizes of the characteristic size CD2 more than the described first opening 160 of second opening 170
CD1, the depth H 2 of the depth H 3 less than the described first opening 160 of second opening 170, second opening 170 exposes institute
State the first opening 160.The characteristic size CD1s of the characteristic size CD2 more than the described first opening 160 of second opening 170, has
It is filled in first opening 160 beneficial to by the conductive material 162, and advantageously reduces the electricity of the epitaxial layer 120
Resistance.Wherein, the depth H 3 of second opening 170 can be configured as needed, but should not typically touch body area 123,
In order to avoid the reverse breakdown characteristics of influence device.
Second opening 170 can be groove or through hole, and when the described first opening 160 is through hole, described second opens
Mouth 170 is preferably through hole；When the described first opening 160 is groove, second opening 170 is preferably groove, now, described
Second opening 170 can also be through hole.
The opening 170 of first opening 160 and second in the preparation, can first prepare first opening 160, then prepare
Second opening 170；Second opening 170 can also be first prepared, then prepares first opening 160；It is, of course, also possible to
Using integrated (all in one) technique, while preparing the opening 170 of first opening 160 and second, this is this area
Technical staff is it should be understood that therefore not to repeat here.
In the step S13, as is illustrated by figs. 11 and 12, when the conductive material 162 is filled, while described the
The filling conductive material 162 in one opening 160 and the second opening 170, in the opening 170 of first opening 160 and second
Conductive material 162 forms the metal closures, for turning on the substrate 110 and source area 121.
The substrate 150 is peeled off with the substrate 110, the semiconductor devices 2 of the present embodiment has been obtained, such as Figure 13
Shown, the semiconductor devices 2 is essentially identical with the semiconductor devices 1, and difference is, in the semiconductor devices 2, institute
State substrate 110 and be also formed with second opening 170, first opening 160 and second away from the side of the epitaxial layer 120
Conductive material 162 in opening 170 forms the metal closures, for turning on the substrate 110 and source area 121.
3rd embodiment
Figure 14-Figure 17 is referred to, to illustrate the 3rd embodiment of invention.In Figure 14-Figure 17, reference number is represented and schemed
3- Fig. 9 identicals are stated and first embodiment identical structure.The preparation method of the 3rd embodiment is real with the described 3rd
The preparation method for applying example is essentially identical, and its difference is：The step of filling conductive material 162 in the described first opening 160 is wrapped
Include：
In the substrate 110 barrier layer 161 is deposited away from the side of the epitaxial layer 120；And to the barrier layer 161
It is ground, removes the barrier layer 161 on the surface of epitaxial layer 120, retains the stop in first opening 160
Layer 161, as shown in figure 14；
In the substrate 110 conductive material 162 is deposited away from the side of the epitaxial layer 120；And to the conduction
Material 162 is ground, and removes the conductive material 162 on the surface of epitaxial layer 120, retains in first opening 160
The conductive material 162, as shown in figure 15.
In the present embodiment, the preparation method of the semiconductor devices also includes：
In the substrate 110 metal layer on back 141, as shown in figure 16, institute are deposited away from the side of the epitaxial layer 120
State metal layer on back 141 and form the backplate.Preferably, the material of the metal layer on back 141 is gold, the electric conductivity of gold
It is good.But, the material of the metal layer on back 141 is not limited to be gold, can also be conducting metal or the conjunctions such as copper, silver, nickel, titanium
Gold.
The substrate 150 is peeled off with the substrate 110, the semiconductor devices 3 of the present embodiment has been obtained, such as Figure 17
Shown, the semiconductor devices 3 is essentially identical with the semiconductor devices 1, and difference is, in the semiconductor devices 3, institute
State conductive material 162 and cover first opening 160, the surface of the substrate 110 is not covered.The semiconductor devices 3 is also wrapped
A metal layer on back 141 is included, the metal layer on back 141 is formed at the substrate 110 away from the side of the epitaxial layer 120.
, used as backplate, the material of the backplate can be with the material of the conducting metal 162 not for the metal layer on back 141
Together.
Semiconductor devices of the invention is illustrated by taking radio frequency LDMOS device as an example, but the ordinary skill people of this area
Can be applied to preparation method of the invention in the preparation of other devices by member, as long as needing the device that source area is turned on substrate
Part, can use the method that metal closures are prepared from the back side of the invention.
Obviously, those skilled in the art can carry out various changes and modification without deviating from essence of the invention to the present invention
God and scope.So, if these modifications of the invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising these changes and modification.
Claims (21)
1. a kind of preparation method of semiconductor devices, including：
A substrate is provided, the side of the substrate is formed with an epitaxial layer, surface of the epitaxial layer away from the substrate side
At least source region is formed with, the source area is formed with source electrode away from the side of the substrate；
At least one first is formed in the substrate away from the side of the epitaxial layer to be open, first opening exposes the source
Polar region；And
Conductive material is filled in being open described first, conductive plug is formed.
2. the preparation method of semiconductor devices as claimed in claim 1, it is characterised in that the preparation side of the semiconductor devices
Method also includes：
Second is formed in the substrate away from the side of the epitaxial layer to be open, the characteristic size of second opening is more than described
The characteristic size of the first opening, the depth of the depth less than the described first opening of second opening, second opening exposure
First opening；
The conductive material is filled in being open described second.
3. the preparation method of semiconductor devices as claimed in claim 1 or 2 a, it is characterised in that the step of substrate is provided
And between the step of substrate forms at least one first opening away from the side of the epitaxial layer, also include：
The substrate is carried out away from the side of the epitaxial layer thinning.
4. the preparation method of semiconductor devices as claimed in claim 3, it is characterised in that the substrate is fixed on a substrate
On, the substrate is carried out away from the side of the epitaxial layer thinning.
5. the preparation method of semiconductor devices as claimed in claim 3, it is characterised in that the thickness of the thinning rear substrate is
0.2 μm~20 μm.
6. the preparation method of semiconductor devices as claimed in claim 1, it is characterised in that filled in being open described first and led
The step of electric material, includes：
Successively a barrier layer and the conductive material, the barrier layer are deposited in the substrate away from the side of the epitaxial layer
The first opening described with conductive material covering and the surface of the substrate.
7. the preparation method of semiconductor devices as claimed in claim 1, it is characterised in that filled in being open described first and led
The step of electric material, includes：
In the substrate barrier layer is deposited away from the side of the epitaxial layer；
The barrier layer is ground, the barrier layer of the epi-layer surface is removed；
In the substrate conductive material is deposited away from the side of the epitaxial layer；
The conductive material is ground, the conductive material of the epi-layer surface is removed.
8. the preparation method of semiconductor devices as claimed in claim 7, it is characterised in that the preparation side of the semiconductor devices
Method also includes：
In the substrate metal layer on back is deposited away from the side of the epitaxial layer.
9. the preparation method of semiconductor devices as claimed in claim 8, it is characterised in that the material of the metal layer on back is
Gold.
10. the preparation method of semiconductor devices as claimed in claim 1, it is characterised in that the conductive material be copper, tungsten or
The combination of one or more in aluminium.
The preparation method of 11. semiconductor devices as claimed in claim 1, it is characterised in that first opening for groove or
Through hole.
The preparation method of 12. semiconductor devices as claimed in claim 1, it is characterised in that between the source area and source electrode
Self-aligned silicide is formed with, first opening exposes the self-aligned silicide.
A kind of 13. semiconductor devices, including：
Substrate, the side of the substrate is formed with an epitaxial layer, and the epitaxial layer is formed with away from the surface of the substrate side
At least source region, the source area is formed with source electrode away from the side of the substrate；
First opening, is formed at the substrate away from the side of the epitaxial layer, and first opening exposes the source area；
Second opening, is formed at the substrate away from the side of the epitaxial layer, and the characteristic size of second opening is more than institute
The characteristic size of the first opening is stated, the depth of the depth less than the described first opening of second opening, second opening is sudden and violent
Reveal first opening；And
Conductive material, is filled in first opening and the described second opening, forms conductive plug.
14. semiconductor devices as claimed in claim 13, it is characterised in that conductive material covering first opening with
And the surface of the substrate.
15. semiconductor devices as claimed in claim 13, it is characterised in that conductive material covering first opening,
The surface of the substrate is not covered.
16. semiconductor devices as claimed in claim 15, it is characterised in that the semiconductor devices also includes a back metal
Layer, the metal layer on back is formed at the substrate away from the side of the epitaxial layer.
17. semiconductor devices as claimed in claim 16, it is characterised in that the material of the metal layer on back is gold.
18. semiconductor devices as claimed in claim 13, it is characterised in that the thickness of the substrate is 0.2 μm~20 μm.
19. semiconductor devices as claimed in claim 13, it is characterised in that the conductive material is in copper, tungsten or aluminium
Plant or several combinations.
20. semiconductor devices as claimed in claim 13, it is characterised in that first opening is groove or through hole.
The preparation method of 21. semiconductor devices as claimed in claim 13, it is characterised in that between the source area and source electrode
Self-aligned silicide is formed with, first opening exposes the self-aligned silicide.
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| CN103035730A (en) * | 2012-12-07 | 2013-04-10 | 上海华虹Nec电子有限公司 | Radio frequency laterally diffused metal oxide semiconductor (LDMOS) device and manufacturing method thereof |
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| CN102456614B (en) * | 2010-11-01 | 2013-07-24 | 上海华虹Nec电子有限公司 | Realization method for metal source-substrate passage in radio-frequency LDMOS (laterally-diffused metal oxide semiconductor) apparatus |
| US8816476B2 (en) * | 2011-04-27 | 2014-08-26 | Alpha & Omega Semiconductor Corporation | Through silicon via processing techniques for lateral double-diffused MOSFETS |
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| CN103035730A (en) * | 2012-12-07 | 2013-04-10 | 上海华虹Nec电子有限公司 | Radio frequency laterally diffused metal oxide semiconductor (LDMOS) device and manufacturing method thereof |
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