CN102456614B - Realization method for metal source-substrate passage in radio-frequency LDMOS (laterally-diffused metal oxide semiconductor) apparatus - Google Patents
Realization method for metal source-substrate passage in radio-frequency LDMOS (laterally-diffused metal oxide semiconductor) apparatus Download PDFInfo
- Publication number
- CN102456614B CN102456614B CN 201010528076 CN201010528076A CN102456614B CN 102456614 B CN102456614 B CN 102456614B CN 201010528076 CN201010528076 CN 201010528076 CN 201010528076 A CN201010528076 A CN 201010528076A CN 102456614 B CN102456614 B CN 102456614B
- Authority
- CN
- China
- Prior art keywords
- source
- hole
- metal
- contact
- ground floor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a realization method for a metal source-substrate passage in a radio-frequency LDMOS (laterally-diffused metal oxide semiconductor) apparatus, comprising the following steps of: etching a source-substrate contact through hole by means of a self-alignment, and integrating the source-substrate contact through hole in a technique for forming the contact hole of a source region and a first metal layer, thus simultaneously forming a low-resistance passage between a source and a substrate as well as the interconnection structure of the source region and the first metal layer by performing a metal deposition once only. The realization method disclosed by the invention can greatly reduce the width of the source-substrate contact through hole, increase the density of the apparatus, and augment the gain of the apparatus. Moreover, the passage between the source and the substrate is made of metal, so that the resistance between the source and the substrate is greatly reduced, the heat dissipation of the apparatus is promoted, and the reliability of the apparatus is enhanced.
Description
Technical field
The present invention relates to the implementation method of source metal lining path in a kind of radio frequency LDMOS device.
Background technology
LDMOS is one of device commonly used in the present RF radio frequency technology.Can form low cost based on LDMOS, the RFLDMOS device of high-performance high integration is applied to the HF communication field and other are for the very high application of rate request.In order to improve the response frequency of device, how to improve operating frequency, reduction source lining via resistance is a very difficult problem, be to add the method that pushes away trap by injection, this need carry out the injection of high-energy and high dose, and after high temperature pushes away trap, the charge carrier horizontal proliferation has increased size, and the technology controlling and process precision is difficult to hold, and for the polycrystalline that mixes, does not have metal low though resistance also can reduce.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of implementation method of source metal lining path, and it can realize the source metal lining path of low-resistance.
For solving the problems of the technologies described above, the implementation method of source metal lining path of the present invention after the deposit ground floor insulating barrier, comprises the steps: on the device after forming grid
1) adopt photoetching process to define the position of source lining contact through hole, the ground floor insulating barrier of this position of etching is removed photoresist to grid oxygen afterwards;
2) follow further etching epitaxial loayer to substrate, formation source lining contact through hole;
3) adopt photoetching process to define the position of the contact hole between active area and the ground floor metal afterwards, etching ground floor insulating barrier forms contact hole;
4) depositing metal is with complete filling source lining contact through hole and contact hole;
5) employing CMP technology is removed the metal on the ground floor insulating barrier.
Implementation method of the present invention is carried out the etching that the source serves as a contrast contact through hole by autoregistration, can reduce the width of contact through hole greatly, improves the density of device, increases the gain of device.Owing to as the path between the lining of source, greatly reduced resistance and the heat radiation that helps device between the lining of source with metal.Improved the reliability of device simultaneously, and this method integrated the technology that forms of the contact hole of active area and ground floor metal level, only need a minor metal deposit just to form the interconnect architecture of low impedance path and active area and ground floor metal between the lining of source simultaneously.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the schematic flow sheet of implementation method of the present invention;
Fig. 2 is the structural representation behind the formation grid in an example of the present invention;
Fig. 3 is the structural representation behind the deposit ground floor insulating barrier in an example of the present invention;
Fig. 4 serves as a contrast the position of contact through hole and the structural representation behind etching first insulating barrier for defining the source in an example of the present invention;
Fig. 5 is the structural representation behind the etching formation source lining contact through hole in an example of the present invention;
Fig. 6 is formed with the structural representation behind the contact hole of source region and ground floor metalwork for etching in an example of the present invention;
Fig. 7 is the structural representation behind the depositing metal in an example of the present invention;
Fig. 8 is the structural representation behind the CMP removal excess metal in an example of the present invention.
Embodiment
The implementation method of source metal lining path in the radio frequency LDMOS device of the present invention, it be on the device of (see figure 2) behind the formation grid after the deposit ground floor insulating barrier (see figure 3), comprises the steps (see figure 1):
1) adopt photoetching process to define the position of source lining contact through hole, the ground floor insulating barrier of this position of etching is removed the photoresist (see figure 4) to grid oxygen afterwards.
2) follow further etching epitaxial loayer to substrate, formation source lining contact through hole (see figure 5).The hole of source lining contact through hole is wide to can be 0.2～1 micron.
3) adopt photoetching process to define the position of the contact hole between active area and the ground floor metal afterwards, etching ground floor insulating barrier forms the contact hole (see figure 6).The process of the Kong Kuanwei routine of contact hole can be 0.2～1 micron in the instantiation.In photoetching, photoresist can cover the source lining contact through hole that forms above.Etching forms after the contact hole, removes remaining photoresist.
4) depositing metal is with complete filling source lining contact through hole and contact hole (see figure 7).Optional tungsten of above-mentioned metal or copper adopt the physical sputtering sedimentation to carry out deposit.
5) employing CMP technology is removed the metal (see figure 8) on the ground floor insulating barrier.
Implementation method of the present invention is carried out the etching that the source serves as a contrast contact through hole by autoregistration, can reduce the width of contact through hole greatly, improves the density of device, increases the gain of device.Owing to as the path between the lining of source, greatly reduced resistance and the heat radiation that helps device between the lining of source with metal.Improved the reliability of device simultaneously, and this method integrated the technology that forms of the contact hole of active area and ground floor metal level, only need a minor metal deposit just to form the interconnection structure of low impedance path and active area and ground floor metal between the lining of source simultaneously.
Claims (3)
1. the implementation method of source metal lining path in the radio frequency LDMOS device is characterized in that, after the deposit ground floor insulating barrier, comprises the steps: on the device after forming grid
1) adopt photoetching process to define the position of source lining contact through hole, the ground floor insulating barrier of this position of etching is removed photoresist to grid oxygen afterwards;
2) follow further etching epitaxial loayer to substrate, formation source lining contact through hole;
3) adopt photoetching process to define the position of the contact hole between active area and the ground floor metal afterwards, the described ground floor insulating barrier of etching forms contact hole;
4) adopt the physical sputtering sedimentation to carry out depositing metal tungsten or copper, with complete filling described source lining contact through hole and described contact hole;
5) employing CMP technology is removed the metal on the described ground floor insulating barrier.
2. according to the described implementation method of claim 1, it is characterized in that: 0.2～1 micron of the Kong Kuanwei of described source lining contact through hole.
3. according to the described implementation method of claim 1, it is characterized in that: 0.2～1 micron of the Kong Kuanwei of contact hole in the described step 3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010528076 CN102456614B (en) | 2010-11-01 | 2010-11-01 | Realization method for metal source-substrate passage in radio-frequency LDMOS (laterally-diffused metal oxide semiconductor) apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010528076 CN102456614B (en) | 2010-11-01 | 2010-11-01 | Realization method for metal source-substrate passage in radio-frequency LDMOS (laterally-diffused metal oxide semiconductor) apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102456614A CN102456614A (en) | 2012-05-16 |
| CN102456614B true CN102456614B (en) | 2013-07-24 |
Family
ID=46039640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010528076 Active CN102456614B (en) | 2010-11-01 | 2010-11-01 | Realization method for metal source-substrate passage in radio-frequency LDMOS (laterally-diffused metal oxide semiconductor) apparatus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102456614B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104183499B (en) * | 2014-08-13 | 2017-06-16 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6987052B2 (en) * | 2003-10-30 | 2006-01-17 | Agere Systems Inc. | Method for making enhanced substrate contact for a semiconductor device |
| CN101699631A (en) * | 2009-11-19 | 2010-04-28 | 苏州远创达科技有限公司 | LDMOS power device with buried layer |
| CN101771049A (en) * | 2008-12-29 | 2010-07-07 | 万国半导体有限公司 | Real chip level package power metal oxide semiconductor field effect tube based on a bottom source electrode metal oxide semiconductor field effect tube |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7126193B2 (en) * | 2003-09-29 | 2006-10-24 | Ciclon Semiconductor Device Corp. | Metal-oxide-semiconductor device with enhanced source electrode |
-
2010
- 2010-11-01 CN CN 201010528076 patent/CN102456614B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6987052B2 (en) * | 2003-10-30 | 2006-01-17 | Agere Systems Inc. | Method for making enhanced substrate contact for a semiconductor device |
| CN101771049A (en) * | 2008-12-29 | 2010-07-07 | 万国半导体有限公司 | Real chip level package power metal oxide semiconductor field effect tube based on a bottom source electrode metal oxide semiconductor field effect tube |
| CN101699631A (en) * | 2009-11-19 | 2010-04-28 | 苏州远创达科技有限公司 | LDMOS power device with buried layer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102456614A (en) | 2012-05-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9536840B2 (en) | Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods | |
| CN105940483B (en) | Method for forming wrap-around contact on semiconductor device | |
| CN106257641B (en) | High resistivity semiconductor-on-insulator substrate and its manufacturing method and semiconductor devices | |
| TW201041086A (en) | SOI radio frequency switch for reducing high frequency harmonics | |
| CN104425245B (en) | Reverse-conducting insulated gate bipolar transistor npn npn manufacture method | |
| US9812428B2 (en) | Vertically integrated wafers with thermal dissipation | |
| US20220310510A1 (en) | Interconnection structure and method of manufacturing the same, and electronic device including the interconnection structure | |
| CN104241368A (en) | Lateral diffusion metal oxide semiconductor (ldmos) | |
| CN109690755A (en) | Using tungstenic adhesive layer enhancing interlinking reliability can with realize cobalt interconnection microelectronic component and method | |
| CN103219376B (en) | Gallium and preparation method thereof | |
| CN102237406A (en) | Radio frequency lateral double-diffusion metal oxide semiconductor (LDMOS) device and manufacturing method thereof | |
| TW201801140A (en) | Self-aligned build-up of topographic features | |
| TW201721755A (en) | Methods for doping a sub-fin region of a semiconductor fin structure and devices containing the same | |
| CN102456614B (en) | Realization method for metal source-substrate passage in radio-frequency LDMOS (laterally-diffused metal oxide semiconductor) apparatus | |
| US9905460B2 (en) | Methods of self-forming barrier formation in metal interconnection applications | |
| CN103219369A (en) | Device with low parasitic resistance and high electron mobility and manufacturing method thereof | |
| CN103219378B (en) | A kind of low parasitic resistance radio-frequency power device and preparation method thereof | |
| CN103219377B (en) | One realizes asymmetric self aligned RF power device of source and drain grid and preparation method thereof | |
| CN103219379A (en) | High electron mobility device adopting grid first process and preparation method thereof | |
| CN103855023A (en) | Forming method of semiconductor device and semiconductor device | |
| KR102244115B1 (en) | Modulation of magnetic properties through implantation and associated structures | |
| CN103187292B (en) | A kind of method manufacturing trench semiconductor power device | |
| KR20210039893A (en) | Gallium nitride-on-silicon devices | |
| CN103165453A (en) | High-dielectric metal gate metal oxide semiconductor (MOS) and manufacturing method thereof | |
| US20240162058A1 (en) | Tools and methods for subtractive metal patterning |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131225 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20131225 Address after: 201206 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |