CN104182202A - Oscillator and true random number generating circuit formed by same - Google Patents
Oscillator and true random number generating circuit formed by same Download PDFInfo
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- CN104182202A CN104182202A CN201310192755.1A CN201310192755A CN104182202A CN 104182202 A CN104182202 A CN 104182202A CN 201310192755 A CN201310192755 A CN 201310192755A CN 104182202 A CN104182202 A CN 104182202A
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Abstract
The invention discloses an oscillator and a true random number generating circuit formed by the same in the field of design of an integrated circuit. The oscillator adopts a novel structure; a main loop can adopt a quadrilateral, octagonal or dodecagonal structure or other structures, i.e. a 4n-gonn structure, wherein n is an integer greater than zero. The true random number generating circuit comprises a high-speed oscillator, a low-speed oscillator, an xor circuit, a clock circuit, a system clock circuit and a sampling circuit. The oscillator provides a random source for the true random number generating circuit, forms the high-speed oscillator and the low-speed oscillator and is controlled by two external enable signals a and b; signals at the output ends of the high-speed oscillator and the low-speed oscillator are different or the high-speed oscillator and the low-speed oscillator output primary random number seeds; the clock circuit and the system clock circuit control the sampling circuit to carry out sampling on the primary random number seeds for twice so as to generate a true random number sequence; the true random number generating circuit solves the problems of poor randomness and periodic generation of the true random number sequence.
Description
Technical field
The invention belongs to integrated circuit (IC) design field, relate to the true random number circuit for generating of a kind of oscillator and formation thereof, the true random number sequence that this circuit produces has height random, can be applied to and need the various safety enciphers of true random number field, RFID label as safe in height.
Background technology
Along with the development of radio communication, information security is more and more important, and communication system needs encryption and decryption technology to realize secure communication, and this just be unable to do without random number.Random number comprises pseudo random number and true random number, and pseudo random number is to realize by mathematical algorithm, determines when the Seed Sequences of its input end, and algorithm is definite, and its output signal is just determined.Pseudo random number has the feature of randomness, but output signal is periodic signal, is easily cracked, and security is poor.True random number is realized by physical features, in circuit design, common implementation method has direct amplification thermonoise method, vibration sampling method, discrete time chaos realizes method and metastable state circuit is realized method, vibration sampling method utilizes the phase noise of oscillator and shakes as stochastic source, phase noise is caused by the thermonoise of metal-oxide-semiconductor in oscillator, shake is caused by the metastable state existing in circuit, competition risk, so the randomness of the random number producing is better.Because the true random number circuit for generating implementation procedure based on vibration sampling method is simple in structure, required area is few, low in energy consumption, so used widely in encryption, decryption system and near-field communication etc.
Summary of the invention
The invention provides the true random number circuit for generating of a kind of oscillator and formation thereof, its object is to solve the poor problem of random number randomness, makes the true random number sequence generating have unpredictable and unduplicated feature.
A kind of oscillator provided by the invention, form 2n+1 stable loop and 4n oscillation circuit by 8n phase inverter, wherein n is greater than zero integer, each described stable loop comprises 1 major loop and 2n cross coupling inverter circuit, this major loop is 4n limit shape, formed by 4n described phase inverter cascade, and each phase inverter lays respectively on a limit of 4n limit shape, described 2n cross coupling inverter circuit is made up of remaining 4n described phase inverter, the described phase inverter that each described cross coupling inverter circuit forms loop by two cascades is formed, and on each axis of symmetry of described 4n limit shape, two points are all connected with two points on a described cross coupling inverter circuit, the described reverser that each described oscillation circuit forms loop by 2n+1 cascade forms, and in the middle of this 2n+1 phase inverter, 2n phase inverter is positioned on described major loop, and 1 phase inverter is positioned on described cross coupling inverter circuit.
The true random number circuit for generating being made up of described oscillator provided by the invention, comprises quick oscillation device, oscillator, XOR circuit, clock circuit, system clock circuit and sample circuit at a slow speed;
Quick oscillation device is connected with enable signal b with two outside enable signal a respectively with the input end of oscillator at a slow speed, quick oscillation device is with the output terminal of oscillator and the input end of XOR circuit are connected at a slow speed, outside enable signal c is connected with clock circuit input end, clock circuit output terminal, XOR circuit output terminal and system clock circuit output terminal are all connected from the different input ends of sample circuit, and the output terminal of sample circuit is true random number sequence output terminal;
In the time that enable signal a and enable signal b are " 1 " simultaneously, quick oscillation device and oscillator starting of oscillation at a slow speed, quick oscillation device produces high-frequency signal, and oscillator produces low frequency signal at a slow speed, produces behind the door elementary random number seed through XOR; When enable signal c is " 1 ", clock circuit produces fixed frequency signal, and the signal that this signal and systems clock circuit produces is sampled respectively to elementary random number seed, produces true random number sequence after double sampling.
Described quick oscillation device and at a slow speed oscillator are the oscillators that major loop adopts above-mentioned 4n limit shape structure, by regulating the size of metal-oxide-semiconductor to realize the output of different frequency, for ensureing the randomness of true random number, oscillation frequency is in 10 times of left and right of clock circuit frequency, quick oscillation frequency is greater than 10 times of clock circuit frequencies, and oscillation frequency is less than 10 times of clock frequencies at a slow speed.
Described XOR circuit is made up of the exclusive or logic gate of two inputs, realizes XOR function.
Described clock circuit, for providing clock signal to sample circuit, carries out elementary sampling to elementary random number seed, thereby produces elementary random number sequence.The concrete structure of described clock circuit is made up of the phase inverter (S in loop five cascades
25, S
26, S
27, S
28, S
29) composition, each phase inverter input endpoint or exit point
with the metal-oxide-semiconductor electric capacity (M of (GND) over the ground
1, M
2, M
3, M
4, M
5) be connected, realize delay feature, and by regulating metal-oxide-semiconductor capacitor size to realize required output frequency.
Described system clock circuit provides clock signal by broadcast algorithm logical timer, and the low-frequency clock that broadcast algorithm logical timer is digital circuit, for elementary random number sequence is sampled, produces required true random number sequence.
Described sample circuit comprises elementary sampling d type flip flop and secondary sampling d type flip flop, XOR circuit output is connected with the input end of the elementary sampling d type flip flop of sample circuit, the output terminal of clock circuit accesses the clock signal input terminal of elementary sampling d type flip flop, and XOR circuit output end signal is carried out to elementary sampling; Elementary sampling d type flip flop output terminal is connected with the input end of the secondary sampling d type flip flop in sample circuit, the output terminal of system clock circuit accesses the clock signal input terminal of secondary sampling d type flip flop, thereby the output signal to elementary sampling d type flip flop is sampled, the output terminal of secondary sampling d type flip flop is true random number sequence output terminal.
The present invention have the quick oscillation device of larger phase noise and shake and at a slow speed oscillator as stochastic source, by the raising randomness of repeatedly sampling, design a kind of true random number circuit for generating based on vibration sampling method, solve the poor problem of random number randomness, the true random number sequence of generation has unpredictable and unduplicated feature.Particularly, the present invention compared with prior art has following technique effect:
(1), in the present invention, oscillator is subject to phase noise and the larger frequency of effect of jitter for generation of one.The just fast start-up once oscillator powers on, the advantage of oscillatory circuit is to forgive many loops, and stable loop is mutually nested with oscillation circuit, " 0 " in circuit and " 1 " signal ceaselessly overturn, this makes to be full of in circuit wired-AND logic circuits and race hazard mechanism, thereby causes output frequency unstable.In addition, this circuit is very sensitive to supply voltage and external noise interference, and in the time there is interference in working environment, output signal will produce larger amount of jitter, and this is for the further randomness that improves true random number sequence of true random number circuit for generating.
(2) oscillator major loop of the present invention is adopted as the oscillator of quadrilateral, octagon, dodecagon etc., and signal race hazard is serious, can produce phase noise and the large frequency of shake; Wherein, major loop is that compared with the oscillator of octagon, dodecagon etc. is tetragonal oscillator with major loop, stable loop and oscillation circuit increase, and signal race hazard is more serious, thereby can produce phase noise and the larger frequency of shake.
(3) because true random number circuit for generating is using oscillator as stochastic source, and the randomness of oscillator itself is to be caused by the phase noise in physical characteristics and shake, this just makes true random number circuit for generating produce unpredictable and unduplicated true random number sequence.
Brief description of the drawings
Fig. 1 is the oscillator circuit structure schematic diagram taking quadrilateral as major loop;
Fig. 2 is the oscillator circuit structure schematic diagram taking octagon as major loop;
Fig. 3 is the structural representation of true random number circuit for generating;
Fig. 4 is the waveform schematic diagram of true random number circuit for generating;
Fig. 5 is the clock circuit structural representation that forms loop with five phase inverter cascades.
Embodiment
Analyze the true random number circuit for generating of a kind of oscillator and formation thereof according to accompanying drawing, following is only exemplary explanation, and the application of oscillator and true random number circuit for generating is not constituted any limitation.In each embodiment of described the present invention, involved technical characterictic just can combine mutually as long as do not form each other conflict below.
Fig. 1 is the oscillator circuit structure schematic diagram taking quadrilateral as major loop, in the middle of the topological structure of this oscillator, comprises 4 nodes, is respectively 1., 2., 3., 4., and node and node are by phase inverter (S
1, S
2, S
3, S
4, S
5, S
6, S
7, S
8) connect.Oscillator agent structure is 3 stable loops and 4 oscillation circuits.In the middle of stable loop, have 1 major loop and 2 cross coupling inverter circuit, major loop for 1. → 2. → 3. → 4. → 1., cross coupling inverter circuit for 1. → 3. → 1. and 2. → 4. → 2..Oscillation circuit is that 3 phase inverter cascades form loops, 2., 3. 1., 2. 1. 4 oscillation circuits be respectively → 2. → 3. → → 3. → 4. → → 4. → 1. → 3., 4. → 1. → 2. → 4..By metal-oxide-semiconductor size is set, obtain different output frequencies, quick oscillation device frequency is greater than oscillator output frequency at a slow speed.
Fig. 2 is the oscillator circuit structure schematic diagram taking octagon as major loop, and the topological structure of oscillator is that circuit structure in Fig. 1 is improved to the new departure putting forward, and its larger phase noise and shake have improved the randomness of true random number sequence.Topological structure comprises 8 nodes, be respectively 5., 6., 7., 8., 9., 10.,
node and node are by phase inverter (S
9, S
10, S
11, S
12, S
13, S
14, S
15, S
16) connect.Oscillator agent structure is 5 stable loops and 8 oscillation circuits.In the middle of stable loop, have 1 major loop and 4 cross coupling inverter circuit, major loop is
cross coupling inverter circuit for 5. → 9. → 5., 6. → 10. → 6.,
oscillation circuit is that 5 grades of phase inverter cascades form loop, and 8 oscillation circuits are respectively
Described oscillator major loop can be not only quadrilateral structure, can also be the structures such as octagon, dodecagon, be 4n limit shape structure, n be greater than zero integer, 4n phase inverter cascade forms a stable loop, and each phase inverter is on each limit of 4n limit shape.Two points on the shape axis of symmetry of 4n limit are connected with two points on a cross coupling inverter circuit, and cross coupling inverter circuit is made up of the phase inverter (S in loop two cascades
17, S
18or S
19, S
20or S
21, S
22or S
23, S
24) institute forms, total 2n cross coupling inverter circuit.
Fig. 3 is the structural representation of true random number circuit for generating, comprise quick oscillation device, oscillator at a slow speed, XOR circuit, clock circuit, system clock circuit and sample circuit, two outside enable signal a and enable signal b are connected with the input end of oscillator at a slow speed with quick oscillation device respectively, quick oscillation device is with the output terminal of oscillator and the input end of XOR circuit are connected at a slow speed, outside enable signal c is connected with clock circuit input end, clock circuit output terminal, XOR circuit output terminal is all connected from the different input ends of sample circuit with system clock circuit output terminal, the output terminal of sample circuit is true random number sequence output terminal.
Fig. 4 is the waveform schematic diagram of true random number circuit for generating, and it is tetragonal topological structure that quick oscillation device and at a slow speed oscillator adopt major loop, and its course of work is as follows,
Step 1: quick oscillation device and at a slow speed oscillator power on, in the time that enable signal a and enable signal b are " 1 " simultaneously, quick oscillation device and oscillator starting of oscillation at a slow speed, quick oscillation device produces high-frequency signal, oscillator produces low frequency signal at a slow speed, produces behind the door elementary random number seed through XOR.
Step 2: clock circuit powers on, enable signal c is " 1 " signal, clock circuit starting of oscillation also provides clock signal to elementary sampling d type flip flop, and elementary random number seed is sampled, and exports elementary random number sequence.
Step 3: elementary random number sequence enters secondary sampling d type flip flop, and system clock circuit is started working, and elementary random number sequence is carried out to double sampling, produces required true random number sequence.
Whole process is that " 1 " is t to generating true random number sequence elapsed-time standards from enable signal a and enable signal b simultaneously, should be noted that enable signal a and enable signal b are if not enable simultaneously, will cause quick oscillation device and uncertain phase differential between oscillator at a slow speed, thereby increased the otherness between double sampling, this can improve the randomness of true random number sequence.
Fig. 5 is the clock circuit structural representation that forms loop with 5 phase inverter cascades, and loop comprises 5 nodes, is respectively
node and node are by phase inverter (S
25, S
26, S
27, S
28, S
29) connect, oscillation circuit is
each node has accessed a metal-oxide-semiconductor electric capacity (M over the ground
1, M
2, M
3, M
4, M
5), in the time that enable signal c is " 1 ", once the just starting oscillation that powers on regulates metal-oxide-semiconductor size to obtain different output frequencies, thereby to quick oscillation device and at a slow speed oscillator pass through the elementary random number seed that XOR produces behind the door and carry out elementary sampling.
The foregoing is only the preferred embodiment of the present invention; the specific embodiment of the invention is not limited by this; to being familiar with the scientific research of this technical field and technician after know-why of the present invention and embodiment are announced; can make some amendments and replacement to it; all should contain in the protection domain of this invention; therefore, the protection domain of this invention is as the criterion with the scope of claim.
Claims (9)
1. an oscillator, it is characterized in that, it forms 2n+1 stable loop and 4n oscillation circuit by 8n phase inverter, wherein n is greater than zero integer, each described stable loop comprises 1 major loop and 2n cross coupling inverter circuit, this major loop is 4n limit shape, formed by 4n described phase inverter cascade, and each phase inverter lays respectively on a limit of 4n limit shape, described 2n cross coupling inverter circuit is made up of remaining 4n described phase inverter, the described phase inverter that each described cross coupling inverter circuit forms loop by two cascades is formed, and on each axis of symmetry of described 4n limit shape, two points are all connected with two points on a described cross coupling inverter circuit, the described reverser that each described oscillation circuit forms loop by 2n+1 cascade forms, and in the middle of this 2n+1 phase inverter, 2n phase inverter is positioned on described major loop, and 1 phase inverter is positioned on described cross coupling inverter circuit.
2. the true random number circuit for generating being made up of oscillator described in claim 1, is characterized in that, this true random number circuit for generating comprises quick oscillation device, oscillator, XOR circuit, clock circuit, system clock circuit and sample circuit at a slow speed; Quick oscillation device and at a slow speed oscillator are the oscillators that major loop adopts described 4n limit shape structure;
Quick oscillation device is connected with enable signal b with two outside enable signal a respectively with the input end of oscillator at a slow speed, quick oscillation device is with the output terminal of oscillator and the input end of XOR circuit are connected at a slow speed, outside enable signal c is connected with clock circuit input end, clock circuit output terminal, XOR circuit output terminal and system clock circuit output terminal are all connected from the different input ends of sample circuit, and the output terminal of sample circuit is true random number sequence output terminal;
In the time that enable signal a and enable signal b are " 1 " simultaneously, quick oscillation device and oscillator starting of oscillation at a slow speed, quick oscillation device produces high-frequency signal, and oscillator produces low frequency signal at a slow speed, produces behind the door elementary random number seed through XOR; When enable signal c is " 1 ", clock circuit produces fixed frequency signal, and the signal that this signal and systems clock circuit produces is sampled respectively to elementary random number seed, produces true random number sequence after double sampling.
3. true random number circuit for generating according to claim 2, is characterized in that, quick oscillation frequency is greater than 10 times of clock circuit frequencies, and oscillation frequency is less than 10 times of clock frequencies at a slow speed.
4. true random number circuit for generating according to claim 2, is characterized in that, described XOR circuit is made up of the exclusive or logic gate of two inputs, realizes XOR function.
5. true random number circuit for generating according to claim 2, is characterized in that, described clock circuit, for providing clock signal to sample circuit, carries out elementary sampling to elementary random number seed, thereby produces elementary random number sequence.
6. true random number circuit for generating according to claim 2, it is characterized in that, described system clock circuit provides clock signal by broadcast algorithm logical timer, broadcast algorithm logical timer is the low-frequency clock of digital circuit, for elementary random number sequence is sampled, produce required true random number sequence.
7. according to arbitrary described true random number circuit for generating in claim 2 to 6, it is characterized in that, described sample circuit comprises elementary sampling d type flip flop and secondary sampling d type flip flop, XOR circuit output is connected with the input end of the elementary sampling d type flip flop of sample circuit, the output terminal of clock circuit accesses the clock signal input terminal of elementary sampling d type flip flop, and XOR circuit output end signal is carried out to elementary sampling; Elementary sampling d type flip flop output terminal is connected with the input end of the secondary sampling d type flip flop in sample circuit, the output terminal of system clock circuit accesses the clock signal input terminal of secondary sampling d type flip flop, thereby the output signal to elementary sampling d type flip flop is sampled, the output terminal of secondary sampling d type flip flop is true random number sequence output terminal.
8. according to arbitrary described true random number circuit for generating in claim 2 to 6, it is characterized in that, the phase inverter that described clock circuit forms loop by five cascades forms, each phase inverter input endpoint or exit point are connected with metal-oxide-semiconductor electric capacity over the ground, realize delay feature, and by regulating metal-oxide-semiconductor capacitor size to realize required output frequency.
9. according to arbitrary described true random number circuit for generating in claim 2 to 6, it is characterized in that, the major loop of described oscillator is quadrilateral structure.
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| CN201310192755.1A CN104182202B (en) | 2013-05-22 | 2013-05-22 | There is circuit in the true random number of a kind of oscillator and its composition |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106209099A (en) * | 2016-06-28 | 2016-12-07 | 中国电子科技集团公司第二十四研究所 | Production line analog-digital converter dynamic compensating device based on true random number sequence |
| CN106325814A (en) * | 2016-08-12 | 2017-01-11 | 西安电子科技大学 | Real random number generator based on double-loop coupling oscillation circuit |
| CN107506174A (en) * | 2017-08-14 | 2017-12-22 | 深圳大学 | Real random number generator based on hungry electric current ring oscillator |
| CN111352608A (en) * | 2020-02-28 | 2020-06-30 | 电子科技大学 | Low-overhead FPGA (field programmable Gate array) basic true random number generation system |
| CN113377337A (en) * | 2021-07-07 | 2021-09-10 | 山东方寸微电子科技有限公司 | True random number generator and chip |
-
2013
- 2013-05-22 CN CN201310192755.1A patent/CN104182202B/en active Active
Non-Patent Citations (7)
| Title |
|---|
| ERIK J. PANKRATZ等: ""Multiloop High-Power-Supply-Rejection Quadrature Ring Oscillator"", 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 * |
| KNUT WOLD等: ""Analysis and enhancement of random number generator in FPGA based on oscillator rings"", 《INTERNATIONAL JOURNAL OF RECONFIGURABLE COMPUTING》 * |
| MIECZYSLAW JESSA等: ""Enhancing the Randomness of a Combined True Random Number Generator Based on the Ring Oscillator Sampling Method"", 《2011 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS》 * |
| 吴燕雯等: ""一种基于噪声的真随机数发生器的ASIC设计与实现"", 《微电子学》 * |
| 周干民等: ""一种基于锁相环的真随机数发生器"", 《电子与信息学报》 * |
| 李蕾等: ""应用于UHF RFID标签的低功耗真随机数发生器"", 《电路与***学报》 * |
| 郑小岳等: ""基于振荡采样的真随机数发生器IP设计"", 《江南大学学报（自然科学版）》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106209099A (en) * | 2016-06-28 | 2016-12-07 | 中国电子科技集团公司第二十四研究所 | Production line analog-digital converter dynamic compensating device based on true random number sequence |
| CN106209099B (en) * | 2016-06-28 | 2019-06-04 | 中国电子科技集团公司第二十四研究所 | Production line analog-digital converter dynamic compensating device based on true random number sequence |
| CN106325814A (en) * | 2016-08-12 | 2017-01-11 | 西安电子科技大学 | Real random number generator based on double-loop coupling oscillation circuit |
| CN106325814B (en) * | 2016-08-12 | 2018-11-20 | 西安电子科技大学 | True Random Number Generator based on double-ring coupled oscillating circuit |
| CN107506174A (en) * | 2017-08-14 | 2017-12-22 | 深圳大学 | Real random number generator based on hungry electric current ring oscillator |
| CN107506174B (en) * | 2017-08-14 | 2020-07-14 | 深圳大学 | Starvation current ring oscillator-based true random number generator |
| CN111352608A (en) * | 2020-02-28 | 2020-06-30 | 电子科技大学 | Low-overhead FPGA (field programmable Gate array) basic true random number generation system |
| CN111352608B (en) * | 2020-02-28 | 2022-08-02 | 电子科技大学 | Low-overhead FPGA (field programmable Gate array) basic true random number generation system |
| CN113377337A (en) * | 2021-07-07 | 2021-09-10 | 山东方寸微电子科技有限公司 | True random number generator and chip |
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Effective date of registration: 20200709 Address after: 215000 Jinmao Road 888, Zhoushi Town, Kunshan City, Suzhou City, Jiangsu Province Patentee after: Taixin Intelligent Technology (Kunshan) Co.,Ltd. Address before: 430074 Hubei Province, Wuhan city Hongshan District Luoyu Road No. 1037 Patentee before: HUAZHONG University OF SCIENCE AND TECHNOLOGY |