CN104181968B - A kind of low pressure difference linear voltage regulator with slope start-up circuit - Google Patents
A kind of low pressure difference linear voltage regulator with slope start-up circuit Download PDFInfo
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- CN104181968B CN104181968B CN201410370014.2A CN201410370014A CN104181968B CN 104181968 B CN104181968 B CN 104181968B CN 201410370014 A CN201410370014 A CN 201410370014A CN 104181968 B CN104181968 B CN 104181968B
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Abstract
The invention provides a kind of low pressure difference linear voltage regulator with slope start-up circuit, this voltage stabilizer comprises start-up circuit (201) and voltage stabilizer main circuit (202); Wherein start-up circuit (201), on the one hand for generation of two-way slope enable signal EN and EN_b, as the input signal of voltage stabilizer main circuit Enable Pin, the opposing party is used for the input of output voltage signal Vro as voltage stabilizer main circuit, described voltage signal Vro slope rises, is finally stabilized in a magnitude of voltage; Voltage stabilizer main circuit (202), under the control of two-way enable signal EN and EN_b, for carrying out scale amplifying to described voltage signal Vro, exports a burning voltage Vo.Low pressure difference linear voltage regulator of the present invention effectively can prevent surge current when electrifying startup, and its electric current consumed is very low.
Description
Technical field
The invention belongs to low pressure difference linear voltage regulator (LDO) technical field, be specifically related to a kind of LDO with slope start-up circuit.
Background technology
In recent years, along with the fast development of the industries such as communication, computing machine and consumer electronics, people increase day by day to the demand of electronic product, and this has also driven the industry development of integrated circuit related with same chip.In electronic product, especially in the middle of the portable type electronic products such as mobile phone, digital camera, palm PC, in order to improve power-efficient, extending battery life, power management chip is often needed to provide voltage to nurse one's health to battery; And whether stablizing the performance impact of circuit of supply voltage is huge.LDO is that one can provide burning voltage, and has the Power Management Devices of energy-efficient, is widely used in many occasions.
Fig. 1 (a) is common LDO structural drawing, by control circuit, power tube M
p, feedback resistance R1 and R2, load capacitance C
oand pull-up resistor R
l.LDO when powering on, V
dDascending velocity very fast, usually in us magnitude, even likely faster.Now LDO loop not yet normally works, and control circuit is also in power up.But the size of power tube Mp is very large, causes its parasitic gate electric capacity also comparatively large, need in power up Mp parasitic gate electric capacity C
pGcharging, therefore Mp grid voltage V
pGascending velocity is slower.
From the above mentioned, the source electrode ascending velocity of Mp is fast, and grid ascending velocity is slow, and the size of Mp is very large, can cause like this in the process of electrifying startup, Mp will there will be very large current impulse, be referred to as surge current, as shown in Fig. 1 (b), considerably beyond the ability to bear of chip.If the serviceable life of chip if things go on like this, will be affected.Further, in the middle of some application scenarios, V
dDby USB system power supply, the USB interface as computer is charged to handheld device.In the middle of these application scenarios, if to V when LDO powers on
dDextract excessive electric current, exceed the rated current of USB electric power system, will likely cause electric power system to make a mistake and restart, and even break down.Therefore, the heavy current pulse that when avoiding electrifying startup, LDO occurs becomes particularly important.Generally can add what is called " soft start " circuit in the application, the power up of LDO is protected.
Existing soft Starting Technology has several, one is adopt the devices such as off chip resistor electric capacity, output voltage is made slowly to increase, ensure the appearance not having surge current, as shown in Figure 2, document [1] Soft-StartCircuitsforLDOLinearRegulators, TexasInstrumentsInc., Dallas, TX, 2003.WhitePaper. [Online] .Available:http: provide in //focus.ti.com/lit/an/slyt096/slyt096.pdf and use sheet external component to carry out soft start; Two is adopt sheet inner control circuit to realize soft start, as shown in Fig. 3 (a), document [2] M.Al-ShyoukhandL.Hoi, " ACompactRamp-BasedSoft-StartCircuitforVoltageRegulators, " CircuitsandSystemsII:ExpressBriefs, IEEETransactionson, vol.56, pp.535-539,2009, the Vref terminal voltage of error amplifier slowly rises in the mode on slope, and the mode with slope also slowly rises by output voltage.After enable EN signal effectively, also there will not be large surge current.
But this several method has shortcoming, first method, because employ the outer components and parts of a large amount of sheets, can increase cost and the volume of electronic product; After second method only ensure that EN signal effectively, there is no the appearance of surge current, but when VDD powers on, still likely occur surge current; Because when VDD power-up speeds is exceedingly fast (as hundred nanosecond orders), M
pgrid voltage slower than source voltage ascending velocity, LDO can be made to flow through very large pulse current, as shown in Fig. 3 (b).
Summary of the invention
In view of this, the object of this invention is to provide a kind of LDO with slope start-up circuit, LDO of the present invention effectively can prevent surge current when electrifying startup, and its electric current consumed is very low.
To achieve these goals, the technical solution adopted in the present invention is:
With a low pressure difference linear voltage regulator for slope start-up circuit, it comprises start-up circuit and voltage stabilizer main circuit;
Start-up circuit, on the one hand for generation of two-way slope enable signal EN and EN_b, as the input signal of voltage stabilizer main circuit Enable Pin, the opposing party is used for the input of output voltage signal Vro as voltage stabilizer main circuit, described voltage signal Vro slope rises, is finally stabilized in a magnitude of voltage.The input end Vri of start-up circuit and reference voltage source export V
bGbe connected, the Enable Pin Start_up of start-up circuit is directly connected with direct supply VDD, also can control separately by a control signal.
Start-up circuit comprises the first promoter circuit and the second promoter circuit;
First promoter circuit, for generation of two-way slope enable signal EN and EN_b; Described first promoter circuit comprises on three phase inverters, three Schmidt triggers, four electric capacity, two slopes and rises unit and two slope decline unit;
The inside annexation of the first promoter circuit is: the input end of the first phase inverter is as the Enable Pin Start_up of start-up circuit, and its output terminal is connected with the input end the first slope rising unit; The output terminal first slope rising unit is connected with the input end of the first Schmidt trigger with one end of the first electric capacity respectively; The output terminal of the first Schmidt trigger is connected with the input end of the second phase inverter with the input end the second slope rising unit respectively; The output terminal second slope rising unit is connected with one end of the second electric capacity, and as the ramp-up signal output terminal EN in the enable signal of described two-way slope; The output terminal of the second phase inverter is connected with the input end of the first slope decline unit, the output terminal of the first slope decline unit is connected with the input end of the second Schmidt trigger with one end of the 3rd electric capacity respectively, and as the ramp-down signal output terminal EN_b in the enable signal of described two-way slope; The output terminal of the second Schmidt trigger is connected with the input end of the second slope decline unit, and the output terminal of the second slope decline unit is connected with the input end of the 3rd Schmidt trigger with one end of the 4th electric capacity respectively; The output terminal of the 3rd Schmidt trigger is connected with the input end of the 3rd phase inverter; The other end of the first electric capacity and the second electric capacity is all connected to ground GND, and the other end of the 3rd electric capacity and the 4th electric capacity is all connected to direct supply VDD.
Second promoter circuit, rises to a burning voltage from 0 current potential in the mode on slope for making output voltage Vro; Second promoter circuit comprises comparer, two phase inverters, three PMOS, two NMOS tube, the first current source and the 5th electric capacity.
The inside annexation of the second promoter circuit is: the end of oppisite phase of comparer is connected with the source electrode of the 3rd PMOS, and as an input end Vri of start-up circuit; The in-phase end of comparer is connected with the drain electrode of the 3rd PMOS respectively, the source electrode of the 4th PMOS and the drain electrode of drain electrode, the 5th PMOS, the drain electrode of the 4th NMOS tube and the 5th electric capacity one end be connected; The output terminal VO_Com of comparer is connected with the drain electrode of the 3rd NMOS tube with the input end of the 4th phase inverter respectively; The output terminal of the 4th phase inverter is connected with the grid of the 3rd PMOS with the input end of the 5th phase inverter respectively; The output terminal of the 5th phase inverter is connected with the grid of the 5th PMOS with the grid of the 4th PMOS respectively; The drain electrode of the 5th PMOS is connected with the output terminal of the first current source; The input end of the first current source is connected with direct supply VDD; The other end of the source electrode of the 3rd NMOS tube, the source electrode of the 4th NMOS tube and the 5th electric capacity is all connected to ground GND;
The output terminal EN_SS of the 3rd phase inverter is connected with the grid of the 4th NMOS tube with the grid of the 3rd NMOS tube respectively.
First slope rising unit and the second slope rise unit is same circuits structure, and described first slope decline unit and the second slope decline unit are same circuits structure.
Slope rises unit and comprise the 6th PMOS, the 5th NMOS tube and the second current source.Its annexation is: the grid of the 6th PMOS is connected with the grid of the 5th NMOS tube, and as slope rising the input end of unit; The drain electrode of the 6th PMOS is connected with the drain electrode of the 5th NMOS tube, and as slope rising the output terminal of unit; The source electrode of the 6th PMOS is connected with the output terminal of the second current source; The input end of the second current source is connected with direct supply VDD; The source electrode of the 5th NMOS tube is connected to ground GND.
Slope decline unit comprises the 7th PMOS, the 6th NMOS tube and the 3rd current source; Its annexation is: the grid of the 7th PMOS is connected with the grid of the 6th NMOS tube, and as the input end of slope decline unit; The drain electrode of the 7th PMOS is connected with the drain electrode of the 6th NMOS tube, and as the output terminal of slope decline unit; The source electrode of the 7th PMOS is connected with direct supply VDD; The source electrode of the 6th NMOS tube is connected with the input end of the 3rd current source, and the output terminal of the 3rd current source is connected to ground GND.
The value of described second electric capacity is less than the value of described 3rd electric capacity, ensures that following characteristics is achieved: described ramp-up signal EN rises to VDD current potential from 0 current potential with ramp system, and described ramp-down signal EN_b drops to 0 current potential from VDD current potential; The Time Created of EN is less than the Time Created of EN_b, and when EN rises to the moment of VDD current potential just, the current potential of EN_b is greater than the threshold voltage of the first NMOS tube (NM1).
Voltage stabilizer main circuit, under the control of two-way enable signal EN and EN_b, for carrying out amplification output one burning voltage Vo to voltage signal Vro.
Voltage stabilizer main circuit comprises the first PMOS, the first NMOS tube, error amplifier OP1, impact damper, power tube, the feedback unit, pull-up resistor and the output capacitance that are made up of the first resistance and the second resistance; Wherein
The grid of the first PMOS is connected with the output terminal EN of described start-up circuit, and the drain electrode of the first PMOS is connected with the grid of power tube, and the source electrode of the first PMOS is connected with direct supply VDD; The grid of the first NMOS tube is connected with the output terminal EN_b of described start-up circuit, the drain electrode of the first NMOS tube and the output terminal V of error amplifier
o1be connected, the source electrode of the first NMOS tube is connected with ground GND;
Impact damper is made up of the second PMOS and the second NMOS tube; The grid of the second PMOS is connected with its drain electrode, and is connected with the drain electrode of the second NMOS tube with the grid of power tube respectively; The source electrode of the second PMOS is connected with direct supply VDD; The grid of the second NMOS tube and the output terminal V of error amplifier OP1
o1be connected, the source electrode of the second NMOS tube is connected with ground GND;
The in-phase end V of error amplifier OP1
refbe connected with the output terminal Vro of start-up circuit, the end of oppisite phase V of error amplifier OP1
fbin access feedback unit, the first resistance is connected with the second resistance part;
The source electrode of power tube is connected with direct supply VDD; The drain electrode of power tube is connected with one end of one end of the first resistance, one end of output capacitance and pull-up resistor respectively, and the other end of pull-up resistor and the other end of output capacitance are connected to GND; The two ends of the second resistance are connected with GND with the other end of the first resistance respectively; The drain electrode of power tube is as the output end vo of voltage stabilizer main circuit.
Beneficial effect:
The present invention adopts two promoter circuit, produces a two-way slope enable signal EN and EN_b and road ramp signal Vro respectively, carries out electrifying startup to low differential voltage linear voltage stabilizer circuit.Two-way slope enable signal EN and EN_b is for starting voltage stabilizer loop, and another road ramp signal Vro is used for arranging reference voltage to voltage stabilizer, makes the voltage power up transition of each node of voltage stabilizer main circuit steady, especially power tube M
pgrid voltage there is not large voltage fluctuation.Based on above-mentioned feature, adopt design of the present invention, the surge current of low pressure difference linear voltage regulator in power up is effectively suppressed.The present invention simultaneously adopts start-up circuit to be that sheet realizes, and can start, reduce volume and the cost of electronic product without the need to the outer components and parts of sheet.
Accompanying drawing explanation
The waveform schematic diagram of voltage stabilizer power up shown in the structural drawing (b) figure (a) of the common low pressure difference linear voltage regulator of Fig. 1 (a);
Fig. 2 adopts the soft start schematic diagram of sheet external component;
Fig. 3 adopts the soft starting circuit figure of sheet upslope benchmark;
The low differential voltage linear voltage stabilizer circuit figure of Fig. 4 band slope start-up circuit;
The each node signal waveform of circuit shown in Fig. 4 schematic diagram in Fig. 5 power up;
The detailed circuit diagram of Fig. 6 slope start-up circuit;
Fig. 7 slope rises circuit diagram and the input-output characteristic curve figure of unit and slope decline unit;
The input-output characteristic curve figure of Schmidt trigger in Fig. 8 Fig. 4;
The signal waveforms of low pressure difference linear voltage regulator when Fig. 9 does not have a slope start-up circuit;
Figure 10 do not have slope start enable signal EN and EN_b time low pressure difference linear voltage regulator signal waveforms;
The signal waveforms of low pressure difference linear voltage regulator when Figure 11 contains slope start-up circuit
In figure, each sequence number represents respectively:
PM1---the first PMOS; PM2---the second PMOS; PM3---the 3rd PMOS;
PM4---the 4th PMOS; PM5---the 5th PMOS; PMu---the 6th PMOS;
PMd---the 7th PMOS; NM1---the first NMOS tube; NM2---the second NMOS tube;
NM3---the 3rd NMOS tube; NM4---the 4th NMOS tube; NMu---the 5th NMOS tube;
NMd---the 6th NMOS tube; Ibs---the first current source; Ibr1---the second current source;
Ibr2---the 3rd current source.
Embodiment
Illustrate below in conjunction with accompanying drawing and technical scheme of the present invention is described in detail.
According to exemplary embodiment of the present invention, be the circuit diagram of the low pressure difference linear voltage regulator 200 of band slope start-up circuit with reference to figure 4, Fig. 4.As shown in Figure 4, low pressure difference linear voltage regulator 200 comprises start-up circuit 201 and voltage stabilizer main circuit 202.The startup control end Start_up of start-up circuit 201 and direct supply V
dDbe connected, also can control separately, in the middle of following embodiment describes, be connected to example with Start_up and VDD be described.
In Fig. 4, voltage current waveform such as Fig. 5 of some key events illustrates; With reference to figure 4 and Fig. 5, at t
1in the moment, whole low pressure difference linear voltage regulator 200 circuit starts the V that powers on
dDrise, ramp-up signal EN is in 0 current potential, ramp-down signal EN_b and V
dDascending velocity is identical, and reference voltage input Vref, the output end vo of voltage stabilizer main circuit 202 are all in 0 current potential.At described V
dDin uphill process, the first PMOS PM1 is in conducting state, and the first PMOS PM1 will carry out rapid charge to the parasitic gate electric capacity of power tube Mp, makes grid voltage V
pGwith source voltage V
dDascending velocity be consistent, be cut-off state in the process that also namely power tube Mp rises at VDD, there will not be the situation of the current impulse spike of power tube Mp, flow through the electric current I of power tube Mp
mpbe almost 0.First NMOS tube NM1 is also in conducting state, and object makes the second NMOS tube NM2 grid be in 0 current potential, and the second NMOS tube NM2 is in cut-off state, prevents described V
dDin uphill process, the first PMOS PM1 and the second NMOS tube NM2 defines the low impedance path of power supply to ground, occurs by from the first PMOS PM1 to the current impulse of the second NMOS tube NM2.
At described V
dDafter uphill process, at t
2in the moment, described ramp-up signal EN will rise in ramp voltage mode, and described ramp-down signal EN_b will decline with ramp system; Δ t after powering on from the t1 moment
1time to be used for etc. being ready to use in as start-up circuit provides the reference source circuit of direct supply and reference voltage source to set up completely.At t
3in the moment, described ramp-up signal EN arrives V
dDcurrent potential; In the t4 moment, described ramp-down signal EN_b arrives V
thncurrent potential, V
thnfor the threshold voltage of NM1; In the t5 moment, described ramp-down signal EN_b arrives 0 current potential.Δ t
2for the Time Created of described ramp-up signal EN, Δ t
2+ Δ t
3for the Time Created of described ramp-down signal EN_b.Described two-way slope enable signal EN, EN_b adopt slope and do not adopt the mode of step signal, are to prevent power tube Mp grid voltage V
pGfrom V
dDwhen current potential declines too sharply, power tube Mp is caused to occur current spike.
At t
3in the moment, the first PMOS PM1 ends completely, to the second PMOS PM2 without control action, and now the first NMOS tube NM1 still conducting.From t
4after moment, NM1 starts to turn off gradually, and due to the effect of error amplifier 203, the grid voltage of NM2 starts to rise, thus V
pGstart the certain potentials that declines.At t
5in the moment, EN_b signal drops to 0 current potential, and NM1 turns off completely, and no longer include control action to error amplifier 203 and impact damper 204, voltage stabilizer main circuit 202 starts to enter normal operating conditions.From EN_b sets up end to Vref, rising needs through Δ t
4time delay, Vref rises to V from 0 current potential
bGneed Δ t
5time.From t
6in the moment, Vref rises to reference voltage source V from 0 current potential in the mode on slope
bG, and V
pGstart slowly to decline with ramp system, flow through the electric current I of power tube Mp
mpstart to increase with ramp system, output voltage Vo also increases with ramp system.From t
7moment starts voltage stabilizer and enters normal operating conditions.
Because whole start-up course is all carry out in the mode on slope, each node there will not be level saltus step sharply, and whole circuit does not all occur current spike.
Fig. 6 is the specific implementation circuit realizing slope start-up circuit 201 in Fig. 4, and slope start-up circuit 201 comprises the first promoter circuit 310 and the second promoter circuit 320.
Two slopes that first promoter circuit 310 comprises rise unit 311,312 and two slope decline unit 313,314 and be respectively identical structure, its specific implementation circuit represents in the figure 7.
As shown in Figure 7, slope rises unit and comprise PMOS PMu, NMOS tube NMu and current source Ibr1.Its annexation is: the grid of the 6th PMOS PMu is connected with the grid of the 5th NMOS tube NMu, and as slope rising the input end of unit; The drain electrode of the 6th PMOS PMu is connected with the drain electrode of the 5th NMOS tube NMu, and as slope rising the output terminal of unit; The source electrode of the 6th PMOS PMu is connected with the output terminal of the second current source Ibr1; The input end of the second current source Ibr1 and direct supply V
dDbe connected; The source electrode of the 5th NMOS tube NMu is connected to ground GND.
Slope decline unit comprises PMOS PMd, NMOS tube NMd and current source Ibr2.Its annexation is: the grid of the 7th PMOS PMd is connected with the grid of the 6th NMOS tube NMd, and as the input end of slope decline unit; The drain electrode of the 7th PMOS PMd is connected with the drain electrode of the 6th NMOS tube NMd, and as the output terminal of slope decline unit; The source electrode of the 7th PMOS PMd is connected with direct supply VDD; The source electrode of the 6th NMOS tube NMd is connected with the input end of the 3rd current source Ibr2, and the output terminal of the 3rd current source Ibr2 is connected to ground GND.
As shown in Figure 7 slope rises the embodiment of unit and slope decline unit, electric capacity Cu two ends original state is 0 current potential, when slope rising the input end Vin_u of unit from V
dDduring potential step to 0 current potential, current source Ibr1 begins through PMu and charges to Cu, and output end vo _ u starts to rise with ramp system, and rise time slope rising element output signal Vo_u is:
When slope rising the input end Vin_u of unit from 0 potential step to V
dDduring current potential, Cu is by NMu rapid discharge, and output end vo _ u will from V
dDpotential step to 0 current potential.
Electric capacity Cd two ends original state is V
dDcurrent potential, when the input end Vin_d of slope decline unit is from 0 potential step to V
dDduring current potential, electric capacity Cd will be discharged by NMd and Ibr2, output end vo _ d start with ramp system decline, output signal Vo_d fall time be:
As can be seen from (1), (2) formula, if the size of current source Ibr1 and Ibr2 has been determined, the capacitance size that Time Created slope rising the output signal of unit and slope decline unit can be connect by output terminal determines, can obtain required time delay thus.In figure 6, by C
1and C
2control rise time slope rising unit 311 and 312 respectively, by C
3and C
4control the fall time of slope decline unit 313 and 314 respectively.
With reference to figure 6 and Fig. 8, the first Schmidt trigger Sch1 and the second Schmidt trigger Sch2 is identical structure.Fig. 8 is the voltage transitions characteristic of described Schmidt trigger Sch1, Sch2, and the hysteresis interval of described Schmidt trigger is comparatively large, only has input end just to overturn close to when 0 current potential or VDD current potential.Namely the trigger characteristic of described Schmidt trigger Sch1, Sch2 is: rise to V at the input signal Vi_sh of Schmidt trigger from 0
dDprocess in, at Vi_sh close to V
dDcurrent potential place, the output signal Vo_sh of Schmidt trigger is from V
dDpotential step to 0 current potential; At the input signal Vi_sh of Schmidt trigger from V
dDcurrent potential drops in the process of 0 current potential, and at Vi_sh close to 0 current potential place, the output signal of Schmidt trigger is from 0 potential step to V
dDcurrent potential.
With reference to figure 5 and Fig. 6, when Start_up signal is from 0 potential step to V
dDduring current potential, undertaken anti-phase by the first phase inverter Inv1, output terminal slope rising unit 311 rises to V from 0 current potential in the mode on slope
dD, due to the trigger characteristic of the first Schmidt trigger Sch1, ensure that the output end signal that slope rises unit 311 is close to V
dDduring current potential, Sch1 just overturns.There is upset and just result in and slope rises unit 312 and output signal EN and start rising in Sch1, and causes the upset of the second phase inverter Inv2, and then slope decline unit 313 outputs signal EN_b from V
dDcurrent potential starts to decline.According to Fig. 7 and formula (1), the time delay Δ t in Fig. 5
1can be expressed as:
According to Fig. 7 and formula (1), slope rising the rise time that unit 312 outputs signal, is also Δ t Time Created slope rising enable signal EN
2for:
According to Fig. 7 and formula (2), the fall time of slope decline unit 313 output signal is also Δ t Time Created of slope decline enable signal EN_b
3for:
When described ramp signal EN_b slope drops to close to 0 current potential, the second Schmidt trigger Sch2 overturns (from 0 potential step to V
dDcurrent potential), and then cause the output signal of slope decline unit 314 to start slope decline.According to Fig. 7 and formula (2), Δ t fall time of the output signal of described slope decline unit 314
4for:
When the output signal of described slope decline unit 314 drops to close to 0 current potential, the 3rd Schmidt trigger Sch3 overturns (from 0 potential step to V
dDcurrent potential), and then cause the output signal EN_SS of the 3rd phase inverter Inv3 to overturn (from V
dDpotential step to 0 current potential).
When upset occurs described EN_SS signal, namely at t
6in the moment, the startup work of the first promoter circuit 310 completes, and the second promoter circuit 311 starts to start work.
With reference to as shown in Figure 6, the second promoter circuit 320 comprises comparer 321, two phase inverter Inv4, Inv5, three PMOS PM3, PM4, PM5, two NMOS tube NM3, NM4, current source Ibs and electric capacity C
5.
With reference to figure 4 and Fig. 6, when described EN_SS signal is V
dDduring current potential, the 3rd NMOS tube NM3 and the 4th NMOS tube NM4 is conducting state, and the output terminal Vro of the second promoter circuit 320, the in-phase end of comparer 321 are 0 current potential, due to end of oppisite phase and the reference voltage source V of comparer 321
bGbe connected, so the output signal V of comparer 321
o_
combe 0 current potential, the output potential of the 4th phase inverter Inv4 is V
dDcurrent potential, the output potential of the 5th phase inverter Inv5 is 0 current potential, and the 3rd PMOS PM3 is cut-off state.
When described EN_SS signal is from V
dDduring potential step to 0 current potential, NM3 and NM4 ends, and the first current source Ibs passes through the 5th PMOS PM5 to the 5th electric capacity C
5charging, Vro starts to rise from 0 current potential slope.
When Vro end exceeds the minimum accuracy voltage of comparer 321 than Vri end, comparer 321 is from 0 potential step to V
dDcurrent potential, and then cause the 4th phase inverter Inv4 step to 0 current potential, the 5th phase inverter Inv5 step is to V
dDcurrent potential, PM3 enters conducting state, and PM5 enters cut-off state, and current source Ibs is no longer to C5 charging, and Vro end is held coupled by PM3 with Vri, and now Vro current potential is equal with Vri current potential, is equal to V
bG.Vro rises to V from 0 current potential slope
bGrequired Time Created is Δ t
5:
Drain electrode and the source electrode of the 4th PMOS PM4 connect, and its effect is feedthrough effect and the charge injection of offsetting Inv4 and Inv5 PM3 and PM4 when overturning, and when PM3 conducting, the transition of output terminal Vro signal is more steady.The gate area of PM3 equals the gate area that 2 times of the gate area of PM4 add PM5, and namely wide the and length of PM3, PM4, PM5 should meet following formula:
W
PM3·L
PM3＝2W
PM4·L
PM4+W
PM5·L
PM5(8)
Wherein, W
pM3for the gate area of PM3, W
pM4for the gate area of PM4, W
pM5for the gate area of PM5.
In addition, the above-mentioned definition to each element and method is not limited in various concrete structures, shape or the mode mentioned in embodiment, and those of ordinary skill in the art can change simply it or replace, such as:
Slope shown in Fig. 6 and Fig. 7 rises unit and slope decline unit, can replace with other slope circuit for generating.As long as ramp-up signal and ramp-down signal can be produced.
The beneficial effect of low pressure difference linear voltage regulator of the present invention is:
(1) beneficial effect of slope start-up circuit is illustrated below in conjunction with simulation waveform, namely to the inhibiting effect of current impulse when powering on.With reference to figure 4 and embodiment illustrated in fig. 6, realistic model is 0.35um standard CMOS process storehouse, supply voltage value V
dD=3.3V, output voltage V
o=3V, pull-up resistor is R
l=40 Ω, namely load current is 75mA, and maximum load current is 100mA.Each electric capacity value is: C
1=90fF, C
2=100fF, C
3=250fF, C
4=200fF, C
5=2pF, C
o=2uF.Each current source value is all equal: Ibs=Ibr1=Ibr2=10nA.V in Fig. 9 ~ Figure 11
dDrise time is all set to 100ns.
Fig. 9 is oscillogram when not having slope start-up circuit 201, and Vref terminal voltage directly and reference voltage source V
bGbe connected, as can be seen from Figure 9, at V
dDin the process risen, I
mpwaveform will there will be the pulse current of about 1.75A.
Figure 10 is the method adopting the document [2] provided in background technology, namely the circuit waveform during startup enable signal EN and EN_b of slope is not had, the drain terminal of PM1 and NM1 now in Fig. 4 does not all access in voltage stabilizer main circuit 202, but the Vro of slope start-up circuit 201 end is still held with the Vref of operational amplifier OP1203 and is connected.As can be seen from Figure 10, at V
dDin the process risen, I
mpwaveform still there will be the pulse current of about 1.75A.
Figure 11 is oscillogram when adopting slope start-up circuit 201.Can find out, in whole start-up course, all not occur peak current, circuit of the present invention can realize the inhibiting effect to peak current in the zooming situation of supply voltage.
(2) simultaneously, the present invention comprises slope start-up circuit 201 and realizes on sheet completely, realizes the soft start of LDO without the need to any piece element.Save cost and the volume of electronic product.Meanwhile, whole circuit only has comparer current sinking when static state, and the precision of comparer and rate request are not high, and the electric current of consumption can within 1uA, and therefore, the present invention also has the feature of low-power consumption.
In sum, these are only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. the low pressure difference linear voltage regulator with slope start-up circuit, is characterized in that: this voltage stabilizer comprises start-up circuit (201) and voltage stabilizer main circuit (202); Wherein
Start-up circuit (201), on the one hand for generation of two-way slope enable signal EN and EN_b, as the input signal of voltage stabilizer main circuit Enable Pin, be used for the input of output voltage signal Vro as voltage stabilizer main circuit on the other hand, described voltage signal Vro slope rises, is finally stabilized in a magnitude of voltage;
Voltage stabilizer main circuit (202), under the control of two-way enable signal EN and EN_b, for carrying out scale amplifying to described voltage signal Vro, exports a burning voltage Vo;
Described start-up circuit (201) comprises the first promoter circuit (310) and the second promoter circuit (320):
First promoter circuit (310), for generation of two-way slope enable signal EN and EN_b; Described first promoter circuit (310) comprises three phase inverter (Inv1, Inv2, Inv3), three Schmidt triggers (Sch1, Sch2, Sch3), four electric capacity (C1, C2, C3, C4), two slopes rise unit (311,312) and two slope decline unit (313,314);
The inside annexation of the first promoter circuit (310) is: the input end of the first phase inverter (Inv1) is as the Enable Pin Start_up of start-up circuit (201), and its output terminal is connected with the input end the first slope rising unit (311); The output terminal first slope rising unit (311) is connected with the input end of the first Schmidt trigger (Sch1) with one end of the first electric capacity (C1) respectively; The output terminal of the first Schmidt trigger (Sch1) is connected with the input end of the second phase inverter (Inv2) with the input end the second slope rising unit (312) respectively; The output terminal second slope rising unit (312) is connected with one end of the second electric capacity (C2), and as the ramp-up signal output terminal EN in the enable signal of described two-way slope; The output terminal of the second phase inverter (Inv2) is connected with the input end of the first slope decline unit (313), the output terminal of the first slope decline unit (313) is connected with the input end of the second Schmidt trigger (Sch2) with one end of the 3rd electric capacity (C3) respectively, and as the ramp-down signal output terminal EN_b in the enable signal of described two-way slope; The output terminal of the second Schmidt trigger (Sch2) is connected with the input end of the second slope decline unit (314), and the output terminal of the second slope decline unit (314) is connected with the input end of the 3rd Schmidt trigger (Sch3) with one end of the 4th electric capacity (C4) respectively; The output terminal of the 3rd Schmidt trigger (Sch3) is connected with the input end of the 3rd phase inverter (Inv3); The other end of the first electric capacity (C1) and the second electric capacity (C2) is all connected to ground GND, and the other end of the 3rd electric capacity (C3) and the 4th electric capacity (C4) is all connected to direct supply VDD;
Second promoter circuit (320), rises to a burning voltage from 0 current potential in the mode on slope for making output voltage Vro; Second promoter circuit (320) comprises comparer (321), two phase inverters (Inv4, Inv5), three PMOS (PM3, PM4, PM5), two NMOS tube (NM3, NM4), the first current source (Ibs) and the 5th electric capacity (C5);
The inside annexation of the second promoter circuit (320) is: the end of oppisite phase of comparer (321) is connected with the source electrode of the 3rd PMOS (PM3), and as an input end Vri of start-up circuit (201); The in-phase end of comparer (321) is connected with one end of the drain electrode of the 3rd PMOS (PM3), the source electrode of the 4th PMOS (PM4) and the drain electrode of drain electrode, the 5th PMOS (PM5), the drain electrode of the 4th NMOS tube (NM4) and the 5th electric capacity (C5) respectively; The output terminal VO_Com of comparer (321) is connected with the drain electrode of the 3rd NMOS tube (NM3) with the input end of the 4th phase inverter (Inv4) respectively; The output terminal of the 4th phase inverter (Inv4) is connected with the grid of the 3rd PMOS (PM3) with the input end of the 5th phase inverter (Inv5) respectively; The output terminal of the 5th phase inverter (Inv5) is connected with the grid of the 5th PMOS (PM5) with the grid of the 4th PMOS (PM4) respectively; The source electrode of the 5th PMOS (PM5) is connected with the output terminal of the first current source (Ibs); The input end of the first current source (Ibs) is connected with direct supply VDD; The other end of the source electrode of the 3rd NMOS tube (NM3), the source electrode of the 4th NMOS tube (NM4) and the 5th electric capacity (C5) is all connected to ground GND;
The output terminal EN_SS of the 3rd phase inverter (Inv3) is connected with the grid of the 4th NMOS tube (NM4) with the grid of the 3rd NMOS tube (NM3) respectively.
2. low pressure difference linear voltage regulator according to claim 1, it is characterized in that, described voltage stabilizer main circuit (202) comprises the first PMOS (PM1), the first NMOS tube (NM1), error amplifier OP1 (203), impact damper (204), power tube (Mp), the feedback unit, the pull-up resistor (R that are made up of the first resistance (R1) and the second resistance (R2)
l) and output capacitance (Co); Wherein
The grid of the first PMOS (PM1) is connected with the output terminal EN of described start-up circuit (201), the drain electrode of the first PMOS (PM1) is connected with the grid of power tube (Mp), and the source electrode of the first PMOS (PM1) is connected with direct supply VDD; The grid of the first NMOS tube (NM1) is connected with the output terminal EN_b of described start-up circuit (201), the drain electrode of the first NMOS tube (NM1) and the output terminal V of error amplifier (OP1)
o1be connected, the source electrode of the first NMOS tube (NM1) is connected with ground GND;
Impact damper (204) is made up of the second PMOS (PM2) and the second NMOS tube (NM2); The grid of the second PMOS (PM2) is connected with its drain electrode, and is connected with the drain electrode of the second NMOS tube (NM2) with the grid of power tube (Mp) respectively; The source electrode of the second PMOS (PM2) is connected with direct supply VDD; The grid of the second NMOS tube (NM2) and the output terminal V of error amplifier OP1 (201)
o1be connected, the source electrode of the second NMOS tube (NM2) is connected with ground GND;
The in-phase end V of error amplifier OP1 (201)
refbe connected with the output terminal Vro of start-up circuit (201), the end of oppisite phase V of error amplifier OP1 (201)
fbin access feedback unit, the first resistance (R1) is connected with the second resistance (R2) part;
The source electrode of power tube (Mp) is connected with direct supply VDD; The drain electrode of power tube (Mp) respectively with one end of the first resistance (R1), one end of output capacitance (Co) and pull-up resistor (R
l) one end be connected, pull-up resistor (R
l) the other end and the other end of output capacitance (Co) be connected to GND; The two ends of the second resistance (R2) are connected with GND with the other end of the first resistance (R1) respectively; The drain electrode of power tube (Mp) is as the output end vo of voltage stabilizer main circuit (202).
3. low pressure difference linear voltage regulator according to claim 1, is characterized in that, described first slope rises on unit (311) and the second slope and rises unit (312) for same circuits structure,
Slope rises unit and comprise the 6th PMOS (PMu), the 5th NMOS tube (NMu) and the second current source (Ibr1); Its annexation is: the grid of the 6th PMOS (PMu) is connected with the grid of the 5th NMOS tube (NMu), and as slope rising the input end of unit; The drain electrode of the 6th PMOS (PMu) is connected with the drain electrode of the 5th NMOS tube (NMu), and as slope rising the output terminal of unit; The source electrode of the 6th PMOS (PMu) is connected with the output terminal of the second current source (Ibr1); The input end of the second current source (Ibr1) is connected with direct supply VDD; The source electrode of the 5th NMOS tube (NMu) is connected to ground GND.
4. low pressure difference linear voltage regulator according to claim 1, is characterized in that, described first slope decline unit (313) and the second slope decline unit (314) are same circuits structure;
Slope decline unit comprises the 7th PMOS (PMd), the 6th NMOS tube (NMd) and the 3rd current source (Ibr2); Its annexation is: the grid of the 7th PMOS (PMd) is connected with the grid of the 6th NMOS tube (NMd), and as the input end of slope decline unit; The drain electrode of the 7th PMOS (PMd) is connected with the drain electrode of the 6th NMOS tube (NMd), and as the output terminal of slope decline unit; The source electrode of the 7th PMOS (PMd) is connected with direct supply VDD; The source electrode of the 6th NMOS tube (NMd) is connected with the input end of the 3rd current source (Ibr2), and the output terminal of the 3rd current source (Ibr2) is connected to ground GND.
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| US10444779B2 (en) * | 2016-11-03 | 2019-10-15 | Mediatek Inc. | Low dropout voltage regulator for generating an output regulated voltage |
| CN106571739A (en) * | 2016-11-11 | 2017-04-19 | 昆山龙腾光电有限公司 | Soft starting circuit and power supply device |
| CN107272808B (en) * | 2017-08-11 | 2019-01-29 | 泉州市天龙电子科技有限公司 | A kind of LDO circuit applied to integrated chip |
| CN108258895B (en) * | 2018-02-05 | 2020-11-17 | 上海艾为电子技术股份有限公司 | Soft start circuit and power supply system |
| CN108919872B (en) * | 2018-06-25 | 2020-06-09 | 北京集创北方科技股份有限公司 | Low dropout linear regulator and voltage stabilizing method thereof |
| CN111949060A (en) * | 2020-08-14 | 2020-11-17 | 电子科技大学 | Slow starting circuit |
| CN112363561B (en) * | 2020-11-05 | 2022-11-15 | 上海艾为电子技术股份有限公司 | Linear voltage regulator and soft start method thereof |
| CN113467566B (en) * | 2021-08-06 | 2022-10-11 | 上海艾为电子技术股份有限公司 | Ramp voltage generating circuit, chip and electronic equipment |
| CN117311433A (en) * | 2023-11-07 | 2023-12-29 | 深圳奥简科技有限公司 | Soft-start low-dropout linear voltage stabilizing circuit |
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