CN104157653B - A kind of EEPROM memory cell - Google Patents
A kind of EEPROM memory cell Download PDFInfo
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- CN104157653B CN104157653B CN201410394627.XA CN201410394627A CN104157653B CN 104157653 B CN104157653 B CN 104157653B CN 201410394627 A CN201410394627 A CN 201410394627A CN 104157653 B CN104157653 B CN 104157653B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 53
- 229920005591 polysilicon Polymers 0.000 claims abstract description 53
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 230000014759 maintenance of location Effects 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 238000003860 storage Methods 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 3
- 229910052760 oxygen Inorganic materials 0.000 claims 3
- 239000001301 oxygen Substances 0.000 claims 3
- 239000013078 crystal Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005674 electromagnetic induction Effects 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
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- Non-Volatile Memory (AREA)
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- Read Only Memory (AREA)
Abstract
The invention discloses a kind of EEPROM memory cell structure, belong to technical field of manufacturing semiconductors, the EEPROM memory cell structure includes：Semiconductor base and the mos capacitance formed on a semiconductor substrate, polysilicon capacitance, MOS selecting pipes, MOS read pipe；The capacitance of the polysilicon capacitance is more than the capacitance of the mos capacitance.The EEPROM memory cell operating voltage of the structure is low, therefore can improve its data retention, with high reliability, durability and Information Security.
Description
Technical field
The present invention relates to a kind of semiconductor storage unit, more particularly to a kind of eeprom memory part.
Background technology
RFID tag be widely used at present freight supply management, package track identification, logistic storage, Mobile business,
In terms of aviation and medical services.Passive RFID tag chip includes radio frequency, wherein logic and memory module, memory module
Information storage space is provided for product identification, transmission, directoryof and user profile etc..In the prior art, EEPROM is reading to grasp
Compared to ferroelectric RAM (Ferroelectric Random Access Memory, FeRAM) with competing in terms of work
Advantage is striven, because its read operation need not re-write after not destroying information, reading.In addition, its compatibility with CMOS technology
Also superior to the latter, it is easy to large-scale industrial production, beneficial to reducing cost.
Passive RFID tag chip unpowered power supply, electromagnetic induction when it with reader by acting on extremely has to couple
The energy of limit.Existing EEPROM power consumptions are larger, because its grid structure is by polysilicon control grid, coupling oxide layer, polycrystalline
The vertical stack structure of silicon floating gate and tunnel oxide composition, the problem of structure is brought be：First, EEPROM operating voltage is made
It is higher, it is unfavorable for reducing the work field strength of chip, increase reading/writing distance；2nd, EEPROM is carried as the information of RFID label chip
, because the capacitance of its existing stack architecture is small, sometimes at work, during with operating distance and angle change, there is centre in body
The possibility of power down, can cause information to lose or mistake write-in.
The content of the invention
The present invention is directed to the defect that above-mentioned technology is present, and technical problem to be solved is：A kind of EEPROM storages are provided
Unit, the EEPROM memory cell operating voltage of the structure is low, therefore can improve its data retention, with highly reliable
Property, durability and Information Security.
To solve the above problems, a kind of EEPROM memory cell that the present invention is provided, including：Semiconductor base and partly leading
Mos capacitance, polysilicon capacitance, MOS selecting pipes, the MOS formed in body substrate reads pipe；The capacitance of the polysilicon capacitance is big
In the capacitance of the mos capacitance.
Described EEPROM memory cell, its semiconductor base can be the epitaxial silicon chip of p-type doping；The mos capacitance
It is PMOS electric capacity 110；The MOS selecting pipes are NMOS selecting pipes 130；It is that NMOS reads pipe 140 that the MOS, which reads pipe,.
Described EEPROM memory cell, the PMOS electric capacity 110 includes：The ion on the epitaxial silicon chip 100 that p-type is adulterated
Injection forms n traps 112, the 102a of gate oxide one, the 102b of gate oxide two, the floating boom 122a for being placed in the 102a of gate oxide one, source
The 114a of drain region one, the 114b of source-drain area two, the 116a of mos capacitance contact hole one being placed on the 114a of source-drain area one and it is placed in source-drain area
Mos capacitance contact hole two 116b, the floating boom 122a on two 114b are as the Top electrode of PMOS electric capacity, and the mos capacitance connects
The 116a of contact hole one and the 116b short circuits of mos capacitance contact hole two are used to connect DL, the 114a of source-drain area one and source-drain area two 114b
It is used as the bottom electrode of PMOS electric capacity 110；
The NMOS selecting pipes 130 include：The epitaxial silicon chip 100 of p-type doping, the 102b of gate oxide two, it is placed in gate oxidation
One 102a of layer floating boom 122a, drain region 134a, the NMOS selections for sharing source-drain area 134b, source region 134c, being placed on the 134a of drain region
Pipe contact hole 136, the NMOS selecting pipes contact hole 136 connection BL, the shared source-drain area 134b is both NMOS selecting pipes 130
Source region, be again NMOS read pipe 140 drain region.
The NMOS, which reads pipe 140, to be included：The epitaxial silicon chip 100 of p-type doping, the 102b of gate oxide two, it is placed in gate oxidation
First layer polysilicon gate 122b on two 102b of layer, share source-drain area 134b, source region 134c and for being placed on source region 134c
NMOS reads pipe contact hole 146, and the NMOS reads pipe contact hole 146 and connects ground wire；The shared source-drain area 134b is both
The source region of NMOS selecting pipes 130, is the drain region that NMOS reads pipe 140 again；Polysilicon gate 122b reads the grid of pipe 140 as NMOS
Pole is connected with RWL.
The polysilicon capacitance 120 includes：Floating boom 122a, polysilicon gate 124, dielectric layer 123, it is placed in polysilicon gate 124
On polysilicon gate contact hole 126, the floating boom 122a is used as the bottom crown of polysilicon capacitance 120, and the polysilicon gate 124 uses
Make the top crown of polysilicon capacitance 120, the polysilicon gate 124 is connected by polysilicon gate contact hole 126 placed on it
WWL, the dielectric layer 123 is used as the medium between the upper and lower pole plate of polysilicon capacitance 120.Described EEPROM memory cell,
The capacitance of the polysilicon capacitance 120 is 10~20 times of the capacitance of PMOS electric capacity 110, polysilicon capacitance 120 preferably
Capacitance be 10 times of capacitance of PMOS electric capacity 110.The capacitance of current prior art EEPROM polysilicon capacitance
With the capacitance sizableness of PMOS electric capacity, both ratios are about 1: 1, because both insulating dielectric materials, area and thickness
All same so that device operation voltage Vpp=2V1；Using technical solution of the present invention, the area of polysilicon capacitance can be increased
10 times, Vpp=1.1V1 can be made, operating voltage is effectively reduced.
EEPROM memory cell of the present invention can be used in passive RFID tag chip.
Beneficial effects of the present invention：Significantly reduced, carried using the eeprom memory operating voltage of technical solution of the present invention
Its high data retention, with high reliability, durability and Information Security.For example, the typical case of technical solution of the present invention
11~12 volts of EEPROM operating voltages, the working life of 15 years, compared to 20 volts more of the prior art, the working life of 10 years,
Its low-voltage, low-power consumption, reliability, durability and data retention are significantly improved.
Brief description of the drawings
Fig. 1 is the plan view from above of the EEPROM memory cell described in the embodiment of the present invention；
Fig. 2 is cross-sectional view of the memory cell along A-A directions shown in Fig. 1；
Fig. 3 is cross-sectional view of the memory cell along B-B directions shown in Fig. 1；
Fig. 4 is cross-sectional view of the memory cell along C-C directions shown in Fig. 1.
In figure, the epitaxial silicon chip of 100-P types doping, 102a- gate oxides one, 102b- gate oxides two, 110-PMOS electricity
Hold, 112-n traps, 114a- source-drain areas one, 114b- source-drain areas two, 116a-MOS capacitance contacts hole one, 116b-MOS capacitance contacts
Hole two, 120- polysilicon capacitances, 122a- floating booms, 123- dielectric layers, 124- polysilicon gates, 126- polysilicon capacitance contact holes,
130-NMOS selecting pipes, 134a- drain regions, 134b- shares source-drain area, 134c- source regions, 136-NMOS selecting pipe contact holes, 140-
NMOS reads pipe, and 146-NMOS reads pipe contact hole.
Embodiment
With reference to the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Ground is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Based on this
Embodiment in invention, the every other reality that those of ordinary skill in the art are obtained under the premise of creative work is not made
Example is applied, protection scope of the present invention is belonged to.
Embodiment one
A kind of EEPROM memory cell as shown in Figure 1, the semiconductor base is the epitaxial silicon chip 100 of p-type doping,
PMOS electric capacity 110, polysilicon capacitance 120, NMOS selecting pipes 130, the NMOS formed on semiconductor base reads pipe 140；It is described
PMOS electric capacity 110 includes：Ion implanting formation n traps 112, the 102a of gate oxide one, grid on the epitaxial silicon chip 100 that p-type is adulterated
The 102b of oxide layer two, the floating boom 122a for being placed in the 102a of gate oxide one, the 114a of source-drain area one, the 114b of source-drain area two, are placed in source and drain
The 116a of mos capacitance contact hole one and the 116b of mos capacitance contact hole two being placed on the 114b of source-drain area two, institute on the 114a of area one
Floating boom 122a is stated as the Top electrode of PMOS electric capacity, the 116a of mos capacitance contact hole one and the 116b of mos capacitance contact hole two are short
Connect for connecting DL, the 114a of source-drain area one and the 114b of source-drain area two as PMOS electric capacity 110 bottom electrode.
The NMOS selecting pipes 130 include：The epitaxial silicon chip 100 of p-type doping, the 102b of gate oxide two, it is placed in gate oxidation
One 102a of layer floating boom 122a, drain region 134a, the NMOS selections for sharing source-drain area 134b, source region 134c, being placed on the 134a of drain region
Pipe contact hole 136, the NMOS selecting pipes contact hole 136 connection BL, the shared source-drain area 134b is both NMOS selecting pipes 130
Source region, be again NMOS read pipe 140 drain region.
The NMOS, which reads pipe 140, to be included：The epitaxial silicon chip 100 of p-type doping, the 102b of gate oxide two, it is placed in gate oxidation
First layer polysilicon gate 122b on two 102b of layer, share source-drain area 134b, source region 134c and for being placed on source region 134c
NMOS reads pipe contact hole 146, and the NMOS reads pipe contact hole 146 and connects ground wire；The shared source-drain area 134b is both
The source region of NMOS selecting pipes 130, is the drain region that NMOS reads pipe 140 again；Polysilicon gate 122b reads the grid of pipe 140 as NMOS
Pole is connected with RWL.
The polysilicon capacitance 120 includes：Floating boom 122a, polysilicon gate 124, dielectric layer 123, it is placed in polysilicon gate 124
On polysilicon gate contact hole 126, the floating boom 122a is used as the bottom crown of polysilicon capacitance 120, and the polysilicon gate 124 uses
Make the top crown of polysilicon capacitance 120, the polysilicon gate 124 is connected by polysilicon gate contact hole 126 placed on it
WWL, the dielectric layer 123 is used as the medium between the upper and lower pole plate of polysilicon capacitance 120.
Described EEPROM memory cell, the capacitance of the polysilicon capacitance 120 is the capacitance of PMOS electric capacity 110
10 times.
Using the EEPROM of technical solution of the present invention 11~12 volts of operating voltage, the working life of 15 years, compared to more existing
There are 20 volts, the working life of 10 years in technology, its low-voltage, low-power consumption, reliability, durability and data retention have
It is obvious to improve.
Claims (4)
1. a kind of EEPROM memory cell, including：Semiconductor base and the mos capacitance formed on a semiconductor substrate, polysilicon
Electric capacity, MOS selecting pipes, MOS read pipe；Characterized in that, the capacitance of the polysilicon capacitance is more than the electricity of the mos capacitance
Capacitance, the semiconductor base is the epitaxial silicon chip of p-type doping, and the mos capacitance is PMOS electric capacity (110), the MOS selections
Pipe is NMOS selecting pipes (130), and it is that NMOS reads pipe (140) that the MOS, which reads pipe,；
The PMOS electric capacity (110) includes：Ion implanting formation n traps (112), grid oxygen on the epitaxial silicon chip (100) that p-type is adulterated
Change layer one (102a), gate oxide two (102b), floating boom (122a), the source-drain area one for being placed in gate oxide one (102a)
(114a), source-drain area two (114b), the mos capacitance contact hole one (116a) being placed on source-drain area one (114a) and it is placed in source-drain area
Mos capacitance contact hole two (116b) on two (114b), the floating boom (122a) is used as the Top electrode of PMOS electric capacity (110), institute
Stating mos capacitance contact hole one (116a) and mos capacitance contact hole two (116b) short circuit is used to connect DL, the source-drain area one
(114a) and source-drain area two (114b) as PMOS electric capacity (110) bottom electrode；
The NMOS selecting pipes (130) include：The epitaxial silicon chip (100) of p-type doping, gate oxide two (102b), it is placed in grid oxygen
Change layer one (102a) floating boom (122a), drain region (134a), share source-drain area (134b), source region (134c), be placed in drain region
NMOS selecting pipes contact hole (136), the NMOS selecting pipes contact hole (136) connection BL, the shared source and drain on (134a)
Area (134b) is both the source region of NMOS selecting pipes (130), is the drain region that NMOS reads pipe (140) again；
The NMOS, which reads pipe (140), to be included：The epitaxial silicon chip (100) of p-type doping, gate oxide two (102b), it is placed in grid oxygen
Change the first layer polysilicon gate (122b) on layer two (102b), share source-drain area (134b), source region (134c) and for being placed in source
NMOS in area (134c) reads pipe contact hole (146), and the NMOS reads pipe contact hole (146) connection ground wire；It is described to share
Source-drain area (134b) is both the source region of NMOS selecting pipes (130), is the drain region that NMOS reads pipe (140) again；Polysilicon gate
(122b) is connected as the NMOS grids for reading pipe (140) with RWL；
The polysilicon capacitance (120) includes：Floating boom (122a), polysilicon gate (124), dielectric layer (123), it is placed in polysilicon gate
(124) the polysilicon gate contact hole (126) on, the floating boom (122a) is used as the bottom crown of polysilicon capacitance (120), described many
Crystal silicon grid (124) are used as the top crown of polysilicon capacitance (120), and the polysilicon gate (124) passes through polysilicon placed on it
Grid contact hole (126) connects WWL, and the dielectric layer (123) is used as the medium between polysilicon capacitance (120) upper and lower pole plate.
2. a kind of EEPROM memory cell as claimed in claim 1, it is characterised in that the electricity of the polysilicon capacitance (120)
Capacitance is 10~20 times of the capacitance of PMOS electric capacity (110).
3. a kind of EEPROM memory cell as claimed in claim 2, it is characterised in that the electricity of the polysilicon capacitance (120)
Capacitance is 10 times of the capacitance of PMOS electric capacity (110).
4. the EEPROM memory cell as described in claim 1-3 any claims, it is characterised in that the EEPROM storages
Unit can be used in passive RFID tag chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410394627.XA CN104157653B (en) | 2014-08-02 | 2014-08-02 | A kind of EEPROM memory cell |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410394627.XA CN104157653B (en) | 2014-08-02 | 2014-08-02 | A kind of EEPROM memory cell |
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| CN104157653A CN104157653A (en) | 2014-11-19 |
| CN104157653B true CN104157653B (en) | 2017-08-01 |
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| CN201410394627.XA Active CN104157653B (en) | 2014-08-02 | 2014-08-02 | A kind of EEPROM memory cell |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6275424B1 (en) * | 1999-07-14 | 2001-08-14 | Advanced Micro Devices, Inc. | Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device |
| KR100731086B1 (en) * | 2006-09-04 | 2007-06-22 | 동부일렉트로닉스 주식회사 | Method for measuring floating gate capacitance in mosfet |
| CN101377955A (en) * | 2007-08-28 | 2009-03-04 | 三星电子株式会社 | Electrically erasable programmable read-only memory (EEPROM) cell and methods for forming and reading the same |
-
2014
- 2014-08-02 CN CN201410394627.XA patent/CN104157653B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6275424B1 (en) * | 1999-07-14 | 2001-08-14 | Advanced Micro Devices, Inc. | Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device |
| KR100731086B1 (en) * | 2006-09-04 | 2007-06-22 | 동부일렉트로닉스 주식회사 | Method for measuring floating gate capacitance in mosfet |
| CN101377955A (en) * | 2007-08-28 | 2009-03-04 | 三星电子株式会社 | Electrically erasable programmable read-only memory (EEPROM) cell and methods for forming and reading the same |
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| Publication number | Publication date |
|---|---|
| CN104157653A (en) | 2014-11-19 |
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Effective date of registration: 20200710 Address after: Room 516, building A3, innovation industrial park, No. 800, Wangjiang West Road, hi tech Zone, Hefei City, Anhui Province 230000 Patentee after: Hefei Sijing Electronic Co.,Ltd. Address before: Room 401-07-1 No. 214000 of Jiangsu Province, the New District of Wuxi City Xinda road building 33-1IC design Patentee before: WUXI NAVOTA ELECTRONICS Co.,Ltd. |