CN107316657A - Memory cell - Google Patents
Memory cell Download PDFInfo
- Publication number
- CN107316657A CN107316657A CN201610263582.1A CN201610263582A CN107316657A CN 107316657 A CN107316657 A CN 107316657A CN 201610263582 A CN201610263582 A CN 201610263582A CN 107316657 A CN107316657 A CN 107316657A
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- CN
- China
- Prior art keywords
- memory cell
- programming
- source region
- drain region
- polysilicon
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
Abstract
The present invention is provided in memory cell, including：Semiconductor substrate；Drain region, bonding pad and the source region arranged in the first direction successively in Semiconductor substrate, the selection grid in Semiconductor substrate between drain region and bonding pad, the floating boom in Semiconductor substrate between bonding pad and source region, the length that floating boom extends in a second direction is more than selection grid；The side away from selection grid is formed with first end and the second end to floating boom in a second direction, control gate is formed with first end, programming source region and programming drain region are respectively formed with the Semiconductor substrate at the second end both sides, the second end, programming source region and programming drain region form programming transistor.In the present invention, program regions and erasing region are separated, operation is programmed to programming transistor; operating voltage needed on control gate is smaller, can preferably protect memory cell, reduces the power consumption of memory cell; so as to improve the performance of memory cell, extend the service life of memory cell.
Description
Technical field
The present invention relates to memory cell technologies field, more particularly to a kind of memory cell.
Background technology
Memory unit is provided in computer or other electricity usually as inner member, semiconductor integrated circuit
In sub-device.Memory cell is divided into many different types, such as Random Access Storage Unit (RAM), only
Memory cell (ROM), DRAM cell (DRAM), synchronous dynamic random-access is read to deposit
Storage unit (SDRAM) and non-volatile flash memory cell.Flash memory cell device has evolved into use
In the common source of the non-volatile memory cells of various electronic applications.Flash memory cell device is usually used
Allow the single transistor memory cell unit of high density of memory cells, high reliability and low power consumption.Quick flashing
The common use of memory cell includes personal computer, personal digital assistant (PDA), digital camera and honeycomb
Formula phone.
Memory cell of the prior art includes source electrode, drain electrode, selection grid, floating boom and on floating boom
Control gate.When being operated to memory cell, some storage that selection grid is used to choose in memory cell is single
Member, and add higher operating voltage on the control gate, electronics (that is to say data) is stored in floating boom.
However, make it that the power consumption of memory cell is big compared with high operating voltage on control gate, and therefore, the behaviour on control gate
The height for making voltage determines the power consumption of memory cell.
The content of the invention
It is an object of the present invention to provide a kind of memory cell, solves to need to add on control gate in the prior art
Higher operating voltage and influence the technical problem of power consumption.
In order to solve the above technical problems, the present invention provides a kind of memory cell, including：Semiconductor substrate；Position
Drain region, bonding pad and the source region arranged in the first direction successively in the Semiconductor substrate, positioned at the leakage
The selection grid in the Semiconductor substrate between area and the bonding pad, positioned at the bonding pad and the source
The floating boom in the Semiconductor substrate between area, the length that the floating boom extends in a second direction is more than described
Selection grid；Side of the floating boom in this second direction away from the selection grid is formed with first end and
It is formed with two ends, the first end in control gate, the Semiconductor substrate of second end both sides respectively
Programming source region and programming drain region are formed with, second end, the programming source region and the programming drain region are formed
Programming transistor.
Optionally, the selection grid is formed with the floating boom by one first polysilicon.
Optionally, the control gate is formed by one second polysilicon.
Optionally, second polysilicon also covers the drain region, the source region and the bonding pad.
Optionally, the source region, the bonding pad and the drain region are p-type doping.
Optionally, first through hole is formed with second polysilicon for covering the drain region, the source is covered
The second through hole is formed with second polysilicon in area.
Optionally, the source region and the programming drain region of programming is n-type doping, and the programming transistor is
Nmos pass transistor.
Optionally, second polysilicon also covers programming source region and the programming drain region, passes through described second
The programming source region is connected by polysilicon with the programming drain region.
Optionally, the institute on second polysilicon of the programming source region or covering programming drain region is covered
State and be formed with third through-hole on the second polysilicon.
Optionally, it is formed with the selection grid on fourth hole, the control gate and is formed with fifth hole,
The fifth hole is located on the control gate by the first end
Optionally, the first direction and the second direction are vertical.
Optionally, during programming operation, add on the control gate and add on 9V~14V voltage, second end
0V voltage.
Optionally, during erasing operation, add on the control gate in 0V voltage, the source region plus 9V~14V
Voltage.
Compared with prior art, the memory cell that the present invention is provided includes a programming transistor, and storage is single
The program regions of member and erasable region are separated, and are programmed operation in the programming transistor to memory cell, are reached
To identical program window, the operating voltage needed on control gate is smaller, can reduce the power consumption of memory cell,
Memory cell can be preferably protected, so as to improve the performance of memory cell, extends the use longevity of memory cell
Life.
Brief description of the drawings
Fig. 1 be one embodiment of the invention in memory cell schematic top plan view；
Fig. 2 be one embodiment of the invention in memory cell diagrammatic cross-section；
Fig. 3 be one embodiment of the invention in programming transistor diagrammatic cross-section；
Fig. 4 is the threshold voltage of memory cell in one embodiment of the invention；
The threshold voltage schematic diagram that Fig. 5 repeatedly circulates for memory cell in one embodiment of the invention.
Embodiment
The memory cell of the present invention is described in more detail below in conjunction with schematic diagram, which show this
The preferred embodiment of invention, it should be appreciated that those skilled in the art can change invention described herein, and
Still the advantageous effects of the present invention are realized.Therefore, description below is appreciated that for people in the art
Member's is widely known, and is not intended as limitation of the present invention.
The present invention core concept be there is provided memory cell include：Semiconductor substrate；Positioned at described half
Drain region, bonding pad and the source region arranged in the first direction successively in conductor substrate, positioned at the drain region and described
The selection grid in the Semiconductor substrate between bonding pad, between the bonding pad and the source region
Floating boom in the Semiconductor substrate, the length that the floating boom extends in a second direction is more than the selection grid；
Side of the floating boom in this second direction away from the selection grid is formed with first end and the second end, institute
State and control gate is formed with first end, volume is respectively formed with the Semiconductor substrate of second end both sides
Cheng Yuanqu and programming drain region, second end, the programming source region and the programming drain region form programming crystal
Pipe.In the present invention, memory cell has separated program regions and erasing region, and programming transistor is programmed
Operation, the operating voltage needed for reaching on identical program window, control gate is smaller, can preferably protect
Memory cell, reduces the power consumption of memory cell, so as to improve the performance of memory cell, adds memory cell
Service life.
The memory cell of the present invention is described in detail below in conjunction with accompanying drawing, Fig. 1 bows for memory cell
View, Fig. 2 is the cross-sectional view along AA ' directions in Fig. 1, and Fig. 3 is along BB ' directions in Fig. 1
Cross-sectional view.
With reference to Fig. 1 and Fig. 2, memory cell includes：Semiconductor substrate 100；(X side in the first direction successively
To) arrangement be located at the Semiconductor substrate 100 in drain region D, bonding pad 160 and source region S, positioned at institute
The selection grid SG in the Semiconductor substrate 100 between drain region D and the bonding pad 160 is stated, positioned at institute
State floating boom FG in the Semiconductor substrate 100 between bonding pad 160 and the source region S (in Fig. 1 not
Show).In the present embodiment, the selection grid SG and floating boom FG is by the shape of one first polysilicon 130
Into, also, form extension of the first polysilicon 130 of the floating boom FG in second direction (Y-direction)
First polysilicon 130 development length in second direction (Y-direction) of the length than forming the selection grid SG
Short, i.e., the described floating boom FG length that (Y-direction) extends in a second direction is more than the selection grid SG, its
In, the first direction (X-direction) and the second direction (Y-direction) are vertical.In addition, described floating
Grid FG sides away from the selection grid SG in the second direction (Y-direction) are formed with first end 131
With the second end 132, control gate CG is formed with the first end 131, in the present embodiment, the control
Grid CG is formed by one second polysilicon 140.It is understood that selection grid SG and Semiconductor substrate 100
Between, be each formed between floating boom FG and Semiconductor substrate 100 and between floating boom FG and control gate CG
One dielectric layer (not shown in figure 1) is as gate dielectric layer, and selection grid SG is used to operate memory cell
Apply operating voltage on some memory cell in Shi Xuanzhong memory cell, control gate CG, so that by data
It is stored in floating boom FG.
In the present embodiment, the source region S, the bonding pad 160 and the drain region D are p-type doping,
The source region S, the bonding pad 160 and the drain region D-shaped into one first active area (NW) 110,
And the first active area 110 progress ion implanting is formed respectively.It should be noted that second polysilicon
140 also cover the drain region D, the source region S and the bonding pad 160, are easy to follow-up by the drain region
D, the source region S and the bonding pad 160 are drawn, so as to reduce the area of memory cell.
With reference to shown in Fig. 1 and Fig. 3, shape is distinguished in the Semiconductor substrate 100 of the both sides of the second end 132
Source region S ' and programming drain region D ', second end 132, the programming source region S ' and the programming are programmed into having
Drain region D ' formation programming transistors 170.Further, in the present embodiment, the programming source region S ' and
The programming drain region D ' is n-type doping, and the programming source region S ' and the programming drain region D ' are respectively formed one
In second active area (p-well) 120, the programming transistor 170 is nmos pass transistor.The present embodiment
In, second polysilicon 140 also the second active area 120 described in covering part, the programming source region S ' and
The programming drain region D ', is easy to follow-up by the programming source region S ' and the programming drain region D ' and described second
Active area 120 is drawn, so as to reduce the area of memory cell.In addition, more than the second of covering programming source region S '
The second of crystal silicon 140, covering programming drain region D ' the second active area 120 of the second polysilicon 140 and covering
Polysilicon 140 is connected, i.e., leaked the programming source region S ', the programming by second polysilicon 140
Area D ' and second active area 120 are connected so that the source electrode of the programming transistor 170 of formation, drain electrode
It is connected with substrate, so that follow-up only need to form an extraction electrode and can draw programming transistor,
Reduce the area of memory cell.
Shown in Fig. 1, first is formed on the second polysilicon 140 for covering the drain region D logical
Hole 151, the second through hole 152 is formed on the second polysilicon 140 for covering the source region S, described in covering
Program on the second polysilicon of source region or cover on second polysilicon in the programming drain region or covering part second
Formed on second polysilicon of active area 120 on third through-hole 153, the selection grid SG and form fourth hole
Fifth hole 155 is formed on 154, the control gate CG.First through hole 151, the second through hole the 152, the 3rd
Through hole 153, fourth hole 154 and fifth hole 155 are respectively used to drain region D, source region S, programming is brilliant
Body pipe 170, selection grid SG and control gate CG are drawn.
Control gate CG and threshold voltage in memory cell operating process are given with reference to shown in Fig. 4, in Fig. 4
Relation, the memory cell for the prior art that curve a is represented, the memory cell of the invention that curve b is represented.
Correlation curve a and curve b is understood, when being programmed operation to memory cell of the invention, the control gate
On upper plus 9V~14V voltage, the programming transistor plus 0V voltage, memory cell of the invention with it is existing
When the memory cell for having technology reaches identical threshold voltage, the program voltage needed on control gate CG is smaller,
For example reduce 1.6V, so that in the operating process of memory cell, required power consumption is smaller.In addition, of the invention
It is middle to separate program regions and erasing region, when wiping memory cell, add 0V's on the control gate
Voltage, adds 9V~14V voltage in source region and the first active area 110.
The threshold voltage that memory cell is given with reference to shown in Fig. 5, in Fig. 5 changes with erasing-programming cycle-index
The chart of change, curve c represents the threshold voltage of the programming operation of prior art memory cell, and curve d is represented
The threshold voltage of the programming operation of memory cell of the present invention, curve e represents clashing for prior art memory cell
The threshold voltage of operation, curve f represents threshold voltage when clashing operation of memory cell of the present invention.From Fig. 5
In as can be seen that relative in the prior art, programming transistor is added in memory cell, has no effect on and deposits
The use of the erasing-programming of storage unit.
In summary, in memory cell that the present invention is provided and preparation method thereof, including a programming transistor,
Program regions and erasing region are separated, operation is programmed in the programming transistor to memory cell, reaches
Operating voltage needed on identical program window, control gate is smaller, can preferably protect memory cell,
The power consumption of memory cell is reduced, so as to improve the performance of memory cell, extends the service life of memory cell.
Obviously, those skilled in the art can carry out various changes and modification without departing from this hair to the present invention
Bright spirit and scope.So, if the present invention these modifications and variations belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprising including these changes and modification.
Claims (13)
1. a kind of memory cell, it is characterised in that including：Semiconductor substrate；Drain region, bonding pad and the source region arranged in the first direction successively in the Semiconductor substrate, the selection grid in the Semiconductor substrate between the drain region and the bonding pad, the floating boom in the Semiconductor substrate between the bonding pad and the source region, the length that the floating boom extends in a second direction is more than the selection grid；Side of the floating boom in this second direction away from the selection grid is formed with first end and the second end, control gate is formed with the first end, programming source region and programming drain region are respectively formed with the Semiconductor substrate of second end both sides, second end, the programming source region and the programming drain region form programming transistor.
2. memory cell as claimed in claim 1, it is characterised in that the selection grid is formed with the floating boom by one first polysilicon.
3. memory cell as claimed in claim 2, it is characterised in that the control gate is formed by one second polysilicon.
4. memory cell as claimed in claim 3, it is characterised in that second polysilicon also covers the drain region, the source region and the bonding pad.
5. memory cell as claimed in claim 4, it is characterised in that the source region, the bonding pad and the drain region are p-type doping.
6. memory cell as claimed in claim 4, it is characterised in that be formed with first through hole on second polysilicon in the covering drain region, the second through hole is formed with second polysilicon for covering the source region.
7. memory cell as claimed in claim 4, it is characterised in that the programming source region and the programming drain region are n-type doping, and the programming transistor is nmos pass transistor.
8. the programming source region, is connected by memory cell as claimed in claim 3, it is characterised in that second polysilicon also covers programming source region and the programming drain region by second polysilicon with the programming drain region.
9. memory cell as claimed in claim 8, it is characterised in that be formed with third through-hole on second polysilicon of the covering programming source region or on second polysilicon in the covering programming drain region.
10. memory cell as claimed in claim 1, it is characterised in that be formed with the selection grid on fourth hole, the control gate and be formed with fifth hole, the fifth hole is located on the control gate by the first end.
11. memory cell as claimed in claim 1, it is characterised in that the first direction and the second direction are vertical.
12. add the voltage for adding 0V on 9V~14V voltage, second end on memory cell as claimed in claim 1, it is characterised in that during programming operation, the control gate.
13. add the voltage for adding 9V~14V in 0V voltage, the source region on memory cell as claimed in claim 1, it is characterised in that during erasing operation, the control gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610263582.1A CN107316657B (en) | 2016-04-26 | 2016-04-26 | Memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610263582.1A CN107316657B (en) | 2016-04-26 | 2016-04-26 | Memory cell |
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| Publication Number | Publication Date |
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| CN107316657A true CN107316657A (en) | 2017-11-03 |
| CN107316657B CN107316657B (en) | 2020-08-28 |
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| CN201610263582.1A Active CN107316657B (en) | 2016-04-26 | 2016-04-26 | Memory cell |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019113921A1 (en) * | 2017-12-15 | 2019-06-20 | 成都锐成芯微科技股份有限公司 | Flash memory programming circuit and programming method, and flash memory |
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| CN104617048A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and forming method thereof |
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2016
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| US20100309729A1 (en) * | 2009-06-09 | 2010-12-09 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of manufacturing the same |
| CN103377701A (en) * | 2012-04-24 | 2013-10-30 | 华邦电子股份有限公司 | Semiconductor memory device |
| US20140293709A1 (en) * | 2013-04-01 | 2014-10-02 | SK Hynix Inc. | Single-layer gate eeprom cell, cell array including the same, and method of operating the cell array |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2019113921A1 (en) * | 2017-12-15 | 2019-06-20 | 成都锐成芯微科技股份有限公司 | Flash memory programming circuit and programming method, and flash memory |
| TWI697777B (en) * | 2017-12-15 | 2020-07-01 | 大陸商成都銳成芯微科技股份有限公司 | The flash memory programming circuit, programming method and flash memory |
| US10964391B2 (en) | 2017-12-15 | 2021-03-30 | Chengdu Analog Circuit Technology Inc | Programming circuit and programming method of flash memory and flash memory |
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| CN107316657B (en) | 2020-08-28 |
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