CN104143024B - Quick time-domain simulation method for high-speed parallel link system - Google Patents
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- 230000014509 gene expression Effects 0.000 claims description 8
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- 238000006467 substitution reaction Methods 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims description 3
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- 230000007547 defect Effects 0.000 description 1
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- 238000011156 evaluation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 102000054766 genetic haplotypes Human genes 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000009022 nonlinear effect Effects 0.000 description 1
- 238000011017 operating method Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
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Abstract
The invention discloses a quick time-domain simulation method for a high-speed parallel link system. The quick time-domain simulation method for the high-speed parallel link system can solve the problems that in the prior art, pulse edges are not symmetric, a nonlinear system driver of a device can not get a worst code pattern and a worst eye pattern, calculation description on signal dithering parameters is ambiguous, and the calculation accuracy of the eye width is not high. The quick time-domain simulation method comprises the implementation steps of (1) selecting the high-speed parallel link system, (2) establishing a SPICE model, (3) obtaining an edge response signal, (4) calculating a simulation order, (5) obtaining a rising edge vector and a dropping edge vector, (6) obtaining a worst code pattern sequence vector, (7) obtaining an estimated worst eye pattern, (8) simulating the worst eye pattern through the SPICE model established in the step (2), and (9) obtaining an absolute error with the estimated accuracy. By means of the quick time-domain simulation method, the accurate eye width and dithering data can be obtained.
Description
Technical field
The invention belongs to electronic technology field, further relates to the fast time-domain simulation technical field of High-speed Board Design
In a kind of parallel high-speed links system fast time-domain emulation mode.Present invention can apply to in parallel high-speed links system
The assessment of the worst systematic function.
Background technology
As electronic system is to the trend development of high speed, high density, low-voltage and high current, the speed of plate level interconnection is also got over
Come faster, reflect, crosstalk, the signal integrity such as ground bullet and intersymbol interference (intersymbol interference ISI) is asked
Topic is increasingly highlighted, and the problems referred to above have a serious impact to the signal quality that parallel high-speed links system is received, therefore parallel
Impact of these problems of Signal Integrity of rapid evaluation to systematic function is most important in high-speed link design.Estimate at present parallel
The method of high-speed link systematic function mainly has statistics domain method and time domain approach, and is based on false in the simulation flow of statistics link
If data template and jitter spectrum are white, system is linear.These hypothesis will cause emulation not accurate enough.And time domain is fast
Fast emulation mode can not only overcome the defect of statistics domain emulation method to carry out accurately to parallel high-speed links systematic function
Quickly assessment.
" the An accurate and efficient that Casper B.K., Haycok M.and Mooney R are delivered
analysis method for multi-Gb/s chip-to-chip signaling schemes”(IEEE Symposium
On VLSI Circuits Digest of Technical Papers.2002, Jun.54-57) paper, propose first in text
Peak distortion analysis (Peak Distortion Analysis PDA) time-domain simulation method, it is truly to start quick
The beginning of time-domain-simulation technology.Peak distortion analysis (Peak Distortion Analysis PDA) predict the worst pattern totality
Divide two parts：Part I, predicts the pattern that intersymbol interference (Inter Symbol Interference ISI) affects；Second
Part, predicts the pattern of cross talk effects.The prediction of cross talk effects need not determine primary cursor, other steps and intersymbol interference (Inter
Symbol Interference ISI) it is consistent.The operation of crosstalk is than intersymbol interference (Inter Symbol Interference
ISI it is) simpler, it is only necessary to be according to intersymbol interference (Inter Symbol Interference ISI) latter two operating procedure
Can.But, the method is disadvantageous in that：For rising edge responses and declining the asymmetric situation of edge responses, according to peak
Value distortion analysis (Peak Distortion Analysis PDA) method, the situation that edge response connects 1 is true by forecasting inaccuracy.Institute
System to be constituted for the asymmetric driver in edge, peak distortion analysis (Peak Distortion Analysis PDA)
The eye of method prediction is high may be bigger than normal than actual value.
Patent of invention " the TECHNIQUE FOR DETERMINING of Rambus Inc., Los Altos, CA (US) application
PERFORMANCE CHARACTERISTICS OF ELECTRONIC SYSTEMS”(United States Patent
Application, Appl.No.:10/097133, Patent No.:The BI of US 6775809, Date of Patent:Aug,
10,2004) in disclose a kind of bilateral along response (Double Edge Responses DER) time-domain simulation method.The method
Predominantly two steps：The first step, asks vector, second step, solution vector.The purpose of the method is to solve for out causing in edge impulse response
The worst high level, the worst low level, best high level, best low level vector.The weak point of the method exists
In：And device non-linearity system drive asymmetric for porch is possible to that the worst pattern and the worst eye pattern cannot be obtained；
Although bilateral can emulate nonlinear system along response (Double Edge Responses DER) time-domain simulation method,
Current bit period (Unit is not accounted for due to bilateral along response (Double Edge Responses DER) time-domain simulation method
Inerval UI) driver outside scope switch activity, in this way can not abundant capture systems nonlinear effect pair
The impact of subsequent symbol.
" the Multiple edge responses for fast and accurate that Ren J.and Oh D are delivered
system simulations”(IEEE Transactions on Advanced Packaging.2008,Nov,31(4)
.741-748.) many edges response (Multiple Edge Responses MER) time-domain simulation methods are proposed in paper.Should
Method is comprised the following steps that：1st, many edge response (Multiple Edge Responses MER) rising edges, decline are defined
Side；2nd, vector is sought；3rd, emulation exponent number is determined；4th, solution vector.The method is disadvantageous in that：The method is to signal jitter parameter
Calculating description not enough clearly, only give the high correction data of eye and do not provide the wide contrast number of eye in end product checking
According to, and the wide computational accuracy of eye is not high.
The content of the invention
It is an object of the invention to overcome the shortcomings of above-mentioned prior art, a kind of the quick of parallel high-speed links system is proposed
Time-domain simulation method (Best Time-Domain Simulation BTDS), to obtain, porch is asymmetric and device non-thread
The worst pattern of sexual system driver, and the wide simulation accuracy of eye is improve, and then design good system drive.
For achieving the above object, concrete steps of the invention include as follows：
(1) from parallel high-speed links system.
(2) SPICE models are set up：
By the live width in parallel high-speed links system, distance between centers of tracks, dielectric thickness, dielectric constant, fissipation factor and transmission line
Thickness parameter value, is assigned to corresponding parameter in general-purpose simulation circuit emulator SPICE models, completes parallel high-speed links system
The foundation of SPICE models.
(3) edge response signal is obtained：
(3a) the rising edge signal 00000001111 of benchmark is loaded in general-purpose simulation circuit emulator SPICE models
Emulated, obtained benchmark rising edge response signal；
(3b) the trailing edge signal 11111110000 of benchmark is loaded in general-purpose simulation circuit emulator SPICE models
Emulated, obtained benchmark trailing edge response signal；
(3c) the rising edge signal 01010101111 for having bit preamble 0101010 and zero-signal 01010100000 are loaded into
Emulated in general-purpose simulation circuit emulator SPICE models, the simulation result of the two signals is subtracted each other, obtained by bit preamble
Affect rising edge response signal；
(3d) zero-signal 01010100000 for having bit preamble 0101010 is loaded into into general-purpose simulation circuit emulator SPICE
Emulated in model, obtain being affected to decline edge responses signal by bit preamble.
(4) computer sim- ulation exponent number：
According to the following formula, in computer sim- ulation parallel high-speed links system the worst eye pattern exponent number；
Wherein：N represents the exponent number of the worst eye pattern in emulation parallel high-speed links system, and T represents that benchmark rises edge responses letter
Number and persistent period more than 0.1% of the difference subtracted each other by leading position influence rising edge response signal, t represents that benchmark rising edge rings
The rise time of the rising edge of induction signal.
(5) obtain rising edge and decline edge-vector：
(5a) will by leading position influence rising edge response signal value, and the difference of logical zero response signal value more than 0.001
One point, is set as the Sampling starting point by leading position influence rising edge response signal；
(5b) by the rising edge signal 01010101111 for having bit preamble 0101010, it is loaded into general-purpose simulation circuit emulator
In SPICE models, any one attack line in model is emulated, obtain and only have being risen by leading position influence for intersymbol interference
Edge responses signal；
(5c) to only have intersymbol interference by leading position influence rising edge response signal, sentence rising edge letter from Sampling starting point
Number 01010101111 bit wide is sampled for interval, is sampled 15 times, every time 50 points of sampling, is obtained 15 groups and is only had code
Between crosstalk by leading position influence rising edge response signal vector；
(5d) by the crosstalk noise induced on victim line when emulating to attack line, with only intersymbol interference by front
Lead the addition of position influence rising edge response signal, when acquisition has a crosstalk noise by leading position influence rising edge response signal；
(5e) to have during crosstalk noise by leading position influence rising edge response signal, sentence rising edge letter from Sampling starting point
Number 01010101111 bit wide is sampled for interval, is sampled 15 times, every time 50 points of sampling, obtaining 15 groups has crosstalk
It is vectorial by leading position influence rising edge response signal during noise；
(5f) will be affected to decline edge responses signal value by bit preamble, and the difference of the response signal value of logic 1 more than 0.001 the
One point, is set as being affected to decline the Sampling starting point of edge responses signal by bit preamble；
(5g) by the trailing edge signal 01010100000 for having bit preamble 0101010, it is loaded into general-purpose simulation circuit emulator
In SPICE models, any one attack line in model is emulated, obtain only intersymbol interference is affected decline by bit preamble
Edge responses signal；
(5h) on only have intersymbol interference affected by bit preamble decline edge responses signal, from Sampling starting point sentence trailing edge letter
Number 01010100000 bit wide starts sampling for interval, samples 15 times, every time 50 points of sampling, obtains 15 groups and only has code
Between crosstalk affected by bit preamble decline edge responses signal vector；
(5i) by the crosstalk noise induced on victim line when emulating to attack line, with only intersymbol interference by front
The addition of position influence trailing edge response signal is led, being affected by bit preamble when acquisition has crosstalk noise declines edge responses signal；
(5j) on there is being affected by bit preamble during crosstalk noise to decline edge responses signal, from Sampling starting point trailing edge letter is sentenced
Number 01010100000 bit wide starts sampling for interval, samples 15 times, every time 50 points of sampling, and obtaining 15 groups has crosstalk
Being affected by bit preamble during noise declines edge responses signal vector.
(6) the worst pattern sequence vector is obtained：
Using grid method, to there is being carried out by leading position influence rising edge and trailing edge response signal vector during crosstalk noise
Calculate, obtain the worst accumulation voltage and cause the worst pattern sequence vector of the worst eye pattern.
(7) the worst eye pattern estimated is obtained：
The worst pattern sequence vector for obtaining is loaded in general-purpose simulation circuit emulator SPICE models and is emulated,
Simulation result is loaded in general-purpose simulation circuit emulator SPICE waveform viewers, the worst eye pattern is checked, the worst eye is recorded high
It is wide with eye.
(8) the worst eye pattern of parallel high-speed links system is emulated：
Rising edge and the asymmetric input signal of trailing edge are generated with general-purpose simulation circuit emulator SPICE, by input letter
Emulated in the general-purpose simulation circuit emulator SPICE models of number parallel high-speed links system being loaded in step (2), will
Simulation result is loaded in general-purpose simulation circuit emulator SPICE waveform viewers, checks the worst eye pattern, record the worst eye it is high and
Eye is wide.
(9) absolute error of estimate accuracy is obtained：
(9a) by the worst eye in step (8) it is high with step (7) in the high substitution following formula of the worst eye estimated, calculating estimates most
The high absolute error of bad eye；
Wherein：ηHThe absolute error of the high H of the worst eye, H are estimated in expressionBTDSExpression optimum time domain approach BTDS is estimated most
The high H of bad eye, HSPICERepresent the high H of the worst eye with general-purpose simulation circuit emulator SPICE emulation；
(9b) by the worst eye in step (8) it is wide with step (7) in the wide substitution following formula of the worst eye estimated, calculate eye wide
Absolute error；
Wherein：ηWThe absolute error of the wide W of the worst eye, W are estimated in expressionBTDSExpression optimum time domain approach BTDS is estimated most
The wide W of bad eye, WSPICERepresent the wide W of the worst eye with general-purpose simulation circuit emulator SPICE emulation；
(9c) input signal bit wide is deducted into the wide peak-to-peak value that obtains of the worst eye to shake, peak-to-peak value shake is substituted into into following formula, meter
Calculate peak-to-peak value shake absolute error；
Wherein：ηJThe absolute error that peak-to-peak value shakes J, J are estimated in expressionBTDSExpression optimum time domain approach BTDS is estimated
Peak-to-peak value shakes J, JSPICERepresent with the peak-to-peak value shake J of general-purpose simulation circuit emulator SPICE emulation.
The present invention has compared with prior art advantages below：
First, the present invention by rising edge and decline edge-vector carry out leggy sampling, overcome prior art for
Porch is asymmetric and device non-linearity system drive is possible to that the shortcoming of the worst pattern and the worst eye pattern cannot be obtained, and makes
It is of the invention with can and device non-linearity system drive asymmetric for porch accurately obtain the worst pattern and
The advantage of the worst eye pattern.
Second, the emulation tool (Best by the way that optimum time-domain simulation method BTDS to be engineered to optimum time domain of the invention
Time-Domain Simulation Tools BTDS_Tools), in that context it may be convenient to simulate that eye is wide, eye is high and shake data
Value, overcomes prior art to the calculating of signal jitter parameter description not enough clearly, and the wide computational accuracy of eye is not high lacks
Point so that accurate eye is wide with obtaining for the present invention, shakes the advantage of data.
3rd, by the way that the time-domain simulation results of parallel high-speed links system are shown in graphical user interfaces in the present invention
Show, user is clear that simulation result and then judges the quality of designed parallel high-speed links system, overcomes existing
Technology is without the shortcoming for showing simulation result directly perceived so that the present invention has the advantages that clearly check simulation result.
Description of the drawings
Fig. 1 is the flow chart of the present invention；
Fig. 2 is the analogous diagram of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawings the invention will be further described.
The implementation steps of the present invention are further described with reference to Fig. 1.
Step 1, from parallel high-speed links system.
Parallel high-speed links system is double from the third generation of the SKhynix of Hynix company production in embodiments of the invention
Haplotype data rate Synchronous Dynamic Random Access Memory (Double-Data-Rate Three Synchronous Dynamic
Random Access Memory DDR3) parallel high-speed links system carries out time-domain-simulation.
Step 2, sets up SPICE models.
By the live width in parallel high-speed links system, distance between centers of tracks, dielectric thickness, dielectric constant, fissipation factor and transmission line
Thickness parameter value, is assigned to corresponding parameter in general-purpose simulation circuit emulator SPICE models, completes parallel high-speed links system
The foundation of general-purpose simulation circuit emulator SPICE models.
Step 3, obtains edge response signal.
The rising edge signal 00000001111 of benchmark is loaded in general-purpose simulation circuit emulator SPICE models to be carried out
Emulation, obtains benchmark rising edge response signal.
The trailing edge signal 11111110000 of benchmark is loaded in general-purpose simulation circuit emulator SPICE models to be carried out
Emulation, obtains benchmark trailing edge response signal.
The rising edge signal 01010101111 for having bit preamble 0101010 and zero-signal 01010100000 are loaded into general
Emulated in analog circuit emulator SPICE models, the simulation result of the two signals is subtracted each other, obtained by leading position influence
Rising edge response signal.
The zero-signal 01010100000 for having bit preamble 0101010 is loaded into into general-purpose simulation circuit emulator SPICE models
In emulated, obtain by bit preamble affected decline edge responses signal.
Step 4, computer sim- ulation exponent number.
According to the following formula, in computer sim- ulation parallel high-speed links system the worst eye pattern exponent number：
Wherein：N represents the exponent number of the worst eye pattern in emulation parallel high-speed links system, and T represents that benchmark rises edge responses letter
Number and persistent period more than 0.1% of the difference subtracted each other by leading position influence rising edge response signal, t represents that benchmark rising edge rings
The rise time of the rising edge of induction signal.
Step 5, obtains rising edge and declines edge-vector.
Will be by leading position influence rising edge response signal value, and first more than 0.001 of the difference of logical zero response signal value
Point, is set as the Sampling starting point by leading position influence rising edge response signal.
By the rising edge signal 01010101111 for having bit preamble 0101010, general-purpose simulation circuit emulator is loaded into
In SPICE models, any one attack line in model is emulated, obtain and only have being risen by leading position influence for intersymbol interference
Edge responses signal.
To only have intersymbol interference by leading position influence rising edge response signal, sentence rising edge signal from Sampling starting point
01010101111 bit wide is sampled for interval, is sampled 15 times, every time 50 points of sampling, is obtained 15 groups and is only had intersymbol
Crosstalk by leading position influence rising edge response signal vector.
By the crosstalk noise induced on victim line when emulating to attack line, with only intersymbol interference by bit preamble
Affect rising edge response signal to be added, when acquisition has a crosstalk noise by leading position influence rising edge response signal.
To have during crosstalk noise by leading position influence rising edge response signal, sentence rising edge signal from Sampling starting point
01010101111 bit wide is sampled for interval, is sampled 15 times, every time 50 points of sampling, and obtaining 15 groups has crosstalk to make an uproar
It is vectorial by leading position influence rising edge response signal during sound.
To be affected to decline edge responses signal value, and first more than 0.001 of the difference of the response signal value of logic 1 by bit preamble
Point, is set as being affected to decline the Sampling starting point of edge responses signal by bit preamble.
By the trailing edge signal 01010100000 for having bit preamble 0101010, general-purpose simulation circuit emulator is loaded into
In SPICE models, any one attack line in model is emulated, obtain only intersymbol interference is affected decline by bit preamble
Edge responses signal.
On only have intersymbol interference affected by bit preamble decline edge responses signal, sentence trailing edge signal from Sampling starting point
01010100000 bit wide starts sampling for interval, samples 15 times, every time 50 points of sampling, obtains 15 groups and only has intersymbol
Crosstalk affected by bit preamble decline edge responses signal vector.
By the crosstalk noise induced on victim line when emulating to attack line, with only intersymbol interference by bit preamble
Affect to decline the addition of edge responses signal, being affected by bit preamble when acquisition has crosstalk noise declines edge responses signal.
On there is being affected by bit preamble during crosstalk noise to decline edge responses signal, from Sampling starting point trailing edge signal is sentenced
01010100000 bit wide starts sampling for interval, samples 15 times, every time 50 points of sampling, and obtaining 15 groups has crosstalk to make an uproar
Being affected by bit preamble during sound declines edge responses signal vector.
Step 6, obtains the worst pattern sequence vector.
Using grid method, to there is being carried out by leading position influence rising edge and trailing edge response signal vector during crosstalk noise
Calculate, obtain the worst accumulation voltage and cause the worst pattern sequence vector of the worst eye pattern.
Grid method is comprised the following steps that：
The first step, by first class value and 1 phase by leading position influence rising edge response signal vector of only intersymbol interference
Subtract, obtain use grid method calculate needed for rising edge-vector, be labeled as R (1, t), t=1,2 ..., 50, wherein, R (1,
T) represent using grid method calculate needed for rising edge-vector in first group only have intersymbol interference by leading position influence rising edge
Response signal vector, t represents the number for rising the value that edge-vector is included needed for calculating using grid method.
Second step, by only intersymbol interference affected by bit preamble decline edge responses signal vector the first class value and 1 phase
Subtract, obtain use grid method calculate needed for decline edge-vector, be labeled as F (1, t), t=1,2 ..., 50, wherein, F (1,
T) represent using grid method calculate needed for decline edge-vector in first group only have intersymbol interference affected by bit preamble decline
Edge responses signal vector, t represents the number for rising the value that edge-vector is included needed for calculating using grid method.
3rd step, uses A1,i, i=1,2 ..., 51 represent cumulative effect voltage of the intersymbol interference to high level, wherein,
I represents Vector Groups number of the intersymbol interference to the cumulative effect voltage of high level；Use B1,i, i=1,2 ..., 51 represent intersymbol
Crosstalk to low level cumulative effect voltage, wherein, i represents Vector Groups of the intersymbol interference to low level cumulative effect voltage
Number；If high level cumulative effect voltage A1,1=0, low level cumulative effect voltage B1,1=0；Use MH(1, i), i=1,
2 ..., 51 represent the vector for causing high level accumulation voltage, use ML(1, i), i=1,2 ..., 51 expressions cause low
The vector of level L accumulation voltages.
4th step, with R (A1,i,A1,i+1)=0 represents and rises in edge-vector from the cumulative effect voltage A of i-th high level1,i
It is converted to the cumulative effect voltage A of i+1 high level1,i+1Accumulated value be 0；With F (B1,i,B1,i+1)=0 represents trailing edge
From i-th low level cumulative effect voltage B in vector1,iIt is converted to the low level cumulative effect voltage B of i+11,i+1It is tired
Value added is 0；With F (A1,i,B1,i+1)=F (1, i) represent and decline in edge-vector from the cumulative effect voltage A of i-th high leveliTurn
Change to the low level cumulative effect voltage B of i+1i+1Accumulated value be F (1, i)；With R (B1,i,A1,i+1)=R (1, i) represent
Rise in edge-vector from i-th low level cumulative effect voltage BiIt is converted to the cumulative effect voltage A of i+1 high leveli+1
Accumulated value be R (1, i).
5th step, when having crosstalk noise by leading position influence rising edge and trailing edge response signal to flow control 0 to
The negative value of the lookup signal vector in the 50th value successively, records the position i of negative value；As high level accumulation voltage vector MH(1,i
+ 1) when i+1 value is 1, i-th high level accumulation voltage A1,iIt is converted to i+1 high level accumulation voltage A1,i+1It is tired
It is value added for R (Ai,Ai+1)；When the vector M of high level accumulation voltageHWhen the i+1 value of (1, i+1) is 0, i-th high level tires out
Product voltage A1,iIt is converted to i+1 high level accumulation voltage A1,i+1Accumulated value be F (Ai,Bi+1)；When finding out signal vector
All negative values when, obtain when first group has crosstalk noise caused by leading position influence rising edge response signal vector it is total
High level accumulation voltage A1,51。
6th step, repeat the 5th step, until draw it is all have crosstalk noise when by leading position influence rising edge response believe
Total high level accumulation voltage A that number vector causes2,51,A3,51,A4,51,A5,51,......A14,51,A14,51。
7th step, compares this 15 total high level accumulation voltage AN, 51, n=1,2,3 ... 15, draw the worst
Accumulation voltage Aj,51；Cause the worst accumulation voltage Aj,51Pattern vector be MH(j, i), i=1,2 ..., 51, wherein,
MH(j, i) represents the pattern vector of the worst accumulation voltage of high level H.
8th step, from the 0th to the 50th by leading position influence rising edge response signal vector of only intersymbol interference
In value successively lookup signal vector on the occasion of, record on the occasion of position i；As low level accumulation voltage vector ML(1, i+1)
When i+1 value is 0, i-th low level accumulation voltage B1,iIt is converted to i+1 low level accumulation voltage B1,i+1Accumulated value
For F (Bi,Bi+1)；When the vector M of low level accumulation voltageLWhen the i+1 value of (1, i+1) is 1, i-th low level accumulation electricity
Pressure B1,iIt is converted to i+1 low level accumulation voltage B1,i+1Accumulated value be R (Bi,Ai+1)；When the institute for finding out signal vector
Have on the occasion of when, obtain by first group only have intersymbol interference caused by leading position influence rising edge response signal vector it is total low
Level accumulation voltage B1,51。
9th step, repeat step eight is until showing that remaining 14 groups only have being rung by leading position influence rising edge for intersymbol interference
Total low level accumulation voltage B that induction signal vector causes2,51,B3,51,B4,51,B5,51,......B14,51,B14,51。
Tenth step, compares this 15 total low level accumulation voltage BN, 51, n=1,2,3 ... 15, draw the worst
Accumulation voltage Bj,51, cause the worst accumulation voltage Bj,51Pattern vector be ML(j, i), i=1,2 ..., 51, wherein,
ML(j, i) represents the pattern vector of the worst accumulation voltage of low level L.
Above step be with grid method to have during crosstalk noise by leading position influence rising edge response signal vector sum only
There is being calculated by leading position influence rising edge response signal vector for intersymbol interference, obtain the worst accumulation voltage and cause the worst
The worst pattern sequence vector of eye pattern.
Step 7, obtains the worst eye pattern estimated.
The worst pattern sequence vector for obtaining is loaded in general-purpose simulation circuit emulator SPICE models and is emulated,
Simulation result is loaded in general-purpose simulation circuit emulator SPICE waveform viewers, the worst eye pattern is checked, the worst eye is recorded high
It is wide with eye.
Step 8, emulates the worst eye pattern of parallel high-speed links system.
Rising edge and the asymmetric input signal of trailing edge are generated with general-purpose simulation circuit emulator SPICE, by input letter
Emulated in the general-purpose simulation circuit emulator SPICE models of number parallel high-speed links system being loaded in step (2), will
Simulation result is loaded in general-purpose simulation circuit emulator SPICE waveform viewers, checks the worst eye pattern, record the worst eye it is high and
Eye is wide.
Step 9, obtains the absolute error of estimate accuracy.
By the worst eye in step (8) it is high with step (7) in the high substitution following formula of the worst eye estimated, calculating estimates the worst eye
High absolute error.
Wherein：ηHThe absolute error of the high H of the worst eye, H are estimated in expressionBTDSExpression optimum time domain approach BTDS is estimated most
The high H of bad eye, HSPICERepresent the high H of the worst eye with general-purpose simulation circuit emulator SPICE emulation.
By the worst eye in step (8) it is wide with step (7) in the wide substitution following formula of the worst eye estimated, calculate wide absolute of eye
Error.
Wherein：ηWThe absolute error of the wide W of the worst eye, W are estimated in expressionBTDSExpression optimum time domain approach BTDS is estimated most
The wide W of bad eye, WSPICERepresent the wide W of the worst eye with general-purpose simulation circuit emulator SPICE emulation.
Input signal bit wide is deducted into the wide peak-to-peak value that obtains of the worst eye to shake, peak-to-peak value shake is substituted into into following formula, calculate peak
Peak Jitter absolute error.
Wherein：ηJThe absolute error that peak-to-peak value shakes J, J are estimated in expressionBTDSExpression optimum time domain approach BTDS is estimated
Peak-to-peak value shakes J, JSPICERepresent with the peak-to-peak value shake J of general-purpose simulation circuit emulator SPICE emulation.
Effect of the present invention is further described with reference to emulation experiment.
1. simulated conditions.
The simulated conditions of the present invention are emulated using general-purpose simulation circuit emulator SPICE emulation tools, peak distortion analysis
Instrument PDA_Tools, optimum time-domain simulation method emulation tool BTDS_Tools, Hynix Skhynix decks files；
2. simulation process
The parameter setting of Hynix Skhynix decks files is as follows：Rising edge is 20ps, and trailing edge is 50ps, position
Cycle UI is 750ps, and step-length 10ps, simulation time is 40ns.
The simulation result of peak distortion analysis PDA and optimum time domain BTDS emulation mode is verified, is predicted
Eye pattern predicts the outcome and is put into the eye diagram results that obtain of general-purpose simulation circuit emulator SPICE emulation with its pattern for obtaining and enters
Row contrast, error should be less than 5%, be calculated with below equation and validation error comparing result.
Wherein：ηHThe absolute error of the high H of the worst eye, H are estimated in expressionBTDSExpression optimum time domain approach BTDS is estimated most
The high H of bad eye, HSPICERepresent the high H of the worst eye with general-purpose simulation circuit emulator SPICE emulation；ηWThe wide W of the worst eye is estimated in expression
Absolute error, WBTDSThe wide W of the worst eye, W that expression optimum time domain approach BTDS is estimatedSPICERepresent imitative with general-purpose simulation circuit
The wide W of the worst eye of true device SPICE emulation.
The concrete operations step that the simulation result of peak distortion analysis PDA and optimum time domain BTDS emulation mode is verified
It is rapid as follows.
The first step, imports peak distortion analysis the tr0 files that general-purpose simulation circuit emulator SPICE emulation is obtained first
Emulation tool PDA_Tools, obtains that eye pattern eye is high, and eye is wide and jitter parameter value.Then according to peak distortion analysis PDA methods
The pattern that obtains is imported in general-purpose simulation circuit emulator SPICE and emulated, and it is high to record the eye for obtaining, and eye is wide and jitter value.Emulation
As a result show, a height of 666.6mv of eye, a width of 531.4ps of eye that peak distortion analysis emulation tool PDA_Tools predictions are obtained.
The a height of 809mv of the eye for obtaining, a width of 608ps of eye are measured in general-purpose simulation circuit emulator SPICE.The wide error of the high and eye of eye surpasses
10% is crossed, can be drawn the following conclusions from data above：Peak distortion analysis PDA methods cannot process rising edge and trailing edge not
Symmetrical situation.
Second step, adopts that eye that optimum time-domain simulation method BTDS is obtained is high to predict the outcome as 793mv, and eye is wide, is
698.4ps.The pattern obtained with optimum time-domain simulation method BTDS is put into what general-purpose simulation circuit emulator SPICE emulation was obtained
The a height of 795mv of eye, it is then 697ps that eye is wide, and simulation result is as shown in Figure 2.Wherein Fig. 2 (a) and 2 (b) are optimum using the present invention
The profile and eye pattern of the emulation mode BTDS prediction of time domain；Fig. 2 (c) and 2 (d) are the emulation sides using prior art optimum time domain
The pattern sequence that method BTDS is generated is put into the eye pattern that general-purpose simulation circuit emulator SPICE emulation is obtained.
3rd step, with what optimum time-domain simulation method BTDS was predicted 189.2ps is dithered as.The pattern that prediction is obtained is put into
Verify in general-purpose simulation circuit emulator SPICE, what is obtained is dithered as 196.13ps, simulation result such as Fig. 2 (c) and 2 (d).It is right
Peak distortion analysis PDA emulation modes, present invention optimum time domain BTDS emulation mode and general-purpose simulation circuit emulator SPICE
Simulation result such as following table.
| PDA/SPICE | PDA errors | BTDS/SPICE | BTDS errors | |
| Eye high (mv) | 666.6/809 | 21.36% | 697/670.2 | 3.8% |
| Eye wide (ps) | 531.4/608 | 14.4% | 561/553.9 | 1.2% |
| Peak-to-peak value shakes (ps) | 217.6/141 | 35.1% | 189.2/196.13 | 3.7% |
Wherein：PDA represents peak distortion analysis emulation mode, and SPICE is represented using the imitative of general-purpose simulation circuit emulator
True method, BTDS represents optimum time-domain simulation method.
3. simulation result and analysis.
By contrasting with general-purpose simulation circuit emulator SPICE simulation results, the optimum time-domain-simulation in the present invention
Eye that method BTDS is obtained is wide, eye is high and jitter error absolute value is respectively less than 5%.
It is not right that the optimum time-domain simulation method BTDS of the present invention can either solve parallel high-speed links system drive edge
Title problem can obtain the worst pattern and eye pattern again, may certify that the present invention better than peak distortion by the emulation data of upper table
Analysis PDA time-domain simulation methods and bilateral edge response DER time-domain simulation methods, and wide and shake the data of eye have been drawn, and
MER time-domain simulation methods are responded better than many edges.
Claims (1)
1. a kind of fast time-domain emulation mode of parallel high-speed links system, comprises the following steps that：
(1) from parallel high-speed links system；
(2) SPICE models are set up：
By the live width in parallel high-speed links system, distance between centers of tracks, dielectric thickness, dielectric constant, fissipation factor and transmission line thickness
Parameter value, is assigned to corresponding parameter in general-purpose simulation circuit emulator SPICE models, completes the general of parallel high-speed links system
The foundation of analog circuit emulator SPICE models；
(3) edge response signal is obtained：
(3a) the rising edge signal 00000001111 of benchmark is loaded in general-purpose simulation circuit emulator SPICE models is carried out
Emulation, obtains benchmark rising edge response signal；
(3b) the trailing edge signal 11111110000 of benchmark is loaded in general-purpose simulation circuit emulator SPICE models is carried out
Emulation, obtains benchmark trailing edge response signal；
(3c) the rising edge signal 01010101111 for having bit preamble 0101010 and zero-signal 01010100000 are loaded into general
Emulated in analog circuit emulator SPICE models, the simulation result of the two signals is subtracted each other, obtained by leading position influence
Rising edge response signal；
(3d) zero-signal 01010100000 for having bit preamble 0101010 is loaded into into general-purpose simulation circuit emulator SPICE models
In emulated, obtain by bit preamble affected decline edge responses signal；
(4) computer sim- ulation exponent number：
According to the following formula, in computer sim- ulation parallel high-speed links system the worst eye pattern exponent number；
Wherein：N represent emulation parallel high-speed links system in the worst eye pattern exponent number, T represent benchmark rising edge response signal and
The persistent period that the difference subtracted each other by leading position influence rising edge response signal is more than 0.1%, t represents that benchmark rises edge responses letter
Number rising edge rise time；
(5) obtain rising edge and decline edge-vector：
(5a) by first by the difference of leading position influence rising edge response signal value and logical zero response signal value more than 0.001
Point, is set as the Sampling starting point by leading position influence rising edge response signal；
(5b) by the rising edge signal 01010101111 for having bit preamble 0101010, it is loaded into general-purpose simulation circuit emulator
In SPICE models, any one attack line in model is emulated, obtain and only have being risen by leading position influence for intersymbol interference
Edge responses signal；
(5c) to only have intersymbol interference by leading position influence rising edge response signal, sentence rising edge signal from Sampling starting point
01010101111 bit wide is sampled for interval, is sampled 15 times, every time 50 points of sampling, is obtained 15 groups and is only had intersymbol
Crosstalk by leading position influence rising edge response signal vector；
(5d) by the crosstalk noise induced on victim line when emulating to attack line, with only intersymbol interference by bit preamble
Affect rising edge response signal to be added, when acquisition has a crosstalk noise by leading position influence rising edge response signal；
(5e) to have during crosstalk noise by leading position influence rising edge response signal, sentence rising edge signal from Sampling starting point
01010101111 bit wide is sampled for interval, is sampled 15 times, every time 50 points of sampling, and obtaining 15 groups has crosstalk to make an uproar
It is vectorial by leading position influence rising edge response signal during sound；
(5f) will be affected to decline edge responses signal value, and first more than 0.001 of the difference of the response signal value of logic 1 by bit preamble
Point, is set as being affected to decline the Sampling starting point of edge responses signal by bit preamble；
(5g) by the trailing edge signal 01010100000 for having bit preamble 0101010, it is loaded into general-purpose simulation circuit emulator
In SPICE models, any one attack line in model is emulated, obtain only intersymbol interference is affected decline by bit preamble
Edge responses signal；
(5h) on only have intersymbol interference affected by bit preamble decline edge responses signal, sentence trailing edge signal from Sampling starting point
01010100000 bit wide starts sampling for interval, samples 15 times, every time 50 points of sampling, obtains 15 groups and only has intersymbol
Crosstalk affected by bit preamble decline edge responses signal vector；
(5i) by the crosstalk noise induced on victim line when emulating to attack line, with only intersymbol interference by bit preamble
Affect to decline the addition of edge responses signal, being affected by bit preamble when acquisition has crosstalk noise declines edge responses signal；
(5j) on there is being affected by bit preamble during crosstalk noise to decline edge responses signal, from Sampling starting point trailing edge signal is sentenced
01010100000 bit wide starts sampling for interval, samples 15 times, every time 50 points of sampling, and obtaining 15 groups has crosstalk to make an uproar
Being affected by bit preamble during sound declines edge responses signal vector；
(6) the worst pattern sequence vector is obtained：
Using grid method, to there is being counted by leading position influence rising edge and trailing edge response signal vector during crosstalk noise
Calculate, obtain the worst accumulation voltage and cause the worst pattern sequence vector of the worst eye pattern；
The grid method is comprised the following steps that：
The first step, first class value by leading position influence rising edge response signal vector of only intersymbol interference is subtracted each other with 1, is obtained
Rising edge-vector to needed for being calculated using grid method；
Second step, first class value for being affected to decline edge responses signal vector by bit preamble of only intersymbol interference is subtracted each other with 1, is obtained
Decline edge-vector to needed for being calculated using grid method；
3rd step, uses A1,i, i=1,2 ..., 51 represent cumulative effect voltage of the intersymbol interference to high level, wherein, i tables
Show Vector Groups number of the intersymbol interference to the cumulative effect voltage of high level；Use B1,i, i=1,2 ..., 51 represent intersymbol interference
To low level cumulative effect voltage, wherein, i represents Vector Groups number of the intersymbol interference to low level cumulative effect voltage；If
High level cumulative effect voltage A1,1=0, low level cumulative effect voltage B1,1=0；Use MH(1, i), i=1,2 ..., 51
Expression causes the vector of high level accumulation voltage, uses ML(1, i), i=1,2 ..., 51 expressions cause low level L accumulation electricity
The vector of pressure；
4th step, with R (A1,i,A1,i+1)=0 represents and rises in edge-vector from the cumulative effect voltage A of i-th high level1,iTransformation
To the cumulative effect voltage A of i+1 high level1,i+1Accumulated value be 0；With F (B1,i,B1,i+1)=0 represents and declines edge-vector
In from i-th low level cumulative effect voltage B1,iIt is converted to the low level cumulative effect voltage B of i+11,i+1Accumulated value
For 0；With F (A1,i,B1,i+1)=F (1, i) represent and decline in edge-vector from the cumulative effect voltage A of i-th high leveliIt is converted to
The low level cumulative effect voltage B of i+1i+1Accumulated value be F (1, i)；With R (B1,i,A1,i+1)=R (1, i) represent and rise
From i-th low level cumulative effect voltage B in edge-vectoriIt is converted to the cumulative effect voltage A of i+1 high leveli+1It is tired
It is value added for R (1, i)；
5th step, when having crosstalk noise by leading position influence rising edge and trailing edge response signal to flow control 0 to the 50th
The negative value of the lookup signal vector in individual value successively, records the position i of negative value；As high level accumulation voltage vector MH(1,i+1)
I+1 value for 1 when, i-th high level accumulation voltage A1,iIt is converted to i+1 high level accumulation voltage A1,i+1It is cumulative
It is worth for R (Ai,Ai+1)；When the vector M of high level accumulation voltageHWhen the i+1 value of (1, i+1) is 0, i-th high level accumulation
Voltage A1,iIt is converted to i+1 high level accumulation voltage A1,i+1Accumulated value be F (Ai,Bi+1)；When finding out signal vector
During all negative values, obtain when first group has crosstalk noise caused by leading position influence rising edge response signal vector it is total
High level accumulation voltage A1,51；
6th step, repeat the 5th step, until draw it is all have crosstalk noise when by leading position influence rising edge response signal to
Total high level accumulation voltage that amount causes；
7th step, compares all total high level accumulation voltage for drawing, draws the worst accumulation voltage；
8th step, from the 0th to the 50th value by leading position influence rising edge response signal vector of only intersymbol interference
Successively lookup signal vector on the occasion of, record on the occasion of position i；As low level accumulation voltage vector MLThe i+1 of (1, i+1)
When individual value is 0, i-th low level accumulation voltage B1,iIt is converted to i+1 low level accumulation voltage B1,i+1Accumulated value be F
(Bi,Bi+1)；When the vector M of low level accumulation voltageLWhen the i+1 value of (1, i+1) is 1, i-th low level accumulation voltage
B1,iIt is converted to i+1 low level accumulation voltage B1,i+1Accumulated value be R (Bi,Ai+1)；When finding out all of signal vector
On the occasion of when, obtain by first group of total low electricity caused by leading position influence rising edge response signal vector for only having intersymbol interference
Flat accumulation voltage B1,51；
9th step, repeats the 8th step until drawing the vectorial by leading position influence rising edge response signal of all only intersymbol interferences
The total low level accumulation voltage for causing；
Tenth step, compares all total low level accumulation voltage for drawing, draws the worst accumulation voltage；
(7) the worst eye pattern estimated is obtained：
The worst pattern sequence vector for obtaining is loaded in general-purpose simulation circuit emulator SPICE models and is emulated, will be imitative
True result is loaded in general-purpose simulation circuit emulator SPICE waveform viewers, checks the worst eye pattern, records that the worst eye is high and eye
It is wide；
(8) the worst eye pattern of parallel high-speed links system is emulated：
Generate rising edge and the asymmetric input signal of trailing edge with general-purpose simulation circuit emulator SPICE, by input signal plus
Emulated in the general-purpose simulation circuit emulator SPICE models of the parallel high-speed links system being downloaded in step (2), will be emulated
As a result in being loaded into general-purpose simulation circuit emulator SPICE waveform viewers, the worst eye pattern is checked, records that the worst eye is high and eye
It is wide；
(9) absolute error of estimate accuracy is obtained：
(9a) by the worst eye in step (8) it is high with step (7) in the high substitution following formula of the worst eye estimated, calculating estimates the worst eye
High absolute error；
Wherein：ηHThe absolute error of the high H of the worst eye, H are estimated in expressionBTDSThe worst eye that expression optimum time domain approach BTDS is estimated
High H, HSPICERepresent the high H of the worst eye with general-purpose simulation circuit emulator SPICE emulation；
(9b) by the worst eye in step (8) it is wide with step (7) in the wide substitution following formula of the worst eye estimated, calculate wide absolute of eye
Error；
Wherein：ηWThe absolute error of the wide W of the worst eye, W are estimated in expressionBTDSThe worst eye that expression optimum time domain approach BTDS is estimated
Wide W, WSPICERepresent the wide W of the worst eye with general-purpose simulation circuit emulator SPICE emulation；
(9c) input signal bit wide is deducted into the wide peak-to-peak value that obtains of the worst eye to shake, peak-to-peak value shake is substituted into into following formula, calculate peak
Peak Jitter absolute error；
Wherein：ηJThe absolute error that peak-to-peak value shakes J, J are estimated in expressionBTDSThe peak-to-peak that expression optimum time domain approach BTDS is estimated
Value shake J, JSPICERepresent with the peak-to-peak value shake J of general-purpose simulation circuit emulator SPICE emulation.
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| CN107305229B (en) * | 2016-04-22 | 2020-08-14 | 迈普通信技术股份有限公司 | Method and device for evaluating quality of passive link |
| CN106886637B (en) * | 2017-01-23 | 2019-08-06 | 西安电子科技大学 | Time Domain Analysis based on PDN Yu channel Cooperative Analysis method |
| CN107330221B (en) * | 2017-07-21 | 2020-06-16 | 西安电子科技大学 | Method for realizing worst eye diagram based on PDN and channel cooperative model |
| CN107292066A (en) * | 2017-08-14 | 2017-10-24 | 郑州云海信息技术有限公司 | A kind of encryption mixed model SI emulation modes based on ADS and HSPICE |
| CN109033534B (en) * | 2018-06-29 | 2023-04-28 | 西安电子科技大学 | Output device time sequence jitter estimation method based on pseudo-drain open-circuit termination |
| CN112329372A (en) * | 2020-11-17 | 2021-02-05 | 南京蓝洋智能科技有限公司 | Method for generating code pattern for signal integrity analysis |
| CN113536717B (en) * | 2021-07-14 | 2022-05-24 | 北京华大九天科技股份有限公司 | Circuit simulation method based on incremental compilation |
| CN115941129B (en) * | 2022-10-17 | 2024-04-16 | 西安电子科技大学 | High-speed link eye diagram implementation method based on linear fitting error matrix |
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