CN104124154B - The forming method of bipolar transistor, semiconductor devices and bipolar transistor - Google Patents

The forming method of bipolar transistor, semiconductor devices and bipolar transistor Download PDF

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Publication number
CN104124154B
CN104124154B CN201310156949.6A CN201310156949A CN104124154B CN 104124154 B CN104124154 B CN 104124154B CN 201310156949 A CN201310156949 A CN 201310156949A CN 104124154 B CN104124154 B CN 104124154B
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nano wire
base
area
insulating barrier
type
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CN104124154A (en
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李勇
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Thin Film Transistor (AREA)

Abstract

A kind of forming method of bipolar transistor, semiconductor devices and bipolar transistor, wherein, the forming method of bipolar transistor includes：Substrate is provided, insulating barrier, the nano wire on insulating barrier are formed with substrate, it is middle area to define the partial-length nano wire between nano wire two ends；Remove the insulating barrier formation vacancy section of segment thickness under the middle area；After the vacancy section is formed, first kind impurity doping is carried out to area in area in partial-length or whole, base is formed；After base is formed, or before base is formed, Second Type impurity doping is carried out to the nano wire of base both sides, collecting zone and launch site is formed, the type of the first kind impurity is opposite with the type of the Second Type impurity.The present invention combines the transistor fabrication process manufacture bipolar transistor with all-around-gate pole, realizes the compatibility of transistor fabrication and bipolar transistor manufacturing process with all-around-gate pole.

Description

The forming method of bipolar transistor, semiconductor devices and bipolar transistor
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of bipolar transistor, semiconductor devices and bipolar transistor The forming method of pipe.
Background technology
In technical field of semiconductors, bipolar transistor is particularly suitable for use in handling radio frequency（RF）The signal in domain, especially exists There is wide application in terms of handling high-frequency signal.
Bipolar transistor has two kinds of basic structures：NPN type and positive-negative-positive, are made up of two back-to-back PN junctions.Using NPN as Example, prior art discloses a kind of npn type bipolar transistor structure, referring in particular to Fig. 1, including：P-type semiconductor substrate 100；Position The first N well regions 101 in Semiconductor substrate；Surrounded by the first N well regions 101 and the p-well region 102 in substrate 100；By P Well region 102 is surrounded and the 2nd N well regions 103 in substrate 100.Wherein, p-well region 102 as npn type bipolar transistor base Area, the launch site and current collection of the first N well regions 101 and the 2nd N well regions 103 of the both sides of p-well region 102 respectively as NPN transistor Area, can form transmitting PN junction between launch site and base, and current collection PN junction can be formed between collecting zone and base.
The research of the structure and manufacture method of bipolar transistor is long-standing, the structure of common bipolar transistor and manufacture Method may be referred to the Chinese patent literature of Publication No. CN1057547A disclosed in 1 day January in 1992.In the prior art, Bipolar transistor is generally manufactured using CMOS transistor manufacturing process, wherein a big chunk reason is CMOS transistor manufacture Technique is simple, cost is low, and the cost of simple bipolar transistor manufacturing process is higher.With integrated circuit integrated level increasingly Height, following feature sizes of semiconductor devices is less and less, and traditional CMOS transistor manufacturing process faces huge challenge, utilizes The technique of conventional CMOS transistors manufacturing process manufacture bipolar transistor also runs into obstacle.In the prior art, industry is generally recognized For with all-around-gate pole（Gate-All-Around, GAA）The field-effect transistor of nano wire（FET）It is considered as that reply should One of most promising semiconductor devices of challenge.With all-around-gate pole（GAA）The transistor fabrication of nano wire is base In SOI substrate manufacturing process, manufacturing process is simple and good with conventional planar CMOS technology compatibility, obtains generally recognizing for industry Can.
But, in the prior art, there is not yet using with all-around-gate pole（GAA）The transistor manufacture work of nano wire Skill manufactures the technology of bipolar transistor.
The content of the invention
The problem of present invention is solved is to provide a kind of using with all-around-gate pole（GAA）The transistor manufacture work of nano wire Skill manufactures the technology of bipolar transistor.
To solve the above problems, the present invention provides a kind of forming method of new bipolar transistor, including：
Substrate is provided, insulating barrier, the nano wire on the insulating barrier is formed with over the substrate, received described in definition Partial-length nano wire region between rice noodles two ends is middle area；
Remove the insulating barrier formation vacancy section of segment thickness under the middle area；
After the vacancy section is formed, first kind impurity doping is carried out to area in area in partial-length or whole, formed Base；
After base is formed, or before base is formed, Second Type impurity doping is carried out to the nano wire of base both sides, Collecting zone and launch site are formed, the type of the first kind impurity is opposite with the type of the Second Type impurity.
Alternatively, the removal partial insulative layer, the method for the insulating barrier of segment thickness is under area in the removal：Use Wet etching method, etching removes the insulating barrier of segment thickness under the middle area.
Alternatively, before the insulating barrier formation vacancy section of segment thickness under removing the middle area, in addition to：Remove not by The segment thickness insulating barrier of the nano wire covering.
Alternatively, the method for removing the segment thickness insulating barrier not covered by nano wire is anisotropic wet etch Method.
Alternatively, the method that first kind impurity doping is carried out to area in area in partial-length or whole, including：
Form patterned mask layer, the patterned mask layer defines area in area in the partial-length or whole Position；
Using the patterned mask layer as mask, the first kind is carried out to area in area in the partial-length or whole miscellaneous The ion implanting of matter；
Remove the patterned mask layer.
Alternatively, the method that the nano wire to base both sides carries out Second Type impurity doping, including：
Patterned mask layer is formed, the patterned mask layer defines the position of the nano wire of base both sides；
Using the patterned mask layer as mask, the ion note of Second Type impurity is carried out to the nano wire of base both sides Enter；
Remove the patterned mask layer.
Alternatively, the first kind impurity is p-type ion, and Second Type impurity is N-type ion；Or, described first Type dopant is N-type ion, and Second Type impurity is p-type ion.
Alternatively, after the base, collecting zone and launch site is formed, in addition to：Nano wire formation bag described in thermal oxide Enclose the silicon oxide layer of nano wire.
Alternatively, the substrate is silicon-on-insulator substrate, and the silicon-on-insulator substrate includes bottom silicon layer, positioned at institute State the insulating barrier on bottom silicon layer and the top silicon layer on the insulating barrier；
The method for forming the nano wire is that the graphical top silicon layer forms nano wire.
Alternatively, after the base, collecting zone and launch site is formed, in addition to：
Interlayer dielectric layer is formed, the interlayer dielectric layer covers the remaining insulating barrier and nano wire, fills the hollow out Area；
The first connector of the formation connection base, the second of the connection collecting zone insert in the interlayer dielectric layer Plug, connects the 3rd connector of the launch site.
Alternatively, before the interlayer dielectric layer is formed,
First kind impurity doping is carried out to part base, the base stage being located in the base is formed；
After base stage is formed, or formed before base stage, carrying out Second Type impurity to part collecting zone and part launch site mixes It is miscellaneous, form the colelctor electrode being located in the collecting zone, the emitter stage in the launch site；
First connector is connected with base stage, and second connector is connected with colelctor electrode, the 3rd connector and emitter stage Connection.
Alternatively, the substrate includes the firstth area and the secondth area, is formed in firstth area with all-around-gate pole Field-effect transistor, bipolar transistor is formed in secondth area；
The nano wire of the nano wire and the field-effect transistor is formed in same step；
The vacancy section and the vacancy section of the field-effect transistor are formed in same step；
The channel region of the base and the field-effect transistor is formed in same step；
The source electrode of the colelctor electrode, emitter stage and the field-effect transistor, drain electrode are formed in same step；
Conduction on the source electrode of first connector, the second connector, the 3rd connector and the field-effect transistor, drain electrode is slotting Plug is formed in same step.
The present invention also provides a kind of new bipolar transistor, and the bipolar transistor includes：
Between insulating barrier on substrate, the nano wire on the insulating barrier, the definition nano wire two ends Partial-length nano wire is middle area；
Under the middle area, the vacancy section in insulating barrier；
In partial-length in area or whole in area doped with first kind impurity, it is described doped with first kind impurity Middle area part is base；
Doped with Second Type impurity in the nano wire of the base both sides, positioned at base side, doped with Equations of The Second Kind The nanowire portion of type impurity be collecting zone, positioned at base opposite side, doped with Second Type impurity nanowire portion for hair Area is penetrated, the type of the first kind impurity is opposite with the type of the Second Type impurity.
Alternatively, the insulating barrier under the nano wire of the Zhong Qu both sides is higher than the insulating barrier not covered by the nano wire.
Alternatively, the first kind impurity is p-type ion, and Second Type impurity is N-type ion；Or, described first Type dopant is N-type ion, and Second Type impurity is p-type ion.
Alternatively, in addition to：Positioned at the nanowire surface and surround the silicon oxide layer of nano wire, the wheel of the nano wire Exterior feature is cylinder.
Alternatively, in addition to：
Interlayer dielectric layer, the interlayer dielectric layer covers the insulating barrier and nano wire, fills the vacancy section；
First connector of the connection base in the interlayer dielectric layer, the second of the connection collecting zone insert Fill in, connect the 3rd connector of the launch site.
Alternatively, in addition to：
First kind impurity is carried out to part base to adulterate the base stage to be formed；
Adulterate the colelctor electrode to be formed to part collecting zone progress Second Type impurity；
Adulterate the emitter stage to be formed to part launch site progress Second Type impurity；
First connector is connected with base stage, and second connector is connected with colelctor electrode, the 3rd connector and emitter stage Connection.
The present invention also provides a kind of semiconductor devices, and the semiconductor devices includes：
Field-effect transistor with all-around-gate pole；
Any of the above-described described bipolar transistor, the field-effect transistor is located at same substrate with the bipolar transistor On.
Compared with prior art, the present invention has advantages below：
The present invention is to combine to have all-around-gate pole（GAA）Transistor fabrication process manufacture a kind of bipolar transistor.Make With technical scheme, a kind of bipolar transistor of the new similar field-effect transistor with all-around-gate pole is obtained, Realize the good compatibility of field-effect transistor manufacturing process and bipolar transistor manufacturing process with all-around-gate pole.Also It is to say, field-effect transistor and bipolar transistor with all-around-gate pole can be manufactured simultaneously by same technological process. And the present invention is while high-quality bipolar transistor is formed, to the field-effect transistor manufacturing process with all-around-gate pole Change it is less, step is simple and easy to do, and cost is relatively low.
Brief description of the drawings
Fig. 1 is the cross-sectional view of the bipolar transistor of prior art；
Fig. 2 is the schematic flow sheet of the bipolar transistor forming method of the specific embodiment of the invention；
Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A, Fig. 8 A are the bipolar transistor forming methods of first embodiment of the invention Overlooking the structure diagram；
Fig. 3 B, Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 8 B are difference corresponding diagram 3A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A, Fig. 8 A The cross-sectional view along X-X' directions；
Fig. 3 C, Fig. 4 C, Fig. 5 C, Fig. 6 C, Fig. 7 C, Fig. 8 C are difference corresponding diagram 3A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A, Fig. 8 A The cross-sectional view along Y-Y' directions；
Fig. 9~Figure 12 is the cross-sectional view of the bipolar transistor forming method of first embodiment of the invention；
Figure 13~Figure 17, Figure 18 A are the stereochemical structure signals of the bipolar transistor forming method of second embodiment of the invention Figure；
Figure 18 B are the cross-sectional views along Figure 18 A direction of plane 505；
Figure 19 A, Figure 20 A, Figure 21 A, Figure 22 A, Figure 23 A, Figure 24 A, Figure 25 A are the bipolar transistors of third embodiment of the invention The overlooking the structure diagram of pipe forming method；
Figure 19 B, Figure 20 B, Figure 21 B, Figure 22 B, Figure 23 B, Figure 24 B, Figure 25 B be respectively corresponding diagram 19A, Figure 20 A, Figure 21 A, Figure 22 A, Figure 23 A, Figure 24 A, the cross-sectional view in Figure 25 A X-X' directions；
Figure 25 C are the cross-sectional views in corresponding diagram 25A Y-Y' directions；
Figure 25 D are corresponding diagram 25A, Figure 25 B, Figure 25 C dimensional structure diagram.
Embodiment
Inventor passes through creative work, proposes the forming method and a kind of new bipolar crystalline substance of a kind of new bipolar transistor Body pipe, semiconductor devices.
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention Embodiment be described in detail.
First embodiment
In the first embodiment, Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A, Fig. 8 A be the present embodiment bipolar transistor it is tubular Into the top view of method, Fig. 3 B, Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 8 B are difference corresponding diagram 3A, Fig. 4 A, Fig. 5 A, Fig. 6 A, figure 7A, Fig. 8 A cross-sectional view along X-X' directions, Fig. 3 C, Fig. 4 C, Fig. 5 C, Fig. 6 C, Fig. 7 C, Fig. 8 C are difference corresponding diagrams 3A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A, Fig. 8 A cross-sectional view along Y-Y' directions, wherein, X-X' directions are nano wire Bearing of trend, Y-Y' be vertical nano-wire direction.
Reference picture 3A, Fig. 3 B, Fig. 3 C, Fig. 4 A, Fig. 4 B, Fig. 4 C, and reference picture 2 is combined, performing step S21, there is provided substrate 300, insulating barrier 302, the nano wire 301 on insulating barrier 302 are formed with substrate 300.
In a particular embodiment, the method for forming nano wire 301, including：Reference picture 3A, Fig. 3 B, Fig. 3 C there is provided substrate For silicon-on-insulator（SOI）Substrate, the SOI substrate includes bottom silicon layer, the insulating barrier 302 on bottom silicon layer, positioned at exhausted Top silicon layer 321 in edge layer 302, wherein, bottom silicon layer is the substrate 300 of the present embodiment, and the material of insulating barrier 302 is oxidation Silicon, the material of top silicon layer 321 can be silicon, germanium, germanium silicon（SiGe）, GaAs（GaAs）, indium arsenide（InAs）Or other are partly Conductor material；Then, with reference to reference picture 4A, Fig. 4 B, Fig. 4 C, plasma dry etch method or other etching methods, figure are used Change the top silicon layer 321 formation nano wire 301.Size to nano wire 301 can be selected as needed, nano wire 301 Size do not constitute the limitation to specific protection domain of the invention.
Reference picture 4A, Fig. 4 B, Fig. 4 C, Fig. 5 A, Fig. 5 B, Fig. 5 C, defines the partial-length nanometer between the two ends of nano wire 301 Xian Weizhong areas 310.The size in middle area 310 can be selected as needed, not constitute the limit to specific protection domain of the invention System.With reference to reference picture 2, step S22 is performed, the insulating barrier formation vacancy section 303 of the segment thickness of area 310 times in removal.
In the present embodiment, with reference to the forming method introduction with reference to nano wire 301 above, after nano wire 301 is formed, go Except the insulating barrier formation vacancy section 303 of middle 310 times segment thicknesses in area.Specifically, it is initially formed patterned mask layer（It is not shown）, Patterned mask layer defines the position in middle area 310；Using patterned mask layer as mask, area in being removed using wet etching method The insulating barrier of 310 times segment thicknesses, vacancy section 303 is formed under middle area 310；Finally, patterned mask layer is removed.Specific In embodiment, area 310 during patterned mask layer not only exposes also exposes the both sides one fixed width of middle area 310 in X-X' directions Insulating layer region, forms reserved window, corrosive agent passes through this to cause the insulating layer region of the etchant one fixed width Reserved window is gone successively in the insulating barrier under middle area 310.Therefore, on X-X' directions, the width of vacancy section 303 is more than middle area 310 width.In a particular embodiment, it is contemplated that the material of insulating barrier is mainly silica, is used during wet etching Etching agent be buffered oxide etch solution（Buffer oxide etchant, BOE）.Buffered oxide etch solution is by hydrogen fluorine Acid（HF）And ammonium fluoride（NH4F）The etching aqueous solution being made into by a certain percentage.Known join can be used in wherein HF and NH4F ratio Number, will not be repeated here.In addition to buffered oxide etch solution, dilute hydrofluoric acid solution can also be used, can effectively be gone Except segment thickness insulating barrier.
Reference picture 5A, Fig. 5 B, Fig. 5 C, Fig. 6 A, Fig. 6 B, Fig. 6 C, and reference picture 2 is combined, step S23 is performed, is engraved in formation Behind dead zone 303, first kind impurity doping is carried out to area 310 in area in partial-length or whole, base 330 is formed.Need It is bright, first kind impurity doping is carried out to area 310 in area in partial-length or whole, can be to whole along Y-Y' directions The middle area 310 of length carries out first kind impurity doping, or to carrying out first along the middle area 310 of Y-Y' directions partial-length Type dopant is adulterated, and its final purpose is base 330 to be formed.Therefore, the size of base 330 does not constitute specific to the present invention The limitation of protection domain.In the present embodiment, for the progress first kind impurity doping of area in partial-length 310.
In a particular embodiment, the type of first kind impurity is relevant with the type of bipolar transistor to be formed.If treating The bipolar transistor of formation is npn type bipolar transistor, then first kind impurity is p-type ion, such as boron（B）Ion, formation Base 330 is p-well region；If bipolar transistor to be formed is positive-negative-positive bipolar transistor, first kind impurity is N-type ion, Such as phosphorus（P）Or arsenic（As）Ion, the base 330 of formation is N well regions.
In a particular embodiment, the method being doped to area 310 in area in partial-length or whole, including：Form figure The mask layer of shape, the patterned photo mask layer defines the position in area 310 in area in the partial-length or whole；With the figure The mask layer of change is mask, and the ion implanting of first kind impurity is carried out to area 310 in area in the partial-length or whole；Remove Patterned mask layer.Use ion implantation, it is possible to achieve accurate, Uniform Doped.To the doping concentration of first kind impurity Scope, can refer to the well region doping concentration scope of the bipolar transistor of prior art, will not be repeated here.
In a particular embodiment, reference picture 6A, Fig. 6 B, Fig. 6 C, Fig. 7 A, Fig. 7 B, Fig. 7 C, and reference picture 2 is combined, perform step Rapid S24, after base 330 is formed, carries out Second Type impurity doping to the nano wire of the both sides of base 330, forms collecting zone 331st, launch site 332.In the present embodiment, collecting zone 331 include it is remaining in area 310, but collecting zone 331 and launch site 332 Position does not constitute the limitation to technical solution of the present invention, and the nanowire portion of the side in area 310 can be with shape in correspondence is remaining Into launch site, the nanowire portion formation collecting zone of the opposite side of base 330 is also feasible, can be selected as needed.Wherein, The type of the type of one type dopant and Second Type impurity in the contact position of base 330 and collecting zone 331 on the contrary, so form Current collection PN junction, transmitting PN junction is formed in the contact position of base 330 and launch site 332.
In a particular embodiment, if first kind impurity is p-type ion, Second Type impurity is N-type ion, base 330 be p-well region, and collecting zone 331 and launch site 332 are N well regions, and the bipolar transistor of formation is npn type bipolar transistor；If the One type dopant is N-type ion, then Second Type impurity is p-type ion, and base 330 is N well regions, collecting zone 331 and launch site 332 be p-well region, and the bipolar transistor of formation is positive-negative-positive bipolar transistor.
In a particular embodiment, the method to the nano wire progress Second Type impurity doping of the both sides of base 330 includes：Shape Into patterned mask layer, patterned mask layer defines the position of the nano wire of the both sides of base 330；With the patterned mask Layer is mask, and the ion implanting of Second Type impurity is carried out to the nano wire of the both sides of base 330；Remove the patterned mask Layer.
In other embodiments, the step of the step of forming base 330 is with forming collecting zone 331, launch site 332 order can To replace, you can the step of first to carry out being formed collecting zone 331, launch site 332, followed by base 330 is formed, this is also in this hair Within bright protection domain.
In a particular embodiment, reference picture 8A, Fig. 8 B, Fig. 8 C, are forming base 330, collecting zone 331 and launch site 332 Afterwards, can then thermal oxide nano wire, form the silicon oxide layer 304 for surrounding nano wire.It is, base 330, collecting zone 331 Silicon layer 304 is oxidized with launch site 332 to be surrounded, silicon oxide layer 304 can form a little extension into vacancy section 303.Due to Nano wire is carried out during the doping of first kind impurity and Second Type foreign ion injection, nanowire surface can be caused to damage Wound so that nanowire surface becomes out-of-flatness.In thermal oxidation process, nanowire surface can obtain oxidation and repair so that nanometer The surface of line becomes smooth, and the nanometer line profile ultimately formed is near cylindrical.On the other hand, thermal oxidation process can be activated Second Type impurity doping in first kind impurity, collecting zone 331 and launch site 332 in base 330.So, can be with shape Into the bipolar transistor with better quality.
In a particular embodiment, reference picture Figure 12, and reference picture 2 is combined, step S25 is performed, base 330, collection is being formed Behind electric area 331 and launch site 332, in addition to：Interlayer dielectric layer 305 is formed, interlayer dielectric layer 305 covers remaining insulating barrier 302 With nano wire, filling vacancy section 303.
In a particular embodiment,, can be to segment set before interlayer dielectric layer 305 is formed with reference to reference picture 8C and Fig. 9 Electric area 331 and launch site 332 carry out the ion implanting of Second Type impurity, form the He of colelctor electrode 351 being located in collecting zone 331 Emitter stage 352 in launch site 332；Then, reference picture 10, the ion of first kind impurity is carried out to part base 330 Injection, forms the base stage 350 being located in base 330.Fig. 9 is that the ion that whole launch sites 332 are carried out with Second Type impurity is noted Enter, be also feasible.The base stage 350 of first kind impurity doping is formed, the conductive plunger and base on base 330 can be reduced Connection resistance between 330.The colelctor electrode 351 and emitter stage 352 of Second Type impurity doping are formed, collecting zone can be reduced Between conductive plunger and collecting zone 331 on 331, the conductive plunger on launch site 332 and the connection between launch site 332 electricity Resistance, and then lift the performance of bipolar transistor.In a particular embodiment, the step of forming base stage 350, formation colelctor electrode 351 and The order of the step of emitter stage 352 is unrestricted, is included in the scope of the present invention.
In a particular embodiment, the step of forming base stage 350, colelctor electrode 351 and emitter stage 352 enters with foregoing to nano wire The step of row thermal oxide forms silicon oxide layer 304 can replace, that is to say, that can form base 330, collecting zone 331 Behind launch site 332, base stage 350, colelctor electrode 351 and emitter stage 352 are initially formed；Followed by thermal oxide nano wire and form encirclement The silicon oxide layer 304 of nano wire or silicon oxide layer 304 is initially formed, is subsequently formed base stage 350, colelctor electrode 351 and transmitting Pole 352.In the present embodiment, first thermal oxide nano wire and formed surround nano wire silicon oxide layer 304, re-form base stage 350, Colelctor electrode 351 and emitter stage 352.Silicon oxide layer 304 can play the work of the filtering to first kind impurity and Second Type impurity With, it is to avoid ion implantation process causes damage to nano wire.
In a particular embodiment, with reference to reference picture 11, after base stage 350, colelctor electrode 351 and emitter stage 352 is formed, formed Before interlayer dielectric layer 305, metal silicide 306 is formed on base stage 350, colelctor electrode 351 and emitter stage 352, it is specific to can be used Self-aligned silicide formation process.In a particular embodiment, the metal silicide 306 of formation is not only located at base stage 350, colelctor electrode 351 and emitter stage 352 on, also surround base stage 350, the side of colelctor electrode 351 and emitter stage 352, but in the section shown in Figure 11 It is invisible in structural representation.Afterwards, base 330, collecting zone 331 and conductive plunger and metal silicide on launch site 332 306 connections.Metal silicide 306 can be reduced further between the conductive plunger on base 330 and base stage 350, collecting zone 331 Between upper conductive plunger and colelctor electrode 351, the conductive plunger on launch site 332 and the contact resistance between emitter stage 352, with shape Into good Ohmic contact.
With continued reference to Figure 12, and reference picture 2 is combined, perform step S26, connection base is formed in interlayer dielectric layer 305 330 the first connector 340, the second connector 341 for connecting collecting zone 331, the 3rd connector 342 for connecting launch site 332.First inserts The 340, second connector 341 and the 3rd connector 342 are filled in by base 330, collecting zone 331 and launch site 332 and other semiconductor devices Connect.Reference picture 12, when being formed with silicon oxide layer 304 in nanowire surface, interlayer dielectric layer 305 surrounds the silica Layer 304, the first connector 340, the second connector 341, the 3rd connector 342 pass through the silicon oxide layer 304.In the present embodiment, in base Base stage 350 is formed with area 330, colelctor electrode 351 is formed with collecting zone 331, is formed with emitter stage in launch site 332 When 352, the first connector 340 is connected with base stage 350, and the second connector 341 is connected with colelctor electrode 351, the 3rd connector 342 and emitter stage 352 connections.When being formed with metal silicide 306 on base stage 350, colelctor electrode 351 and emitter stage 352, the first connector 340, Second connector 341, the 3rd connector 342 are connected with metal silicide 306, can form good Ohmic contact.
In a particular embodiment, the step of forming the first connector 340, the second connector 341 and the 3rd connector 342 is this area Technology known to technical staff, will not be repeated here.
Second embodiment
Reference picture 13, Figure 14, perform the step S21 shown in Fig. 2, insulating barrier 502 are formed with substrate 500, positioned at exhausted Nano wire 501 in edge layer 502.
In the present embodiment, reference picture 13 is there is provided SOI substrate, and SOI substrate includes bottom silicon layer, on bottom silicon layer Insulating barrier 502, the top silicon layer 521 on insulating barrier 502, substrate 500 be bottom silicon layer；Graphical top silicon layer 521 Nano wire 501 is formed, specific method refers to the nanometer line forming method of first embodiment.
With reference to reference picture 14, Figure 15, it is middle area 510 to define the partial-length nano wire between the two ends of nano wire 501.Holding Step S22 shown in row Fig. 2, in removal before the insulating barrier formation vacancy section 503 of the segment thickness of area 510 times, with reference to receiving above The forming step of rice noodles 501, reference picture 14, in graphical top silicon layer formation nano wire 501, also patterned insulator layer 502, The segment thickness insulating barrier not covered by nano wire 501 is removed, the insulation undercutting knot of insulating barrier 502 is formed under nano wire 501 Structure 502'；Then, the insulating barrier formation vacancy section 503 of the segment thickness of area 510 times, that is, area 510 in removing in reference picture 15, removal Under insulation undercut construction, it is remaining in insulation undercut construction under the both sides nano wire of area 510, residue insulation undercut construction 502' it Between be vacancy section 503.
In a particular embodiment, the method for removing the segment thickness insulating barrier not covered by nano wire 501 is anisotropy Wet etching method.Because anisotropic wet etch can produce undercutting（undercut）Effect, can be surplus using this effect The regular insulation undercut construction 502' being located under nano wire is formed on remaining insulating barrier 502.It is this to form the undercut construction that insulate The technology that method is well known to those skilled in the art, will not be repeated here.In a particular embodiment, in removal under area 510 The method for the undercut construction that insulate is wet etching method, and the etching agent used can include buffered oxide etch solution or dilute hydrogen fluorine Acid solution.
Reference picture 16, performs the step S23 shown in Fig. 2, after vacancy section 503 is formed, to area in partial-length or whole Middle area 510 carries out first kind impurity doping, forms base 530.The step of forming base 530 may be referred to first embodiment Base formation process, both are identical.
Reference picture 17, performs the step S24 shown in Fig. 2, and after base 530 is formed, the nano wire of the both sides of base 530 is entered Row Second Type impurity adulterates, and forms collecting zone 531 and launch site 532, type and the Second Type impurity of first kind impurity Type it is opposite.The step of forming collecting zone 531 and launch site 532 can refer to the collecting zone of first embodiment and the shape of launch site Into technique.
In a particular embodiment, the type of first kind impurity and the type of Second Type impurity and bipolar crystalline substance to be formed The type of body pipe is relevant, specifically refers to the related introduction of first embodiment.
In a particular embodiment, the order of the forming step of the forming step of base 530, collecting zone 531 and launch site 532 It can replace.
In a particular embodiment, reference picture 18A, after base 530, collecting zone 531 and launch site 532 is formed, to nanometer Line carries out thermal oxide and forms the silicon oxide layer 504 for surrounding nano wire, and thermal oxidation causes the profile of nano wire to be approximate circle Cylindricality.Concrete technology can refer to the related introduction of the silicon oxide layer of first embodiment.
In a particular embodiment, reference picture 18A, Figure 18 B, plane 505 is perpendicular to the remaining surface of insulating barrier 502 and passed through The plane of nano wire axis, Figure 18 B are the cross-sectional view in Figure 18 A direction of plane 505, after step of thermal oxidation, First kind impurity is carried out in part base 530 to adulterate to form base stage 550；Then, part collecting zone 531 and part are launched Second Type impurity doping is carried out in area 532, colelctor electrode 551 is formed in collecting zone 531, transmitting is formed in launch site 532 Pole 552.Specifically refer to base stage, the related introduction of collector and emitter formation process of first embodiment.
In a particular embodiment, after base 530, collecting zone 551 and launch site 552 is formed, in base 530, collecting zone 551 and launch site 552 on form conductive plunger, concrete technology can refer to the first connector of first embodiment, the second connector, the 3rd The formation process introduction of connector.
In the first embodiment and the second embodiment, it is proposed that formed using the field-effect transistor with all-around-gate pole Technique forms a kind of technique of bipolar transistor, and this provides new approaches, new solution for the formation process of bipolar transistor. Moreover, bipolar transistor of the bipolar transistor compared to prior art obtained using technical scheme, in performance Maintain better quality.
3rd embodiment
First embodiment and second embodiment are field-effect transistor formation process of the exclusive use with all-around-gate pole The technique for forming bipolar transistor, this is also that bipolar transistor formation process and the field effect transistor with all-around-gate pole are tubular Compatibility into technique provides possibility.That is, being walked forming the field-effect transistor technique with all-around-gate pole In rapid, the simultaneous processing step that bipolar transistor is formed with completion.Therefore, in the present embodiment, the step of forming bipolar transistor To colonize among the forming step of the field-effect transistor with all-around-gate pole.
Below in conjunction with accompanying drawing, the field-effect transistor and bipolar transistor on the same substrate with all-around-gate pole are introduced Pipe.Figure 19 A, Figure 20 A, Figure 21 A, Figure 22 A, Figure 23 A, Figure 24 A, Figure 25 A are overlooking the structure diagram, Figure 19 B, Figure 20 B, figure 21B, Figure 22 B, Figure 23 B, Figure 24 B, Figure 25 B are difference corresponding diagram 19A, Figure 20 A, Figure 21 A, Figure 22 A, Figure 23 A, Figure 24 A, figure The cross-sectional view in 25A X-X' directions, Figure 25 C are the cross-section structures in corresponding diagram 25A the second area II Y-Y' directions Schematic diagram, Figure 25 D are corresponding diagram 25A, Figure 25 B, Figure 25 C dimensional structure diagram, wherein, X-X' directions are vertical nano-wire Direction.Hereafter by by the way that field-effect transistor formation process step and bipolar transistor with all-around-gate pole is described in detail The compatibility of formation process step, to illustrate technical scheme.
（1）Reference picture 19A, Figure 19 B, substrate 600 includes the first area I and the second area II.In the present embodiment, with first The field-effect transistor with all-around-gate pole is formed in area I and is explained in the second area II exemplified by formation bipolar transistor State.
The step S21 shown in Fig. 2 is performed, insulating barrier 601 is formed with substrate 600, position is formed with insulating barrier 601 Nano wire 602 in the first area I, the nano wire 603 in area II.It is situated between with reference to the nano wire formation process of first embodiment Continue, the nano wire 602 of the present embodiment and the formation process of nano wire 603 are：Silicon-on-insulator substrate, the silicon-on-insulator are provided Substrate includes bottom silicon layer, the insulating barrier 601 on bottom silicon layer and the top silicon layer on insulating barrier 601（Do not show Go out）, bottom silicon layer is the substrate 600 in Figure 19 A, Figure 19 B；Then, graphical top silicon layer, nanometer is formed in the first area I Line 602, forms nano wire 603 in the second area II.That is, the nano wire 603 of bipolar transistor is with having all-around-gate The nano wire 602 of the field-effect transistor of pole can be formed in same step.With independent graphical top silicon layer formation field effect The nano wire of transistor is answered to be compared with the nano wire of independent graphical top silicon layer formation bipolar transistor, which reduce graphical Number of times, accordingly save the mask material in patterning process, reduce production cost.
（2）With reference to reference picture 20A, Figure 20 B, during the partial-length nano wire region between definition nano wire 602 two ends is Area 621；It is middle area 631 to define the partial-length nano wire region between the two ends of nano wire 603.Perform the step shown in Fig. 2 The insulating barrier of the segment thickness of area 621 times forms vacancy section 604, forms vacancy section 605 under middle area 631 in S22, removal.Hollow out Area 604, the formation process of vacancy section 605 may be referred to first embodiment, the vacancy section forming step of second embodiment, that is, Say, the shape of vacancy section 604 and/or vacancy section 605 can be the vacancy section shape of first embodiment or engraving for second embodiment Air region shape.If the shape of vacancy section 604 and vacancy section 605 is the vacancy section shape of first embodiment or is the second implementation Vacancy section 605 in the vacancy section shape of example, bipolar transistor forming process and the field-effect transistor with all-around-gate pole Vacancy section 604 can be formed in same step, specifically refer to the introduction of first embodiment and second embodiment.In this reality Apply in example, the shape of vacancy section 604 and vacancy section 605 is by taking the shape of the vacancy section of first embodiment as an example.Control first is implemented The vacancy section forming step of example and second embodiment, at the same formed vacancy section 604, the technique of vacancy section 605 reduce it is patterned Number of times, saves mask material.
（3）With reference to reference picture 19A, Figure 19 B, Figure 20 A, Figure 20 B, Figure 21 A, Figure 21 B, step S23 is performed, in the second area II In, progress first kind impurity adulterates to form base 606 in the middle area 631 of nano wire 603.The present embodiment is to area in whole 631 are doped.When carrying out the doping of first kind impurity to middle area 631, in the first area I, also carried out in nano wire 602 First kind impurity adulterates to form well region 607.Positioned at the middle position of area 621 the part of well region 607 as field-effect transistor ditch Road area.Base 606, well region 607 can be formed in same processing step, that is to say, that the field-effect on same substrate The channel region doping of transistor and the base of bipolar transistor can be formed in same step.Specifically, base 606, well region 607 can simultaneously form after vacancy section 604 and vacancy section 605 is formed.Can be according to treating shape to the type of first kind impurity Into field-effect transistor, bipolar transistor type determine：If the type of field-effect transistor and bipolar transistor is that N-type is brilliant Body pipe, then first kind impurity is N-type ion；If the type of field-effect transistor and bipolar transistor is P-type transistor, the One type dopant is p-type ion.
With reference to reference picture 21A, Figure 21 B, Figure 22 A, Figure 22 B, step S24 is performed, before base 606 is formed or base is formed After 606, Second Type impurity doping is carried out in the nanowire portion of the both sides of base 606, in the nano wire of the both sides of base 606 Form collecting zone 608 and launch site 609 respectively, the type of Second Type impurity is opposite with the type of first kind impurity. The concrete technology is referred to the collecting zone of first embodiment and the related introduction of launch site formation process.
（4）In a particular embodiment, with reference to reference picture 22A, Figure 22 B, Figure 23 A, Figure 23 B, when with all-around-gate pole After the formation of well region 607 of field-effect transistor, the nano wire that can be then pointed to the first area I carries out thermal oxidation, its purpose It is：The surface damage that nano wire is subject in first kind impurity injection process is repaired, and activates the first kind in well region 607 Type impurity.It is corresponding, after base 606, collecting zone 608 and launch site 609 formation of bipolar transistor, it can also be pointed to the Two area II nano wire carries out thermal oxidation, reaches that the first kind repaired in impaired nano wire, activation base 606 is miscellaneous Second Type impurity in matter, activation collecting zone 608 and launch site 609.Therefore, it is pointed to the first area I nano wire and is located at The thermal oxidation of second area II nano wire can be completed in same processing step, and then form the bag positioned at the first area I The silicon oxide layer 610 of nano wire, the silicon oxide layer 611 for surrounding nano wire positioned at the second area II are enclosed, thermal oxidation to receive The profile of rice noodles is near cylindrical.
In a particular embodiment, with reference to reference picture 24A, Figure 24 B, in the first area I, heat is being carried out to well region 607 After oxidation processes, area 621 in being developed across silicon oxide layer 610 and surrounding（Reference picture 20A, Figure 20 B）The silicon oxide layer of position Grid 612, the side wall 613 positioned at the both sides of grid 612.The filling of grid 612 is positioned at the first area I vacancy section 604, and grid 612 is wrapped The part of silicon oxide layer 610 enclosed is as gate dielectric layer, and the nanowire portion that grid 612 is surrounded is channel region, is mixed in channel region It is miscellaneous to have first kind impurity.The technique that the technique of grid 612 is well known to those skilled in the art is formed, be will not be repeated here. In addition, in a particular embodiment, with reference to reference picture 25A, after grid 612 and side wall 613 is formed, can then remove channel region two Side encirclement nano wire the part of silicon oxide layer 610, be follow-up source electrode, drain electrode formation prepare.
（5）In a particular embodiment, it is corresponding diagram 25A with reference to reference picture 25A, Figure 25 B, Figure 25 C, Figure 25 D, Y-Y' directions The second area II nano wire bearing of trend, in the first area I, grid 612 and grid 612 both sides when field-effect transistor To be then that mask carries out Second Type impurity to the nanowire portion of the both sides of grid 612 with side wall 613 after the formation of side wall 613 Heavy doping, forms source electrode 614 and drain electrode 615, the type of Second Type impurity and the type of first kind impurity it is certain on the contrary, The field-effect transistor with all-around-gate pole 612 is formed so in the first area I.
In a particular embodiment, it is follow-up conductive plunger and base, the collection on base, collecting zone and launch site of reduction Contact resistance between electric area and launch site, in the second area II, with reference to reference picture 25C, formed bipolar transistor base, After collecting zone and launch site, or after thermal oxidation is carried out to nano wire, part collecting zone and part launch site are carried out Second Type impurity adulterates, and forms colelctor electrode 616 in collecting zone respectively and emitter stage 617 is formed in launch site.In this reality Apply in example, be also feasible to carry out Second Type impurity doping to whole collecting zones and whole launch sites.Therefore, carrying out The heavy doping of Second Type impurity is formed during source electrode 614 and drain electrode 615, can carry out the to part collecting zone and launch site simultaneously Two type dopants adulterate to form colelctor electrode 616 and emitter stage 617.That is, source electrode 614 and the drain electrode of field-effect transistor 615 can form with the colelctor electrode 616 of bipolar transistor and emitter stage 617 in same processing step.With reference to real with reference to first The forming method introduction of the collector and emitter of example, the source electrode of the field-effect transistor of the present embodiment and drain electrode are applied, it is and bipolar The collector and emitter of transistor is formed in same step, is reduced patterned number of times, is saved process costs.Separately Outside, mutually independently, the step of base stage 618 are formed in base can form preceding completion in colelctor electrode 616 and emitter stage 617, It can be completed after colelctor electrode 616 and the formation of emitter stage 617, specifically refer to the related introduction of first embodiment.
（6）In a particular embodiment, after the source electrode 614 of field-effect transistor and drain electrode 615 is formed, connection source electrode is formed 614 and drain electrode 615 conductive plunger.After bipolar transistor is formed, form connection base, collecting zone and the conduction of launch site and insert Plug.With reference to the first connector of first embodiment, the second connector, the process introduction introduction of the 3rd connector and the field-effect of prior art The conductive plunger process introduction of transistor, connection base, collecting zone and the conductive plunger of launch site are with being connected source electrode 614 and drain electrode 615 conductive plunger with the step of can be formed in same processing step.
In summary, present embodiments provide on the same substrate formed with all-around-gate pole field-effect transistor and The technique of bipolar transistor, at least includes（1）、（2）、（3）、（4）、（5）、（6）Compatible processing step.This not only proves to make Scheme with the field-effect transistor formation process formation bipolar transistor with all-around-gate pole is great feasibility, is also demonstrate,proved The step of bright formation bipolar transistor, can be colonized among the forming step of the field-effect transistor with all-around-gate pole.Two All multiple compatibility steps can save graphical number of times between person, reduce production cost.
The present invention also provides a kind of new bipolar transistor, and the forming method of the above-mentioned bipolar transistor of correspondence will divide below Three embodiments introduce the bipolar transistor.
First embodiment
Reference picture 8A, Fig. 8 B, Fig. 8 C, the bipolar transistor of the present embodiment includes：
Insulating barrier 302 on substrate 300, the nano wire 301 on insulating barrier 302（Reference picture 4A）, definition receives Partial-length nano wire between the two ends of rice noodles 301 is middle area；
Under the middle area 310, the vacancy section 303 in insulating barrier 302；
In partial-length in area or whole in area doped with first kind impurity, doped with the middle area of first kind impurity Part is base 330；
Doped with Second Type impurity in the nano wire of the both sides of base 330, positioned at base side, doped with Second Type The nanowire portion of impurity be collecting zone 331, positioned at base opposite side, doped with Second Type impurity nanowire portion for hair Area 332 is penetrated, the type of first kind impurity is opposite with the type of Second Type impurity.
In the present embodiment, vacancy section 303 is located in the insulating barrier under nano wire.Due to forming the mistake of vacancy section 303 , it is necessary to which nano wire both sides reserved window in X-X' directions, the reserved window is used for etching agent and enters exhausted under nano wire in journey In edge layer, the final width for causing vacancy section 303 in X-X' directions is more than width of the nano wire in X-X' directions.
In a particular embodiment, the type of first kind impurity is p-type ion, then the type of Second Type impurity is N-type Ion；Or, when first kind impurity is N-type ion, then Second Type impurity is p-type ion.So, in base 330 and collection The contact position in electric area 331 is formed with current collection PN junction, and transmitting PN junction is formed with the contact position of base 330 and launch site 332.
In a particular embodiment, the bipolar transistor also includes：Positioned at nanowire surface and surround the oxygen of whole nano wire SiClx layer 304.The silicon oxide layer 304 is formed using thermal oxidation technology so that the profile of nano wire is near cylindrical, lifting The performance of bipolar transistor.
In a particular embodiment, with reference to reference picture 12, the bipolar transistor also includes：Interlayer dielectric layer 305, inter-level dielectric Layer 305 covers insulating barrier 302 and nano wire, the full vacancy section 303 of filling, when the oxidation that nano wire is surrounded in nanowire surface formation During silicon layer 304, interlayer dielectric layer 305 surrounds silicon oxide layer 304；Connect base 330 first in interlayer dielectric layer 305 Connector 340, the second connector 341 for connecting collecting zone 331, the 3rd connector 342 for connecting launch site 332.First connector 340, Two connectors 341, the 3rd connector 342 connect base 330, collecting zone 331, launch site 332 and other semiconductor devices.
In a particular embodiment, the bipolar transistor also includes：First kind impurity is carried out to part base to adulterate to be formed Base stage 350；Adulterate the colelctor electrode 351 to be formed to part collecting zone progress Second Type impurity；The is carried out to part launch site Two type dopants are adulterated the emitter stage 352 to be formed.Wherein, the first connector 340 is connected with base stage 350, the second connector 341 and current collection Pole 351 is connected, and the 3rd connector 342 is connected with emitter stage 352.Base stage 350 is reduced between the first connector 340 and base 330 Resistance is connected, colelctor electrode 351 reduces the connection resistance between the second connector 341 and collecting zone 331, and emitter stage 352 is reduced Connection resistance between 3rd connector 342 and launch site 332.
In a particular embodiment, the bipolar transistor also includes：On base stage 330, colelctor electrode 331 and emitter stage 332 Metal silicide 306, the first connector 340, the second connector 341 and the 3rd connector 342 are connected with metal silicide 306.Metal Silicide 306 can be reduced further between the first connector 340 and base stage 350, between the second connector 341 and colelctor electrode 351, Contact resistance between three connectors 342 and emitter stage 352.
Second embodiment
In the present embodiment, the structure of vacancy section is different from the hollow out plot structure of first embodiment.Reference picture 15, Figure 18 A, Insulating barrier under Figure 18 B, the middle both sides nano wire of area 510 is higher than the insulating barrier 502 not covered by nano wire.Wherein middle 510 liang of area Insulation layer segment under the nano wire of side is considered as the insulation undercut construction 502' of insulating barrier, and insulation undercut construction 502' is insulating barrier 502 part, the vacancy section 503 of the present embodiment is located between insulation undercut construction 502'.
In the present embodiment, the vacancy section 503 and first between insulation undercut construction 502', insulation undercut construction 502' is real Apply example different, the other structures such as nano wire of bipolar transistor are identical with the corresponding construction of first embodiment, corresponding reference can be made.
Reference picture 25A, Figure 25 B, Figure 25 C, Figure 25 D, the present invention also provides a kind of new semiconductor devices, the semiconductor device Part includes：Field-effect transistor with all-around-gate pole 612 on same substrate, in the first area I and positioned at Bipolar transistor in two area II.The grid 612 of field-effect transistor is across the nano wire positioned at the first area I and surrounds the nanometer Line, side wall 613 is formed with the both sides of grid 612.The silica for surrounding nano wire is formed between the nano wire and grid 612 Layer 610, the silicon oxide layer 610 is gate dielectric layer, and the nanowire portion that the silicon oxide layer 610 is surrounded is channel region.612 liang of grid Side is source electrode 614, drain electrode 615.The structure of bipolar transistor can be the bipolar transistor of first embodiment or second embodiment Structure, can make corresponding reference, will not be repeated here.
Although the present invention is disclosed as above with preferred embodiment, but is not limited to the present invention.It is any to be familiar with ability The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above Appearance makes many possible variations and modification to technical solution of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore, Every content without departing from technical solution of the present invention, the technical spirit according to the present invention is to made for any of the above embodiments any simple Modification, equivalent variations and modification, in the range of still falling within technical solution of the present invention protection.

Claims (19)

1. a kind of forming method of bipolar transistor, it is characterised in that including：
Substrate is provided, insulating barrier, the nano wire on the insulating barrier are formed with over the substrate, the nano wire is defined Partial-length nano wire between two ends is middle area；
Remove the insulating barrier formation vacancy section of segment thickness under the middle area, after the vacancy section is formed, the nano wire Two ends are located on the insulating barrier, and the two ends of the nano wire are in contact with the insulating barrier；
After the vacancy section is formed, first kind impurity doping is carried out to area in area in partial-length or whole, base is formed；
After base is formed, or before base is formed, Second Type impurity doping is carried out to the nano wire of base both sides, formed Collecting zone and launch site, the type of the first kind impurity are opposite with the type of the Second Type impurity.
2. forming method as claimed in claim 1, it is characterised in that in the removal under area the insulating barrier of segment thickness side Method is：Using wet etching method, etching removes the insulating barrier of segment thickness under the middle area.
3. forming method as claimed in claim 1, it is characterised in that the insulating barrier shape of segment thickness in the case where removing the middle area Into before vacancy section, in addition to：Remove the segment thickness insulating barrier not covered by the nano wire.
4. forming method as claimed in claim 3, it is characterised in that the segment thickness that the removal is not covered by nano wire is exhausted The method of edge layer is anisotropic wet etch method.
5. forming method as claimed in claim 1, it is characterised in that described that the is carried out to area in area in partial-length or whole The method of one type dopant doping, including：
Form patterned mask layer, the patterned mask layer defines the position in area in area in the partial-length or whole Put；
Using the patterned mask layer as mask, first kind impurity is carried out to area in area in the partial-length or whole Ion implanting；
Remove the patterned mask layer.
6. forming method as claimed in claim 1, it is characterised in that the nano wire to base both sides carries out Second Type The method of impurity doping, including：
Patterned mask layer is formed, the patterned mask layer defines the position of the nano wire of base both sides；
Using the patterned mask layer as mask, the ion implanting of Second Type impurity is carried out to the nano wire of base both sides；
Remove the patterned mask layer.
7. forming method as claimed in claim 1, it is characterised in that the first kind impurity is p-type ion, Second Type Impurity is N-type ion；Or, the first kind impurity is N-type ion, and Second Type impurity is p-type ion.
8. forming method as claimed in claim 1, it is characterised in that after the base, collecting zone and launch site is formed, also Including：The silicon oxide layer of nano wire is surrounded in nano wire formation described in thermal oxide.
9. forming method as claimed in claim 1, it is characterised in that the substrate is silicon-on-insulator substrate, the insulation Silicon substrate includes bottom silicon layer, the insulating barrier on the bottom silicon layer and the top silicon on the insulating barrier on body Layer；
The method for forming the nano wire is that the graphical top silicon layer forms nano wire.
10. forming method as claimed in claim 1, it is characterised in that after the base, collecting zone and launch site is formed, Also include：
Form interlayer dielectric layer, the remaining insulating barrier of interlayer dielectric layer covering and nano wire, the filling vacancy section；
The first connector, the second connector of the connection collecting zone of the connection base are formed in the interlayer dielectric layer, even Connect the 3rd connector of the launch site.
11. forming method as claimed in claim 10, it is characterised in that before the interlayer dielectric layer is formed, to part Base carries out first kind impurity doping, forms the base stage being located in the base；
After base stage is formed, or formed before base stage, Second Type impurity doping, shape are carried out to part collecting zone and part launch site Into the colelctor electrode in the collecting zone, the emitter stage in the launch site；
First connector is connected with base stage, and second connector is connected with colelctor electrode, and the 3rd connector is connected with emitter stage.
12. forming method as claimed in claim 11, it is characterised in that the substrate includes the firstth area and the secondth area, in institute State and the field-effect transistor with all-around-gate pole is formed in the firstth area, bipolar transistor is formed in secondth area；
The nano wire of the nano wire and the field-effect transistor is formed in same step；
The vacancy section and the vacancy section of the field-effect transistor are formed in same step；
The channel region of the base and the field-effect transistor is formed in same step；
The source electrode of the colelctor electrode, emitter stage and the field-effect transistor, drain electrode are formed in same step；
Conductive plunger on the source electrode of first connector, the second connector, the 3rd connector and the field-effect transistor, drain electrode exists Formed in same step.
13. a kind of bipolar transistor, it is characterised in that including：
Insulating barrier on substrate, the nano wire on the insulating barrier, define the part between the nano wire two ends Length nano wire is middle area；
Under the middle area, the vacancy section in insulating barrier, the two ends of the nano wire are located on the insulating barrier, and described receive The two ends of rice noodles are in contact with the insulating barrier；
In partial-length in area or whole in area doped with first kind impurity, the middle area doped with first kind impurity Part is base；
Doped with Second Type impurity in the nano wire of the base both sides, positioned at base side, miscellaneous doped with Second Type The nanowire portion of matter be collecting zone, positioned at base opposite side, doped with Second Type impurity nanowire portion be launch site, The type of the first kind impurity is opposite with the type of the Second Type impurity.
14. bipolar transistor as claimed in claim 13, it is characterised in that the insulation floor height under the nano wire of the Zhong Qu both sides In the insulating barrier not covered by the nano wire.
15. bipolar transistor as claimed in claim 13, it is characterised in that the first kind impurity is p-type ion, second Type dopant is N-type ion；Or, the first kind impurity is N-type ion, and Second Type impurity is p-type ion.
16. bipolar transistor as claimed in claim 13, it is characterised in that also include：Positioned at the nanowire surface and wrap The silicon oxide layer of nano wire is enclosed, the profile of the nano wire is cylinder.
17. bipolar transistor as claimed in claim 13, it is characterised in that also include：
Interlayer dielectric layer, the interlayer dielectric layer covers the insulating barrier and nano wire, fills the vacancy section；
First connector of the connection base in the interlayer dielectric layer, the second connector of the connection collecting zone, company Connect the 3rd connector of the launch site.
18. bipolar transistor as claimed in claim 17, it is characterised in that also include：
First kind impurity is carried out to part base to adulterate the base stage to be formed；
Adulterate the colelctor electrode to be formed to part collecting zone progress Second Type impurity；
Adulterate the emitter stage to be formed to part launch site progress Second Type impurity；
First connector is connected with base stage, and second connector is connected with colelctor electrode, and the 3rd connector is connected with emitter stage.
19. a kind of semiconductor devices, it is characterised in that including：
Field-effect transistor with all-around-gate pole；
Any described bipolar transistor of claim 13~18, the field-effect transistor is located at same with the bipolar transistor On one substrate.
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