CN104409487B - The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon and its manufacture method - Google Patents
The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon and its manufacture method Download PDFInfo
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- CN104409487B CN104409487B CN201410746320.1A CN201410746320A CN104409487B CN 104409487 B CN104409487 B CN 104409487B CN 201410746320 A CN201410746320 A CN 201410746320A CN 104409487 B CN104409487 B CN 104409487B
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- 238000009413 insulation Methods 0.000 title claims abstract description 120
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- 230000002708 enhancing effect Effects 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 230000005641 tunneling Effects 0.000 claims abstract description 81
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- 230000000694 effects Effects 0.000 claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims description 62
- 238000005530 etching Methods 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 12
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 3
- 239000012774 insulation material Substances 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 230000005669 field effect Effects 0.000 abstract description 5
- 230000009471 action Effects 0.000 abstract description 3
- 230000035945 sensitivity Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 35
- 238000005520 cutting process Methods 0.000 description 27
- 230000005684 electric field Effects 0.000 description 9
- 230000001681 protective effect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000037237 body shape Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004347 surface barrier Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract
The present invention relates to a kind of two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon; contrast is with size MOSFETs or tunneling field-effect transistor, by introducing the breakdown protection area of low impurity concentration in collector junction and emitter junction to be obviously improved pressure-resistant positive and reverse voltage endurance capability of the device under deep nanoscale；There is insulation tunneling structure simultaneously in base both sides, insulation tunneling effect is made under the control action of gate electrode while occurring in base both sides, the generation rate of tunnelling current is improved；Outstanding switching characteristic is realized using the correlation of tunneling insulation layer impedance and its fields inside Qianghian extremely sensitivity；Tunneling through signal enhancing by emitter stage realizes outstanding forward conduction characteristic；The invention also provides a kind of specific manufacture method for being applied to manufacture two-way breakdown protection double grid insulation tunnelling enhancing transistor on the body Silicon Wafer of low cost in addition.The transistor significantly improves the working characteristics of nanometer-grade IC unit, it is adaptable to popularization and application.
Description
Technical field：
Field is manufactured the present invention relates to super large-scale integration, is related to a kind of integrated suitable for high-performance superelevation integrated level
The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon and its manufacture method of circuit manufacture.
Background technology：
Currently, with the continuous lifting of integrated level, integrated circuit unit mos field effect transistor
(MOSFETs) precipitous mutation is formd within several nanometers between the source electrode and raceway groove of device or between drain electrode and raceway groove
PN junction, when drain-source voltage is larger, punch-through effect can occur for this precipitous abrupt PN junction, so that component failure, with device
The continuous reduction of part size, this punch-through effect becomes clear day by day.In addition, the continuous shortening of channel length result in MOSFETs devices
The increase of part subthreshold swing, therefore bring the serious deterioration of switching characteristic and the obvious increase of quiescent dissipation.Although passing through
Improving the mode of gate electrode structure can alleviate the degeneration of this device performance, but when device size is further reduced to 20
When nanometer is following, even with the gate electrode structure of optimization, the subthreshold swing of device similarly can be long with device channel
Degree further reduction and increase, so as to result in the deterioration again of device performance；
Tunneling field-effect transistor (TFETs), in contrast to MOSFETs devices, although its average subthreshold swing has been carried
Rise, but its forward conduction electric current is too small, although it is narrower by introducing the energy gaps such as compound semiconductor, SiGe or germanium
Material can increase tunnelling probability to lift transfer characteristic to be generated as the tunnelling part of tunneling field-effect transistor, but add work
Skill difficulty.In addition, being used as the insulating medium layer between grid and substrate using high dielectric constant insulating material, although can improve
Grid but can not inherently improve the tunnelling probability of silicon materials to the control ability of electric field distribution in channel, therefore for tunnelling
The transfer characteristic of field-effect transistor improves very limited.
The content of the invention：
Goal of the invention
To be obviously improved sub- 20 nanoscale devices breakdown characteristics on the premise of compatibility is existing based on bulk silicon technological technology；
It is obviously improved the switching characteristic of nanometer-grade IC basic unit device；Ensure that device has while lifting switch characteristic
Good forward current on state characteristic, the present invention provides a kind of body silicon suitable for high-performance superelevation integrated level IC manufacturing
Two-way breakdown protection double grid insulation tunnelling enhancing transistor and its manufacture method.
Technical scheme
The present invention is achieved through the following technical solutions：
The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon, using the body Silicon Wafer comprising monocrystalline substrate 1
It is used as the substrate of generating device；Launch site 3, base 4, collecting zone 5 and breakdown protection area 2 are located at the top of monocrystalline substrate 1；Base
Area 4 is located between launch site 3 and collecting zone 5, and breakdown protection area 2 is located at the both sides of base 4；Emitter stage 9 is located at the upper of launch site 3
Side；Colelctor electrode 10 is located at the top of collecting zone 5；Conductive layer 6, tunneling insulation layer 7 and gate electrode 8 are successively in the both sides shape of base 4
Into sandwich；Barrier insulating layer 11 and the monocrystalline beyond launch site 3, collecting zone 5, base 4 and the lower section of breakdown protection area 2
The upper surface portion of silicon substrate 1 contacts with each other.
To reach device function of the present invention, the present invention proposes the two-way breakdown protection double grid insulation tunnelling enhancing of body silicon
Transistor, its core texture is characterized as：
The impurity concentration in breakdown protection area 2 is less than 1016It is per cubic centimeter.
The impurity concentration of base 4 is not less than 1017Per cubic centimeter, the both sides of base 4 are in contact with conductive layer 6 and form ohm
Contact.
Between launch site 3 and base 4, there is opposite impurity type, and launch site 3 and transmitting between collecting zone 5 and base 4
Formed between pole 9 between Ohmic contact, collecting zone 5 and colelctor electrode 10 and form Ohmic contact.
Conductive layer 6 is formed at the both sides of base 4, and conductive layer 6 is that metal material either has identical impuritiess with base 4
Type and doping concentration be more than 1019Semi-conducting material per cubic centimeter.
Tunneling insulation layer 7 is the insulation material layer for producing tunnelling current, with two independent sectors, each section shape
Into the opposite side of the side that is in contact with base 4 in the both sides conductive layer 6 of base 4.
Gate electrode 8 is the electrode for controlling tunneling insulation layer 7 to produce tunneling effect, is the electricity that control device is switched on and off
Pole, is in contact with the opposite side of the side that is in contact with conductive layer 6 of two independent sectors of tunneling insulation layer 7.
Conductive layer 6, tunneling insulation layer 7 and gate electrode 8 pass through barrier insulating layer 11 and launch site 3, emitter stage 9, current collection
Area 5 and colelctor electrode 10 are mutually isolated；Gate electrode 8 is mutually isolated by barrier insulating layer 11 and monocrystalline substrate 1.
Conductive layer 6, tunneling insulation layer 7 and gate electrode 8 have collectively constituted the two-way breakdown protection double grid insulation tunnelling of body silicon and increased
The tunnelling base stage of strong transistor, when tunnelling occurs under control of the tunneling insulation layer 7 in gate electrode 8, electric current is from gate electrode 8 through tunnel
Wear insulating barrier 7 and flow to conductive layer 6, and powered for base 4.
The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon, by taking N-type as an example, launch site 3, base 4 and current collection
Area 5 is respectively N areas, P areas and N areas, and its specific operation principle is：When the positively biased of colelctor electrode 10, and gate electrode 8 is in low potential
When, enough electrical potential differences are not formed between gate electrode 8 and conductive layer 6, now tunneling insulation layer 7 is in high-impedance state, does not have
Obvious tunnelling current passes through, hence in so that sufficiently large base electric current can not be formed between base 4 and launch site 3 carrys out driving body silicon
Two-way breakdown protection double grid insulation tunnelling enhancing transistor, i.e. device are off state；With the gradually liter of the voltage of gate electrode 8
Height, the electrical potential difference between gate electrode 8 and conductive layer 6 gradually increases so that tunnelling insulate between gate electrode 8 and conductive layer 6
Electric-field intensity in layer 7 also gradually increases therewith, when the electric-field intensity in tunneling insulation layer 7 is located at below critical value, tunnelling
Insulating barrier 7 still keeps good high-impedance state, and the electrical potential difference between gate electrode and emitter stage almost drops in tunnelling insulation completely
Between the inner and outer wall both sides of layer 7, the electrical potential difference also allowed between base and launch site is minimum, therefore base does not almost have
Electric current flows through, and therefore device also keeps good off state, and when the electric-field intensity in tunneling insulation layer 7 be located at critical value with
When upper, tunneling insulation layer 7 can produce obvious tunnelling current due to tunneling effect, and tunnelling current then can be with gate electrode
The increase of 8 potentials is precipitous at a terrific speed to be risen, and it is interval in the extremely short potential change of gate electrode that this allows for tunneling insulation layer 7
Interior to be rapidly converted into low resistance state by high-impedance state, when tunneling insulation layer 7 is in low resistance state, now tunneling insulation layer 7 is in the He of gate electrode 8
The resistance formed between conductive layer 6 will be much smaller than the resistance formed between conductive layer 6 and emitter stage 3, and this allows for base 4
Sufficiently large positive bias-voltage is formd between launch site 3, and in the presence of tunneling effect, in tunneling insulation layer 7
Produce the movement of a large amount of electric currents between wall and outer wall, conductive layer 6, tunneling insulation layer 7 and gate electrode 8 have collectively constituted that body silicon is two-way to be hit
Wearing protection double grid insulation tunnelling strengthens the tunnelling base stage of transistor, when occurring tunnelling under control of the tunneling insulation layer 7 in gate electrode 8
When, electric current flow to conductive layer 6 from gate electrode 8 through tunneling insulation layer 7, and is powered for base 4；The emitted area 3 of the electric current of base 4 increases
Flowed out after strong by colelctor electrode, now device is in opening.
A kind of concrete technology step of the two-way breakdown protection double grid insulation tunnelling enhancing transistor fabrication process of body silicon is as follows：
Step 1: providing a doping concentration is not higher than 1016Body Silicon Wafer per cubic centimeter, passes through ion implanting or expansion
Day labor skill, is doped to the monocrystalline silicon thin film above body Silicon Wafer, preliminarily forms base 4.
Step 2: again by ion implanting or diffusion technique, to being doped above body Silicon Wafer, in step one shape
Into base 4 both sides formed, concentration opposite with the dopant type in step one be not less than 1019Heavy doping per cubic centimeter
Area, the heavily doped region is used to further form launch site 3 and collecting zone 5, is left between the heavily doped region and base undoped
Region, the undoped region be used for form breakdown protection area 2.
Step 3: forming rectangular-shape monocrystalline silicon isolated island on the body Silicon Wafer provided by techniques such as photoetching, etchings
Queue, makes to be arranged in sequence with launch site 3, breakdown protection area 2, base 4, breakdown protection area 2 and collecting zone 5 in each unit.
Step 4: above the wafer after deposit dielectric planarization surface to exposing launch site 3, base 4, collecting zone 5
With breakdown protection area 2, barrier insulating layer 11 is preliminarily formed.
Step 5: further forming rectangular-shape monocrystalline on the body Silicon Wafer provided by techniques such as photoetching, etchings
Silicon isolated island array, makes each monocrystalline silicon isolated island queue that step 3 is formed be divided into multiple units independent of each other.
Step 6: depositing dielectric above wafer, the part being etched away in step 5 is set fully to be filled, and put down
Smoothization surface further forms barrier insulating layer 11 to launch site 3, base 4, collecting zone 5 and breakdown protection area 2 is exposed.
Step 7: by etching technics, being carved to the barrier insulating layer 11 of the both sides of base 4 of each unit of crystal column surface
Erosion is to exposing monocrystalline substrate 1.
Step 8: depositing metal or the polysilicon with the heavy doping with the identical dopant type in base 4 above wafer, make
The barrier insulating layer 11 being etched away in step 7 is completely filled, then by surface planarisation to expose launch site 3, base 4, collection
Electric area 5, breakdown protection area 2 and barrier insulating layer 11, form conductive layer 6.
Step 9: being performed etching respectively in the side of the remote base of the conductive layer 6 of base both sides to barrier insulating layer 11.
Step 10: depositing tunneling insulation layer medium above wafer, make the barrier insulating layer 11 being etched away in step 9
Insulating dielectric layer is tunneled over to be filled up completely with, then by surface planarisation to exposing launch site 3, base 4, collecting zone 5, conductive layer 6, hit
Protection zone 2 and barrier insulating layer 11 are worn, tunneling insulation layer 7 is formed.
Step 11: entering respectively in the side of the remote base of the tunneling insulation layer 7 of base both sides to barrier insulating layer 11
Row etching.
Step 12: depositing metal or the polysilicon of heavy doping above wafer, make the resistance being etched away in step 11
Gear insulating barrier 11 is completely filled.
Step 13: by surface planarisation to expose launch site 3, base 4, collecting zone 5, conductive layer 6, tunneling insulation layer 7,
Breakdown protection area 2 and barrier insulating layer 11, preliminarily form gate electrode 8.
Step 14: depositing dielectric above wafer, barrier insulating layer 11 is further formed.
Step 15: by etching technics by the barrier insulating layer 11 of the top of gate electrode 8 formed positioned at step 13
Etch away.
Step 16: depositing metal or the polysilicon of heavy doping above wafer, make the resistance being etched away in step 15
Gear insulating barrier 11 is completely filled, by surface planarisation, further forms gate electrode 8.
Step 17: being etched away by etching technics for forming the part between device cell beyond trace portions, enter
One step formation gate electrode 8.
Step 18: depositing dielectric above wafer, by surface planarisation, barrier insulating layer 11 is further formed.
Step 19: the barrier insulating layer 11 of the top positioned at launch site 3 and collecting zone 5 is etched away by etching technics,
Form the through hole of emitter stage 9 and colelctor electrode 10.
Step 20: deposit metal above wafer, make the logical of emitter stage 9 formed in step 10 eight and colelctor electrode 10
Hole is completely filled, and passes through etching technics formation emitter stage 9 and colelctor electrode 10.
Advantage and effect
The invention has the advantages that and beneficial effect：
1. low cost
The specific manufacture method of the two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon is applied to common body silicon
Wafer, cost can be significantly reduced in contrast to the transistor of the manufactured identical function under expensive SOI wafer.
2. two-way breakdown protection function
The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon, device is being improved using breakdown protection area 12 just
To with reverse voltage endurance.By taking N-type device as an example, when colelctor electrode 10 is relative to 9 positively biased of emitter stage, by conductive layer 6, base 4,
The collector junction that breakdown protection area 12 and collecting zone 5 are constituted is in reverse-biased, puncturing between base 4 and collecting zone 5
Protection zone 12 for reverse-biased collector junction there is resistance to wear protective effect, therefore can be obviously improved the positive voltage endurance capability of device；
When colelctor electrode 10 is reverse-biased relative to emitter stage 9, the hair being made up of conductive layer 6, base 4, breakdown protection area 12 and launch site 3
Penetrate knot and be in reverse-biased, the breakdown protection area 12 between base 4 and launch site 3 has for reverse-biased emitter junction to be resisted
Protective effect is worn, therefore the reverse voltage endurance capability of device can be obviously improved；
3. high tunnelling current generation rate
The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon, has insulation tunnel junctions simultaneously in the both sides of base 4
Structure, makes insulation tunneling effect while occurring in base both sides, therefore improve tunnelling current under the control action of gate electrode 8
Generation rate.
4. outstanding switching characteristic
The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon and its manufacture method, utilize tunneling insulation layer impedance
The correlation extremely sensitive between tunneling insulation layer electric field intensity inside high, by choosing appropriate tunnel to tunneling insulation layer 7
Insulating materials, and the height and thickness of tunneling insulation layer 7 are suitably adjusted, so that it may so that tunneling insulation layer 7 is minimum
The conversion between high-impedance state and low resistance state is realized in gate electrode potential constant interval, it is possible to achieve more excellent switching characteristic.
5. high forward conduction electric current
The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon, gate insulation tunnelling current is flowed to by conductive layer 6
Base, and signal enhancing is carried out by launch site, with general T FETs just with a small amount of semiconductor interband tunnelling current conduct
The conducting electric current of device is compared, with more preferable forward current on state characteristic, for these reasons, in contrast to general T FETs devices
Part, the two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon can realize higher forward conduction electric current.
Brief description of the drawings
Fig. 1 is that the two-dimensional structure of the two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon of the present invention overlooks signal
Figure；
Fig. 2 is Fig. 1 diagrammatic cross-sections that tangentially A cuttings are obtained,
Fig. 3 is Fig. 1 diagrammatic cross-sections that tangentially B cuttings are obtained,
Fig. 4 is the schematic top plan view of step one,
Fig. 5 is Fig. 4 diagrammatic cross-sections that tangentially A cuttings are obtained,
Fig. 6 is the schematic top plan view of step 2,
Fig. 7 be Fig. 6 tangentially A cuttings the step of obtain two diagrammatic cross-section,
Fig. 8 is the schematic top plan view of step 3,
Fig. 9 be Fig. 8 tangentially A cuttings the step of obtain three diagrammatic cross-section,
Figure 10 is the schematic top plan view of step 4,
Figure 11 be Figure 10 tangentially A cuttings the step of obtain four diagrammatic cross-section,
Figure 12 is the schematic top plan view of step 5,
Figure 13 be Figure 12 tangentially B cuttings the step of obtain five diagrammatic cross-section,
Figure 14 is the schematic top plan view of step 6,
Figure 15 be Figure 14 tangentially B cuttings the step of obtain six diagrammatic cross-section,
Figure 16 is the schematic top plan view of step 7,
Figure 17 be Figure 16 tangentially B cuttings the step of obtain seven diagrammatic cross-section,
Figure 18 is the schematic top plan view of step 8,
Figure 19 be Figure 18 tangentially B cuttings the step of obtain eight diagrammatic cross-section,
Figure 20 is the schematic top plan view of step 9,
Figure 21 be Figure 20 tangentially B cuttings the step of obtain nine diagrammatic cross-section,
Figure 22 is the schematic top plan view of step 10,
Figure 23 be Figure 22 tangentially B cuttings the step of obtain ten diagrammatic cross-section,
Figure 24 is the schematic top plan view of step 11,
Figure 25 be Figure 24 tangentially B cuttings the step of obtain 11 diagrammatic cross-section,
Figure 26 is the schematic top plan view of step 12,
Figure 27 be Figure 26 tangentially A cuttings the step of obtain 12 diagrammatic cross-section,
Figure 28 be Figure 26 tangentially B cuttings the step of obtain 12 diagrammatic cross-section,
Figure 29 is the schematic top plan view of step 13,
Figure 30 be Figure 29 tangentially B cuttings the step of obtain 13 diagrammatic cross-section,
Figure 31 is the schematic top plan view of step 14,
Figure 32 be Figure 31 tangentially A cuttings the step of obtain 14 diagrammatic cross-section,
Figure 33 be Figure 31 tangentially B cuttings the step of obtain 14 diagrammatic cross-section,
Figure 34 is the schematic top plan view of step 15,
Figure 35 be Figure 34 tangentially B cuttings the step of obtain 15 diagrammatic cross-section,
Figure 36 is the schematic top plan view of step 10 six,
Figure 37 be Figure 36 tangentially A cuttings the step of obtain 16 diagrammatic cross-section,
Figure 38 be Figure 36 tangentially B cuttings the step of obtain 16 diagrammatic cross-section,
Figure 39 is the schematic top plan view of step 10 seven,
Figure 40 be Figure 39 tangentially A cuttings the step of obtain 17 diagrammatic cross-section,
Figure 41 is the schematic top plan view of step 10 eight,
Figure 42 be Figure 41 tangentially A cuttings the step of obtain 18 diagrammatic cross-section,
Figure 43 be Figure 41 tangentially B cuttings the step of obtain 18 diagrammatic cross-section,
Figure 44 is the schematic top plan view of step 10 nine,
Figure 45 be Figure 44 tangentially A cuttings the step of obtain 19 diagrammatic cross-section.
Description of reference numerals：
1st, monocrystalline substrate；2nd, breakdown protection area；3rd, launch site；4th, base；5th, collecting zone；6th, conductive layer；7th, tunnelling is exhausted
Edge layer；8th, gate electrode；9th, emitter stage；10th, colelctor electrode；11st, barrier insulating layer.
Embodiment
The present invention is described further below in conjunction with the accompanying drawings：
Two-dimensional structure if Fig. 1 is the two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon of the present invention overlooks signal
Figure；Fig. 2 is Fig. 1 diagrammatic cross-sections that tangentially A cuttings are obtained；Fig. 3 is Fig. 1 diagrammatic cross-sections that tangentially B cuttings are obtained；Tool
Body includes monocrystalline substrate 1；Breakdown protection area 2；Launch site 3；Base 4；Collecting zone 5；Conductive layer 6；Tunneling insulation layer 7；Grid electricity
Pole 8；Emitter stage 9；Colelctor electrode 10；Barrier insulating layer 11.
The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon, using the body Silicon Wafer comprising monocrystalline substrate 1
It is used as the substrate of generating device；Launch site 3, base 4, collecting zone 5 and breakdown protection area 2 are located at the top of monocrystalline substrate 1；Base
Area 4 is located between launch site 3 and collecting zone 5；Emitter stage 9 is located at the top of launch site 3；Colelctor electrode 10 is located at the upper of collecting zone 5
Side；Conductive layer 6, tunneling insulation layer 7 and gate electrode 8 form sandwich in the both sides of base 4 successively；Barrier insulating layer 11 and position
The upper surface portion phase mutual connection of monocrystalline substrate 1 beyond launch site 3, collecting zone 5, base 4 and the lower section of breakdown protection area 2
Touch.
To reach device function of the present invention, the present invention proposes the two-way breakdown protection double grid insulation tunnelling enhancing of body silicon
Transistor, its core texture is characterized as：
The impurity concentration in breakdown protection area 2 is less than 1016It is per cubic centimeter.
The impurity concentration of base 4 is not less than 1017Per cubic centimeter, both sides are in contact with conductive layer 6 and form Ohmic contact.
There is opposite impurity type between launch site 3 and base 4, between collecting zone 5 and base 4 and launch site 3 and transmitting
Formed between pole 9 between Ohmic contact, collecting zone 3 and colelctor electrode 10 and form Ohmic contact.
Conductive layer 6 is formed at the both sides of base 4, is metal material, or with base 4 have identical dopant type,
And doping concentration is more than 1019Semi-conducting material per cubic centimeter.
Tunneling insulation layer 7 is the insulation material layer for producing tunnelling current, with two independent sectors, each section shape
Into the opposite side of the side that is in contact with base 4 in the both sides conductive layer 6 of base 4.
Gate electrode 8 is the electrode for controlling tunneling insulation layer 7 to produce tunneling effect, is the electricity that control device is switched on and off
Pole, is in contact with the opposite side of the side that is in contact with conductive layer 6 of two independent sectors of tunneling insulation layer 7.
Conductive layer 6, tunneling insulation layer 7 and gate electrode 8 pass through barrier insulating layer 11 and launch site 3, emitter stage 9, current collection
Area 5 and colelctor electrode 10 are mutually isolated；Gate electrode 8 is mutually isolated by barrier insulating layer 11 and monocrystalline substrate 1.
Conductive layer 6, tunneling insulation layer 7 and gate electrode 8 have collectively constituted the two-way breakdown protection double grid insulation tunnelling of body silicon and increased
The tunnelling base stage of strong transistor, when tunnelling occurs under control of the tunneling insulation layer 7 in gate electrode 8, electric current is from gate electrode 8 through tunnel
Wear insulating barrier 7 and flow to conductive layer 6, and powered for base 4.
The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon, by taking N-type as an example, launch site 3, base 4 and current collection
Area 5 is respectively N areas, P areas and N areas, and its specific operation principle is：When the positively biased of colelctor electrode 10, and gate electrode 8 is in low potential
When, enough electrical potential differences are not formed between gate electrode 8 and conductive layer 6, now tunneling insulation layer 7 is in high-impedance state, does not have
Obvious tunnelling current passes through, hence in so that sufficiently large base electric current can not be formed between base 4 and launch site 3 carrys out driving body silicon
Two-way breakdown protection double grid insulation tunnelling enhancing transistor, i.e. device are off state；With the gradually liter of the voltage of gate electrode 8
Height, the electrical potential difference between gate electrode 8 and conductive layer 6 gradually increases so that tunnelling insulate between gate electrode 8 and conductive layer 6
Electric-field intensity in layer 7 also gradually increases therewith, when the electric-field intensity in tunneling insulation layer 7 is located at below critical value, tunnelling
Insulating barrier 7 still keeps good high-impedance state, and the electrical potential difference between gate electrode and emitter stage almost drops in tunnelling insulation completely
Between the inner and outer wall both sides of layer 7, the electrical potential difference also allowed between base and launch site is minimum, therefore base does not almost have
Electric current flows through, and therefore device also keeps good off state, and when the electric-field intensity in tunneling insulation layer 7 be located at critical value with
When upper, tunneling insulation layer 7 can produce obvious tunnelling current due to tunneling effect, and tunnelling current then can be with gate electrode
The increase of 8 potentials is precipitous at a terrific speed to be risen, and it is interval in the extremely short potential change of gate electrode that this allows for tunneling insulation layer 7
Interior to be rapidly converted into low resistance state by high-impedance state, when tunneling insulation layer 7 is in low resistance state, now tunneling insulation layer 7 is in the He of gate electrode 8
The resistance formed between conductive layer 6 will be much smaller than the resistance formed between conductive layer 6 and emitter stage 3, and this allows for base 4
Sufficiently large positive bias-voltage is formd between launch site 3, and in the presence of tunneling effect, in tunneling insulation layer 7
Produce the movement of a large amount of electric currents between wall and outer wall, conductive layer 6, tunneling insulation layer 7 and gate electrode 8 have collectively constituted that body silicon is two-way to be hit
Wearing protection double grid insulation tunnelling strengthens the tunnelling base stage of transistor, when occurring tunnelling under control of the tunneling insulation layer 7 in gate electrode 8
When, electric current flow to conductive layer 6 from gate electrode 8 through tunneling insulation layer 7, and is powered for base 4；The emitted area 3 of the electric current of base 4 increases
Flowed out after strong by colelctor electrode, now device is in opening.
The specific manufacture method of the two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon is applied to common body silicon
Wafer, cost can be significantly reduced in contrast to the transistor of the manufactured identical function under expensive SOI wafer.
The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon, device is being improved using breakdown protection area 12 just
To with reverse voltage endurance.By taking N-type device as an example, when colelctor electrode 10 is relative to 9 positively biased of emitter stage, by conductive layer 6, base 4,
The collector junction that breakdown protection area 12 and collecting zone 5 are constituted is in reverse-biased, puncturing between base 4 and collecting zone 5
Protection zone 12 for reverse-biased collector junction there is resistance to wear protective effect, therefore can be obviously improved the positive voltage endurance capability of device；
When colelctor electrode 10 is reverse-biased relative to emitter stage 9, the hair being made up of conductive layer 6, base 4, breakdown protection area 12 and launch site 3
Penetrate knot and be in reverse-biased, the breakdown protection area 12 between base 4 and launch site 3 has for reverse-biased emitter junction to be resisted
Protective effect is worn, therefore the reverse voltage endurance capability of device can be obviously improved.
The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon, has insulation tunnel junctions simultaneously in the both sides of base 4
Structure, makes insulation tunneling effect while occurring in base both sides, therefore improve tunnelling current under the control action of gate electrode 8
Generation rate.
The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon and its manufacture method, utilize tunneling insulation layer impedance
The correlation extremely sensitive between tunneling insulation layer electric field intensity inside high, by choosing appropriate tunnel to tunneling insulation layer 7
Insulating materials, and the height and thickness of tunneling insulation layer 7 are suitably adjusted, so that it may so that tunneling insulation layer 7 is minimum
The conversion between high-impedance state and low resistance state is realized in gate electrode potential constant interval, it is possible to achieve more excellent switching characteristic.
The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon, gate insulation tunnelling current is flowed to by conductive layer 6
Base, and signal enhancing is carried out by launch site, with general T FETs just with a small amount of semiconductor interband tunnelling current conduct
The conducting electric current of device is compared, with more preferable forward current on state characteristic, for these reasons, in contrast to general T FETs devices
Part, the two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon can realize higher forward conduction electric current.
The unit and array of the two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon proposed by the invention are in body
Specific manufacturing technology steps on Silicon Wafer are as follows：
Step 1: 1016 body Silicon Wafers per cubic centimeter are not higher than there is provided a doping concentration as shown in Fig. 4 to Fig. 5,
By ion implanting or diffusion technique, the monocrystalline silicon thin film above body Silicon Wafer is doped, base 4 is preliminarily formed.
Step 2: as shown in Figure 6 to 7, again by ion implanting or diffusion technique, to being mixed above body Silicon Wafer
Miscellaneous, it is every that the both sides of the base 4 formed in step one form that opposite with the dopant type in step one, concentration is not less than 1019
The heavily doped region of cubic centimetre, the heavily doped region is used to further form launch site 3 and collecting zone 5, the heavily doped region and base
Between leave undoped region, the undoped region be used for form breakdown protection area 2.
Step 3: as shown in Fig. 8 to Fig. 9, forming rectangular on the body Silicon Wafer provided by techniques such as photoetching, etchings
Body shape monocrystalline silicon isolated island queue, makes to be arranged in sequence with launch site 3, breakdown protection area 2, base 4, breakdown protection in each unit
Area 2 and collecting zone 5.
Step 4: as shown in Figure 10 to Figure 11, planarization surface is to exposing transmitting after deposit dielectric above wafer
Area 3, base 4, collecting zone 5 and breakdown protection area 2, preliminarily form barrier insulating layer 11.
Step 5: as shown in Figure 12 to Figure 13, further by techniques such as photoetching, etchings on the body Silicon Wafer provided
Formed rectangular-shape monocrystalline silicon isolated island array, each the monocrystalline silicon isolated island queue for being formed step 3 be divided into it is multiple each other
Independent unit.
Step 6: as shown in Figure 14 to Figure 15, dielectric is deposited above wafer, make the portion being etched away in step 5
Divide and be fully filled, and planarize surface to launch site 3, base 4, collecting zone 5 and breakdown protection area 2 is exposed, further formed
Barrier insulating layer 11.
Step 7: as shown in Figure 16 to Figure 17, by etching technics, to the both sides of base 4 of each unit of crystal column surface
Barrier insulating layer 11 is performed etching to exposing monocrystalline substrate 1.
Step 8: as shown in Figure 18 to Figure 19, deposited above wafer metal or with the identical dopant type in base 4
The polysilicon of heavy doping, is completely filled the barrier insulating layer 11 being etched away in step 7, then surface planarisation is extremely revealed
Go out launch site 3, base 4, collecting zone 5, breakdown protection area 2 and barrier insulating layer 11, form conductive layer 6.
Step 9: as shown in Figure 20 to Figure 21, respectively base both sides conductive layer 6 remote base side to stopping
Insulating barrier 11 is performed etching.
Step 10: as shown in Figure 22 to Figure 23, tunneling insulation layer medium being deposited above wafer, makes to be etched in step 9
The barrier insulating layer 11 fallen is tunneled over insulating dielectric layer and is filled up completely with, then by surface planarisation to expose launch site 3, base 4, collection
Electric area 5, conductive layer 6, breakdown protection area 2 and barrier insulating layer 11, form tunneling insulation layer 7.
Step 11: as shown in Figure 24 to Figure 25, respectively base both sides tunneling insulation layer 7 remote base side
Barrier insulating layer 11 is performed etching.
Step 12: as shown in Figure 26 to Figure 28, metal or the polysilicon of heavy doping being deposited above wafer, makes step 10
The barrier insulating layer 11 being etched away in one is completely filled.
Step 13: as shown in Figure 29 to 30, by surface planarisation to exposing launch site 3, it is base 4, collecting zone 5, conductive
Floor 6, tunneling insulation layer 7, breakdown protection area 2 and barrier insulating layer 11, preliminarily form gate electrode 8.
Step 14: as shown in Figure 31 to Figure 33, dielectric being deposited above wafer, barrier insulating layer is further formed
11。
Step 15: as shown in Figure 34 to Figure 35, by etching technics by the gate electrode 8 that step 13 is formed
The barrier insulating layer 11 of side is etched away.
Step 16: as shown in Figure 36 to Figure 38, metal or the polysilicon of heavy doping being deposited above wafer, makes step 10
The barrier insulating layer 11 being etched away in five is completely filled, by surface planarisation, further forms gate electrode 8.
Step 17: as shown in Figure 39 to Figure 40, being etched away by etching technics is used to form cabling between device cell
Part beyond part, further forms gate electrode 8.
Step 18: as shown in Figure 41 to Figure 43, dielectric is deposited above wafer, by surface planarisation, further
Form barrier insulating layer 11.
Step 19: as shown in Figure 44 to 45, the top positioned at launch site 3 and collecting zone 5 is etched away by etching technics
Barrier insulating layer 11, form the through hole of emitter stage 9 and colelctor electrode 10.
Step 20: as shown in Figure 1 to Figure 3, metal is deposited above wafer, make the emitter stage formed in step 10 eight
9 and the through hole of colelctor electrode 10 be completely filled, and pass through etching technics formation emitter stage 9 and colelctor electrode 10.
Claims (8)
1. the two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon, it is characterised in that：Using including monocrystalline substrate（1）
Body Silicon Wafer as generating device substrate；Launch site（3）, base（4）, collecting zone（5）With breakdown protection area（2）Positioned at list
Crystalline silicon substrate（1）Top；Base（4）Positioned at launch site（3）And collecting zone（5）Between, breakdown protection area（2）Positioned at base
（4）Both sides；Emitter stage（9）Positioned at launch site（3）Top；Colelctor electrode（10）Positioned at collecting zone（5）Top；Conductive layer
（6）, tunneling insulation layer（7）And gate electrode（8）Successively in base（4）Both sides formed sandwich；Barrier insulating layer（11）With
Positioned at launch site（3）, collecting zone（5）, base（4）With breakdown protection area（2）Monocrystalline substrate beyond lower section（1）Upper surface
Part contacts with each other；Breakdown protection area（2）Impurity concentration be less than 1016It is per cubic centimeter；Base（4）Impurity concentration be not less than
1017It is per cubic centimeter；Base（4）Both sides and conductive layer（6）It is in contact and forms Ohmic contact.
2. the two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon according to claim 1, it is characterised in that：Hair
Penetrate area（3）With base（4）Between, collecting zone（5）With base（4）Between there is opposite impurity type, and launch site（3）With transmitting
Pole（9）Between form Ohmic contact, collecting zone（5）With colelctor electrode（10）Between form Ohmic contact.
3. the two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon according to claim 1, it is characterised in that：Lead
Electric layer（6）It is formed at base（4）Both sides, conductive layer（6）It is metal material either same base（4）With identical dopant type
And doping concentration be more than 1019Semi-conducting material per cubic centimeter.
4. the two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon according to claim 1, it is characterised in that：Tunnel
Wear insulating barrier（7）For the insulation material layer for producing tunnelling current, with two independent sectors, each section is formed at base
（4）Both sides conductive layer（6）And base（4）Be in contact the opposite side of side.
5. the two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon according to claim 1, it is characterised in that：Grid
Electrode（8）It is control tunneling insulation layer（7）The electrode of tunneling effect is produced, is the electrode that control device is switched on and off, with tunnel
Wear insulating barrier（7）Two independent sectors and conductive layer（6）The opposite side of side of being in contact is in contact.
6. the two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon according to claim 1, it is characterised in that：Lead
Electric layer（6）, tunneling insulation layer（7）And gate electrode（8）Pass through barrier insulating layer（11）With launch site（3）, emitter stage（9）, collection
Electric area（5）And colelctor electrode（10）It is mutually isolated；Gate electrode（8）Pass through barrier insulating layer（11）With monocrystalline substrate（1）Mutually every
From.
7. the two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon according to claim 1, it is characterised in that：Lead
Electric layer（6）, tunneling insulation layer（7）And gate electrode（8）The two-way breakdown protection double grid insulation tunnelling enhancing of body silicon is collectively constituted brilliant
The tunnelling base stage of body pipe, works as tunneling insulation layer（7）In gate electrode（8）Control under when occurring tunnelling, electric current is from gate electrode（8）Through
Tunneling insulation layer（7）It flow to conductive layer（6）, and be base（4）Power supply.
8. a kind of two-way breakdown protection double grid insulation tunnelling of body silicon as claimed in claim 1 strengthens the manufacture method of transistor,
It is characterized in that：This method step is as follows：
Step 1: providing a doping concentration is not higher than 1016Body Silicon Wafer per cubic centimeter, passes through ion implanting or diffusion work
Skill, is doped to the monocrystalline silicon thin film above body Silicon Wafer, preliminarily forms base（4）；
Step 2: again by ion implanting or diffusion technique, to being doped above body Silicon Wafer, being formed in step one
Base（4）Both sides formed, concentration opposite with the dopant type in step one be not less than 1019Heavy doping per cubic centimeter
Area, the heavily doped region is used to further form launch site（3）And collecting zone（5）, left between the heavily doped region and base without
The region of doping, the undoped region is used to form breakdown protection area（2）；
Step 3: forming rectangular-shape monocrystalline silicon isolated island queue on the body Silicon Wafer provided by photoetching, etching technics, make
Launch site is arranged in sequence with each unit（3）, breakdown protection area（2）, base（4）, breakdown protection area（2）And collecting zone
（5）；
Step 4: above the wafer after deposit dielectric planarization surface to exposing launch site（3）, base（4）, collecting zone
（5）With breakdown protection area（2）, preliminarily form barrier insulating layer（11）；
Step 5: further forming rectangular-shape monocrystalline silicon isolated island on the body Silicon Wafer provided by photoetching, etching technics
Array, makes each monocrystalline silicon isolated island queue that step 3 is formed be divided into multiple units independent of each other；
Step 6: depositing dielectric above wafer, the part being etched away in step 5 is set fully to be filled, and planarize
Surface is to exposing launch site（3）, base（4）, collecting zone（5）With breakdown protection area（2）, further form barrier insulating layer
（11）；
Step 7: by etching technics, to the base of each unit of crystal column surface（4）The barrier insulating layer of both sides（11）Carved
Erosion is to exposing monocrystalline substrate（1）；
Step 8: depositing metal above wafer or having and base（4）The polysilicon of the heavy doping of identical dopant type, makes step
The barrier insulating layer being etched away in rapid seven（11）It is completely filled, then by surface planarisation to exposing launch site（3）, base
（4）, collecting zone（5）, breakdown protection area（2）And barrier insulating layer（11）, form conductive layer（6）；
Step 9: respectively in the conductive layer of base both sides（6）Remote base side to barrier insulating layer（11）Perform etching；
Step 10: depositing tunneling insulation layer medium above wafer, make the barrier insulating layer being etched away in step 9（11）Quilt
Tunneling insulation layer medium is filled up completely with, then by surface planarisation to exposing launch site（3）, base（4）, collecting zone（5）, conductive layer
（6）, breakdown protection area（2）And barrier insulating layer（11）, form tunneling insulation layer（7）；
Step 11: respectively in the tunneling insulation layer of base both sides（7）Remote base side to barrier insulating layer（11）Enter
Row etching；
Step 12: depositing metal or the polysilicon of heavy doping above wafer, make the stop being etched away in step 11 exhausted
Edge layer（11）It is completely filled；
Step 13: by surface planarisation to exposing launch site（3）, base（4）, collecting zone（5）, conductive layer（6）, tunnelling insulation
Layer（7）, breakdown protection area（2）And barrier insulating layer（11）, preliminarily form gate electrode（8）；
Step 14: depositing dielectric above wafer, barrier insulating layer is further formed（11）；
Step 15: the gate electrode that will be formed by etching technics positioned at step 13（8）The barrier insulating layer of top（11）
Etch away；
Step 16: depositing metal or the polysilicon of heavy doping above wafer, make the stop being etched away in step 15 exhausted
Edge layer（11）It is completely filled, by surface planarisation, further forms gate electrode（8）；
Step 17: being etched away for forming the part between device cell beyond trace portions, further by etching technics
Form gate electrode（8）；
Step 18: depositing dielectric above wafer, by surface planarisation, barrier insulating layer is further formed（11）；
Step 19: being etched away by etching technics positioned at launch site（3）And collecting zone（5）Top barrier insulating layer
（11）, form emitter stage（9）And colelctor electrode（10）Through hole；
Step 20: depositing metal above wafer, make the emitter stage formed in step 10 eight（9）And colelctor electrode（10）It is logical
Hole is completely filled, and forms emitter stage by etching technics（9）And colelctor electrode（10）.
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