CN104104825A - Double-sided scanner acquisition system based on FPGA and scanning and correction method thereof - Google Patents
Double-sided scanner acquisition system based on FPGA and scanning and correction method thereof Download PDFInfo
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Abstract
The invention discloses a double-sided scanner acquisition system based on an FPGA and a scanning and correction method thereof. The system comprises a scanning data processing system, a PC host, a first CIS sensor, a second CIS sensor, and a CIS transmission module which is connected with the first CIS sensor and the second CIS sensor simultaneously. The scanning data processing system comprises an FPGA master control chip, a first data conversion module, a second data conversion module, a first memory, a communication interface, a correction module and a USB module which are connected with the FPGA master control chip simultaneously, and an onboard power supply module. The first CIS sensor is connected with the first data conversion module. The second CIS sensor is connected with the second data conversion module. The CIS transmission module is connected with the communication interface. The PC host is connected with the USB module. The double-sided scanner acquisition system based on the FPGA is reasonable in design and convenient to use so that rapid scanning and imaging can be realized, images of two sides are displayed in one step, and thus the double-sided scanner acquisition system based the FPGA is suitable for popularization and application.
Description
Technical field
The present invention relates to a kind of scanner acquisition system, what be specifically related to is a kind of Double face scanner acquisition system and scanning and bearing calibration based on FPGA.
Background technology
The scanner that existing market is conventional, adopts the single-chip microcomputers such as ARM as main control chip mostly.Although take advantage on cost, due to the restriction of ARM chip itself, simultaneously also because scanner self system is unreasonable, cause sweep speed slower, be difficult to meet the live and work rhythm that people accelerate day by day.And existing scanner is generally single-sweep pattern, for the sweep object of double-side pattern, need manual operation twice, do not meet intelligent demand.
Summary of the invention
The object of the present invention is to provide a kind of Double face scanner acquisition system and scanning and bearing calibration based on FPGA, mainly solve existing scanning speed of scanner slow and can not the disposable problem that pattern two sides is scanned.
To achieve these goals, the technical solution used in the present invention is as follows:
Double face scanner acquisition system based on FPGA, comprise scan-data treatment system, PC main frame, for a CIS transducer of acquisition scans object direct picture data with for the 2nd CIS transducer of acquisition scans object reverse side view data, and the CIS transmission module being connected with a CIS transducer and the 2nd CIS transducer simultaneously; Described scan-data treatment system comprises FPGA main control chip, the first data conversion module, the second data conversion module, first memory, communication interface, correction module and USB module simultaneously that be connected with this FPGA main control chip, and for the board mounted power module to whole scan-data treatment system power supply; A described CIS transducer is connected with the first data conversion module, and described the 2nd CIS transducer is connected with the second data conversion module, and described CIS transmission module is connected with communication interface, and described PC main frame is connected with USB module.
As preferably, described USB module is connected with PC main frame by USB2.0 interface.
Specifically, described the first data conversion module comprises the first analog to digital converter and the first light source controller that are all connected with a CIS transducer and FPGA main control chip simultaneously.
Specifically, described the second data conversion module comprises the second analog to digital converter and the secondary light source controller that are all connected with the 2nd CIS transducer and FPGA main control chip simultaneously.
Further, described scan-data treatment system also comprises the second memory being connected with FPGA main control chip.
Again further, described scan-data treatment system also comprises the on-line debugging interface being connected with FPGA main control chip.
Based on above-mentioned hardware foundation, the present invention also provides scan method and the bearing calibration of this Double face scanner acquisition system based on FPGA, as described below respectively:
Scan method
Comprise the following steps:
(1), after system powers on, PC main frame sends scan instruction by USB module to FPGA main control chip;
(2) FPGA main control chip produces the required clock of each module and control signal after receiving instruction, control respectively two CIS transducers by two light source controllers lights simultaneously, and pass to CIS transmission module by communication interface, make mechanical action equipment control respectively a CIS transducer according to the scan pattern of PC main frame requirement and the 2nd CIS transducer carries out IMAQ to the two sides of sweep object;
After (3) two CIS sensor scan images, send data to two analog to digital converters, under the change over clock signal that two analog to digital converters provide at FPGA main control chip, convert the analog signal of two CIS transducer outputs to digital signal respectively, be then transferred in FPGA main control chip simultaneously and process;
(4) after FPGA main control chip deal with data, transfer to PC main frame by USB module, and receive at PC main frame after the data of two sides image, image is shown.
Bearing calibration
Comprise the following steps:
(1), after system powers on, PC main frame sends correction instruction by USB module to FPGA main control chip;
(2) FPGA main control chip produces the required clock of each module and control signal after receiving instruction, control respectively two CIS transducers by two light source controllers lights simultaneously, and pass to CIS transmission module by communication interface, make mechanical action equipment control respectively a CIS transducer and the 2nd CIS transducer according to the scan pattern of PC main frame requirement IMAQ is carried out in the two sides of proofreading and correct paper; In this step, it is bright at the front field time point of scan image that light source controller is only controlled CIS transducer, closes CIS transducer and close light source when rear field;
After (3) two CIS sensor scan images, send data to two analog to digital converters, under the change over clock signal that two analog to digital converters provide at FPGA main control chip, also convert the analog signal of two CIS transducers outputs to digital signal respectively, be then transferred in memory and store;
(4) view data in FPGA main control chip read memory processing, then transfer to PC main frame by USB module, and receive at PC main frame after the data of two sides image, rearrange according to each pixel RGB order, obtain correcting image and show; PC main frame goes out correction parameter according to the image calculation showing simultaneously, and transfers in FPGA main control chip;
(5) FPGA main control chip receives parameter, and store into and there is power failure data and do not lose in the correction module of function, when later each scan image, when FPGA main control chip is from memory after reads image data, read again the correction parameter in correction module, and correction parameter and view data are calculated, obtain the view data after proofreading and correct, be finally transferred to PC main frame by USB module again.
Specifically, in described step (4), the process of PC Framework computing correction parameter is as follows:
(a) PC main frame obtains after view data, before extracting, the 500th of first pixel the walks to R, the G that the 999th row amounts to 500 row, the data of tri-passages of B in half frame images, and obtains this pixel the 500th and walk to the rgb pixel value in the every a line of the 999th row;
(b) the 500th rgb pixel value that walks to this pixel in the every a line of the 999th row is done average computing by PC main frame, obtains R
1 is equal, G
1 is equal, B
1 is equal, obtain R, the G of first pixel in front half frame images, the correction parameter of tri-kinds of color modes of B;
(c) circulation step (a) and (b) successively, until PC main frame has extracted the remaining pixel of front half frame images, and obtain R, the G of remaining each pixel in front half frame images, the correction parameter of tri-kinds of color modes of B;
(d) PC main frame extracts the 500th pixel value walking in the every a line of the 999th row of first pixel in rear half frame images;
(e) the 500th pixel value that walks to this pixel in the every a line of the 999th row is done average computing by PC main frame, obtains black
all, obtain the black correction parameter of first pixel in rear half frame images;
(f) circulation step (d), (e) successively, until PC main frame takes the remaining pixel of rear half frame images, and obtains the black correction parameter of remaining each pixel in rear half frame images;
(g) the black correction parameter of the R of front half frame images, G, B and rear half frame images is transferred to FPGA main control chip by PC main frame, for correction calculation.
Compared with prior art, the present invention has following beneficial effect:
(1) the present invention is reasonable in design, with low cost, and sweep speed is fast, and efficiency is high.
(2) the present invention adopts CIS transducer to gather the two sides of image, its have volume little, easy for installation, without external light source, the advantage that low in energy consumption and imaging zero distorts, than CCD and CMOS, cost is also cheap a lot, then adopt FPGA as main control chip, be responsible for transmission and the processing of image, because FPGA has, internal resource is abundant, I/O quantity is many and can customize the features such as function, can process mass data with very high clock frequency, thereby can publish picture and lay the foundation for rapid scanning.In the present invention, FPGA main control chip is after in conjunction with data conversion module and communication interface, the progressive image that CIS transducer can be collected carries out assembled arrangement, then export complete view data to PC main frame, it has realized the function of rapid scanning image and disposable duplex scanning well by the combination of software and hardware, significantly optimize the performance of scanning, therefore, the present invention compared with prior art, has outstanding substantive distinguishing features and significant progressive.
(3) the present invention has also designed the scheme of correct scan, also be the combination by software and hardware, proofread and correct paper by scanning and obtain needing separately under color mode and black and white scan pattern the correction parameter of using, and apply it in real image scanning, the view data gathering is proofreaied and correct, guarantee the precision of its image scan data, last scanning image out was both conformed to actual scanning object, there is again enough definition.
(4) the present invention is also provided with on-line debugging interface, can with system external debug equipment connection, make FPGA main control chip had can on-line debugging characteristic, user can programme to FPGA according to actual needs again, its functional additive technique and amendment are very convenient, by the present invention's hardware designs cleverly, thereby be also follow-up enhancing and improve systemic-function of the present invention and made good place mat.
(5) cost performance of the present invention is high, workable, and it is with a wide range of applications, and is suitable for applying.
Brief description of the drawings
Fig. 1 is system configuration schematic diagram of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the invention will be further described, and embodiments of the present invention include but not limited to the following example.
Embodiment
As shown in Figure 1, the present invention includes a CIS transducer, the 2nd CIS transducer, scan-data treatment system and PC main frame.A described CIS transducer and the 2nd CIS transducer are used for gathering image, wherein CIS transducer is for the direct picture of acquisition scans object, another root CIS transducer is for the reverse side image of acquisition scans object, and two CIS transducers are connected with scan-data treatment system simultaneously.Described scan-data treatment system is connected with PC main frame, and its instruction issuing according to PC main frame is processed image and transmitted.Specifically, described scan-data treatment system comprises FPGA main control chip, the first data conversion module, the second data conversion module, first memory, communication interface, correction module, USB module and on-line debugging interface simultaneously that be connected with this FPGA main control chip, and for the board mounted power module to whole scan-data treatment system power supply; Wherein, described the first data conversion module is made up of the first analog to digital converter and the first light source controller, the two is all connected with a CIS transducer and FPGA main control chip simultaneously, the second data conversion module is made up of the second analog to digital converter and secondary light source controller, the two is all connected with the 2nd CIS transducer and FPGA main control chip simultaneously, described PC main frame is connected with USB module, and in the present embodiment, scan-data treatment system is connected with PC main frame by USB2.0 interface.
First memory in scan-data treatment system is for temporary storaging data, so that FPGA main control chip is carrying out transferring data in the processing of image and the process of transmission, and in order further to expand the capacity of storage, the present embodiment is also provided with second memory.And further, the type of first memory and second memory is two generation DDR(DRR II).
Communication interface in scan-data treatment system is for making the mechanical action equipment connection of FPGA main control chip and scanner, so that the instruction control mechanical action equipment control CIS sensor scan image issuing by FPGA main control chip.
Correction module in scan-data treatment system for after system compensation, is stored the correction parameter of its generation, and this correction module has the characteristic that power failure data is not lost, and can guarantee that correction parameter do not lose, and the moment facilitates system to proofread and correct in the time of scan image.
On-line debugging interface in scan-data treatment system connects external debug equipment for system, thereby according to actual needs FPGA main control chip is carried out to reprogramming, and its function is added and revised.
Based on above-mentioned hardware foundation, below implementation procedure of the present invention is introduced.The present invention has normal scan and two kinds of patterns of correct scan, and the two flow process is as follows respectively:
Normal scan mode
(1), after system powers on, PC main frame sends scan instruction by USB module to FPGA main control chip;
(2) FPGA main control chip produces the required clock of each module and control signal after receiving instruction, control respectively two CIS transducers by two light source controllers lights simultaneously, and pass to CIS transmission module by communication interface, make CIS transmission module control respectively a CIS transducer according to the scan pattern of PC main frame requirement and the 2nd CIS transducer carries out IMAQ to the two sides of sweep object;
After (3) two CIS sensor scan images, send data to two analog to digital converters, under the change over clock signal that two analog to digital converters provide at FPGA main control chip, convert the analog signal of two CIS transducer outputs to digital signal respectively, be then transferred in FPGA main control chip simultaneously and process;
(4) after FPGA main control chip deal with data, transfer to PC main frame by USB module, and receive at PC main frame after the data of two sides image, image is shown.
Correction mode
(1), after system powers on, PC main frame sends correction instruction by USB module to FPGA main control chip;
(2) FPGA main control chip produces the required clock of each module and control signal after receiving instruction, control respectively two CIS transducers by two light source controllers lights simultaneously, and pass to CIS transmission module by communication interface, make CIS transmission module control respectively a CIS transducer and the 2nd CIS transducer according to the scan pattern of PC main frame requirement IMAQ is carried out in the two sides of proofreading and correct paper; In this step, it is bright at the front field time point of scan image that light source controller is only controlled CIS transducer, closes CIS transducer and close light source when rear field;
After (3) two CIS sensor scan images, send data to two analog to digital converters, under the change over clock signal that two analog to digital converters provide at FPGA main control chip, also convert the analog signal of two CIS transducers outputs to digital signal respectively, be then transferred in memory and store;
(4) view data in FPGA main control chip read memory processing, then transfer to PC main frame by USB module, and receive at PC main frame after the data of two sides image, rearrange according to each pixel RGB order, obtain correcting image and show; PC main frame goes out correction parameter according to the image calculation showing simultaneously, and transfers in FPGA main control chip;
In this step, the process of PC Framework computing correction parameter is as follows:
(a) PC main frame obtains after view data, before extracting, the 500th of first pixel the walks to R, the G that the 999th row amounts to 500 row, the data of tri-passages of B in half frame images, and obtains this pixel the 500th and walk to the rgb pixel value in the every a line of the 999th row;
(b) the 500th rgb pixel value that walks to this pixel in the every a line of the 999th row is done average computing by PC main frame, obtains R
1 is equal, G
1 is equal, B
1 is equal, obtain R, the G of first pixel in front half frame images, the correction parameter of tri-kinds of color modes of B;
(c) circulation step (a) and (b) successively, until PC main frame has extracted the remaining pixel of front half frame images, and obtain R, the G of remaining each pixel in front half frame images, the correction parameter of tri-kinds of color modes of B;
(d) PC main frame extracts the 500th pixel value walking in the every a line of the 999th row of first pixel in rear half frame images;
(e) the 500th pixel value that walks to this pixel in the every a line of the 999th row is done average computing by PC main frame, obtains black
all, obtain the black correction parameter of first pixel in rear half frame images;
(f) circulation step (d), (e) successively, until PC main frame takes the remaining pixel of rear half frame images, and obtains the black correction parameter of remaining each pixel in rear half frame images;
(g) the black correction parameter of the R of front half frame images, G, B and rear half frame images is transferred to FPGA main control chip by PC main frame, and for correction calculation, it can be for the correction under color mode, also can be for the correction under black and white scan pattern;
(5) FPGA main control chip receives parameter, and store into and there is power failure data and do not lose in the correction module of function, when later each scan image, when FPGA main control chip is from memory after reads image data, read again the correction parameter in correction module, and correction parameter and view data are calculated, obtain the view data after proofreading and correct, be finally transferred to PC main frame by USB module again.
Understand for convenience the calculating about correction parameter in the present invention, the present embodiment explains with a calculated examples.
Prepare a pure white correction paper, it is scanned, due to before scanning when half frame images, CIS transducer is lit, and after scanning when half frame images, CIS transducer light source is closed, and therefore, the pure white image of demonstration is also front half frame images.And the resolution of the image of this demonstration is 300DPI, pixel is 2544 x 3504, and the width of image is 2544 pixels, is also that a line view data number is 2544.
Taking first pixel as example:
The 500th row image is divided into three color channels, can be designated as respectively:
R passage: R
1_ 500, R
2_ 500, R
3_ 500 ... R
2544_ 500;
G passage: G
1_ 500, G
2_ 500, G
3_ 500 ... G
2544_ 500;
B passage: B
1_ 500, B
2_ 500, B
3_ 500 ... B
2544_ 500;
The 500th row first row pixel value is (R
1_ 500, G
1_ 500, B
1_ 500).
In like manner can obtain the 501st row first row pixel value is (R
1_ 501, G
1_ 501, B
1_ 501);
The 502nd row first row pixel value is (R
1_ 502, G
1_ 502, B
1_ 502);
……
The 999th row first row pixel value is (R
1_ 999, G
1_ 999, B
1_ 999).
Tri-passages of RGB are done respectively to average computing, and taking R passage as example, formula is as follows:
R
1 is equal=(R
1_ 500+R
1_ 501+R
1_ 502+... + R
1_ 999)/500
G
1 is equaland B
1 is equalcomputing formula and R
1 is equalidentical.
Finally, the R obtaining
1 is equal, G
1 is equaland B
1 is equalbe the RGB correction parameter of first pixel of image.Same computational methods can obtain the RGB correction parameter of all the other 2543 pixels.
Rear half frame images is because light source is closed, thereby what obtain is black image, tri-passage gray values of RGB of the image any point that its scanning obtains all equate, then the same correction parameter that adopts similar aforesaid way to obtain rear each pixel of half frame images, here, we are referred to as black correction parameter.
Thus, R, G, these several correction parameters of B, black of obtaining can all calculate, and in color mode, be used as the correction of view data.
The above-mentioned G calculating, black correction parameter are used as the correction of view data in black and white scan pattern, and in black and white scan pattern, we are referred to as the white WhiteG parameter of gray scale the G correction parameter here.
Above-mentioned correction parameter calculates the 500th row to the 999 row images that why adopt each pixel, for the scanning accuracy in conjunction with existing scanner, in general, proofread and correct paper in the time of scanning, be fixed as A4 breadth owing to proofreading and correct paper, therefore, approximately from the 20th row, the rgb pixel value that it scans is out comparatively stable, the present invention gets its pixel value from the 500th row, and for calculation correction parameter, so calculating can make the accuracy rate of proofreading and correct significantly improve, and also very high for proofreading and correct the reliability of view data of subsequent acquisition.If adopt the 1st row to the 500 row images, because of the reason of scanning accuracy, may cause the not correct correction paper image for scanning of image of the 1st row, thus, will cause correction parameter mistake in computation.Therefore, the present invention selects to record the data of R, G, tri-passages of B since the 500th row image, and for calculation correction parameter.So both consider the reason of existing scanner scanning precision, also reached well the object that the present invention utilizes correction parameter to proofread and correct the view data gathering.
The present invention adopts FPGA as main control chip, and redesign the structure of system, make its had sweep speed fast, can be disposable by the function of image two sides scanning, and possesses the view data function of proofreading and correct to gathering, guarantee that image accurately shows, improve the precision that image shows.The present invention is all linked with one another in design details, closely cooperates, and by software and hardware combining, has well formed a complete function system, and therefore, compared with prior art, technological progress is fairly obvious in the present invention.
Above-described embodiment is only preferably one of implementation of the present invention; should be in order to not limit the scope of the invention; the technical scheme of all any change or the polishing of having no essential meaning done under body design thought of the present invention and spirit, all should be in protection scope of the present invention.
Claims (9)
1. the Double face scanner acquisition system based on FPGA, it is characterized in that, comprise scan-data treatment system, PC main frame, for a CIS transducer of acquisition scans object direct picture data with for the 2nd CIS transducer of acquisition scans object reverse side view data, and the CIS transmission module being connected with a CIS transducer and the 2nd CIS transducer simultaneously; Described scan-data treatment system comprises FPGA main control chip, the first data conversion module, the second data conversion module, first memory, communication interface, correction module and USB module simultaneously that be connected with this FPGA main control chip, and for the board mounted power module to whole scan-data treatment system power supply; A described CIS transducer is connected with the first data conversion module, and described the 2nd CIS transducer is connected with the second data conversion module, and described CIS transmission module is connected with communication interface, and described PC main frame is connected with USB module.
2. the Double face scanner acquisition system based on FPGA according to claim 1, is characterized in that, described USB module is connected with PC main frame by USB2.0 interface.
3. the Double face scanner acquisition system based on FPGA according to claim 1 and 2, it is characterized in that, described the first data conversion module comprises the first analog to digital converter and the first light source controller that are all connected with a CIS transducer and FPGA main control chip simultaneously.
4. the Double face scanner acquisition system based on FPGA according to claim 3, is characterized in that, described the second data conversion module comprises the second analog to digital converter and the secondary light source controller that are all connected with the 2nd CIS transducer and FPGA main control chip simultaneously.
5. the Double face scanner acquisition system based on FPGA according to claim 4, is characterized in that, described scan-data treatment system also comprises the second memory being connected with FPGA main control chip.
6. the Double face scanner acquisition system based on FPGA according to claim 5, is characterized in that, described scan-data treatment system also comprises the on-line debugging interface being connected with FPGA main control chip.
7. the scan method of the Double face scanner acquisition system based on FPGA, is characterized in that, comprises the following steps:
(1), after system powers on, PC main frame sends scan instruction by USB module to FPGA main control chip;
(2) FPGA main control chip produces the required clock of each module and control signal after receiving instruction, control respectively two CIS transducers by two light source controllers lights simultaneously, and pass to CIS transmission module by communication interface, make CIS transmission module control respectively a CIS transducer according to the scan pattern of PC main frame requirement and the 2nd CIS transducer carries out IMAQ to the two sides of sweep object;
After (3) two CIS sensor scan images, send data to two analog to digital converters, under the change over clock signal that two analog to digital converters provide at FPGA main control chip, convert the analog signal of two CIS transducer outputs to digital signal respectively, be then transferred in FPGA main control chip simultaneously and process;
(4) after FPGA main control chip deal with data, transfer to PC main frame by USB module, and receive at PC main frame after the data of two sides image, image is shown.
8. the bearing calibration of the Double face scanner acquisition system based on FPGA, is characterized in that, comprises the following steps:
(1), after system powers on, PC main frame sends correction instruction by USB module to FPGA main control chip;
(2) FPGA main control chip produces the required clock of each module and control signal after receiving instruction, control respectively two CIS transducers by two light source controllers lights simultaneously, and pass to CIS transmission module by communication interface, make mechanical action equipment control respectively a CIS transducer and the 2nd CIS transducer according to the scan pattern of PC main frame requirement IMAQ is carried out in the two sides of proofreading and correct paper; In this step, it is bright at the front field time point of scan image that light source controller is only controlled CIS transducer, closes CIS transducer and close light source when rear field;
After (3) two CIS sensor scan images, send data to two analog to digital converters, under the change over clock signal that two analog to digital converters provide at FPGA main control chip, also convert the analog signal of two CIS transducers outputs to digital signal respectively, be then transferred in memory and store;
(4) view data in FPGA main control chip read memory processing, then transfer to PC main frame by USB module, and receive at PC main frame after the data of two sides image, rearrange according to each pixel RGB order, obtain correcting image and show; PC main frame goes out correction parameter according to the image calculation showing simultaneously, and transfers in FPGA main control chip;
(5) FPGA main control chip receives parameter, and store into and there is power failure data and do not lose in the correction module of function, when later each scan image, when FPGA main control chip is from memory after reads image data, read again the correction parameter in correction module, and correction parameter and view data are calculated, obtain the view data after proofreading and correct, be finally transferred to PC main frame by USB module again.
9. the bearing calibration of the Double face scanner acquisition system based on FPGA according to claim 8, is characterized in that, in described step (4), the process of PC Framework computing correction parameter is as follows:
(a) PC main frame obtains after view data, before extracting, the 500th of first pixel the walks to R, the G that the 999th row amounts to 500 row, the data of tri-passages of B in half frame images, and obtains this pixel the 500th and walk to the rgb pixel value in the every a line of the 999th row;
(b) the 500th rgb pixel value that walks to this pixel in the every a line of the 999th row is done average computing by PC main frame, obtains R
1 is equal, G
1 is equal, B
1 is equal, obtain R, the G of first pixel in front half frame images, the correction parameter of tri-kinds of color modes of B;
(c) circulation step (a) and (b) successively, until PC main frame has extracted the remaining pixel of front half frame images, and obtain R, the G of remaining each pixel in front half frame images, the correction parameter of tri-kinds of color modes of B;
(d) PC main frame extracts the 500th pixel value walking in the every a line of the 999th row of first pixel in rear half frame images;
(e) the 500th pixel value that walks to this pixel in the every a line of the 999th row is done average computing by PC main frame, obtains black
all, obtain the black correction parameter of first pixel in rear half frame images;
(f) circulation step (d), (e) successively, until PC main frame takes the remaining pixel of rear half frame images, and obtains the black correction parameter of remaining each pixel in rear half frame images;
(g) the black correction parameter of the R of front half frame images, G, B and rear half frame images is transferred to FPGA main control chip by PC main frame, for correction calculation.
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| CN110022420A (en) * | 2019-03-13 | 2019-07-16 | 华中科技大学 | A kind of image scanning system based on CIS, method and storage medium |
| CN110233948A (en) * | 2019-07-15 | 2019-09-13 | 珠海奔图电子有限公司 | Scanning device, image forming apparatus, scan method and storage medium |
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