CN104103309B - The operating method of NAND array and computer-readable non-transitory store media - Google Patents

Abstract

The invention discloses a kind of operating method of NAND array and computer-readable non-transitory store media, is the technology for illustrating to support that the reduction programming of nonvolatile memory is disturbed.A kind of three-dimensional/two-dimentional NAND array includes multiple pagings, and it is divided into multiple paging groups.Allow the memory cell within one first paging group of multiple paging groups of the access in an erasing block of three dimensional NAND array, but make the access of the memory cell within one second paging group of multiple paging groups of the access in the erasing block of three-dimensional/two-dimentional NAND array minimized.Paging in identical paging group is not adjacent to each other in three-dimensional/two-dimentional NAND array.

Description

The operating method of NAND array and computer-readable non-transitory store media

Technical field

The invention relates to the storage arrangement including memory management and system, especially a kind of behaviour of NAND array Make method and computer-readable non-transitory store media.

Background technology

Flash memory is one kind of non-volatile integrated circuit memory technology.Traditional flash memory is single using Floating gate storage Member.With becoming increasingly closer between the density increase of storage arrangement and Floating gate memory cell, neighbouring suspension joint is stored in Interference between the electric charge of grid becomes a problem.Which has limited the energy of the increase density of the flash memory based on Floating gate memory cell Power.Memory cell for another pattern of flash memory is referred to alternatively as a charge capturing storage unit, and it uses a dielectric charge Trapping layer substitutes Floating gate.

Typical flash memory cell is made up of field-effect transistor FET constructions, and it has what is separated by a passage Source electrode and drain electrode, and one include a tunnelling and be situated between with the grid of this electric charge storing construction of channel spacing one, electric charge storing construction Electric layer, electric charge storage layer (Floating gate or dielectric material) and a stop dielectric layer.It is referred to as SONOS devices according to early stage Known charge capturing memory is designed, and source electrode, drain electrode and passage are formed in a silicon body (S) that can be strip, tunnelling Dielectric layer is made up of silica (O), and electric charge storage layer is made up of silicon nitride (N), and stop dielectric layer is by silica (O) formed, and grid includes polysilicon (S).

Although other frameworks are known, flash memory device includes the NAND or NOR of AND architecture typically by using Framework is realized.NAND architecture makes it be enjoyed great popularity when being applied to data storage application because of its high density and high speed.NOR Framework is more suited to other application, such as code storage, and random bytes access therein is important.In a kind of NAND architecture In, programming process generally relies on fowler-nordheim tunneling through (Fowler-Nordheim (FN) tunneling), and needs for example big About 20 volts of high voltage, and high voltage transistor is needed to manipulate them.Additional high voltage transistor AND gate on integrated circuit Transistor for logic and other data flows is combined, and can cause the complexity of technique.And this increased complexity can instead increase The cost of feeder apparatus.

The nand memory element of cubical array in a relatively small volume characterized by having bigger memory span. But when programming a selected memory cell of NAND array, neighbouring memory cell is still disturbed by programming.Disturbed by programming Memory cell include：Memory cell in same NAND string, accessed by identical wordline and (but different in same tier Layer) semiconductor bar in memory cell, accessed and in the semiconductor of identical layer (but neighbouring lamination) by identical wordline Memory cell in bar；And still depositing in the semiconductor bar of neighbouring lamination (and different layers) is accessed by identical wordline Storage unit.

A kind of method for reducing programming interference is hot carrier injection (the memory skill of a suitable low voltage program operation Art), and the injection of hot carrier is configurable in a NAND architecture.Hot carrier injection in one NAND architecture is previously in following applications Explained in Reference Number：U. S. application Reference Number 12/797,994, the applying date are on June 10th, 2010, and it is December 15 in 2011 Day is disclosed as U.S. Patent Application Publication No. 2011/0305088；And U. S. application Reference Number 12/898,979, the applying date are On October 6th, 2010, it is to be disclosed as U.S. Patent Application Publication No. 2012/0081962, its whole on April 5th, 2012 It is incorporated by reference herein.

No matter the injection of hot carrier why, programming interference remains a problem in high-density storage.We it is expected more Further improve programming interference.

The content of the invention

A kind of reduction for supporting nonvolatile memory programs the technology of interference.

The one of this technology implements pattern as a kind of operation side for the three-dimensional/two-dimentional NAND array for including multiple pagings (page) Method, multiple pagings are divided into multiple paging groups.The method includes：

Allow multiple paging groups of the access in an erasing block of three-dimensional/two-dimentional NAND array one first paging group it Interior memory cell, but make within one second paging group of multiple paging groups of the access in the erasing block of three dimensional NAND array Memory cell access it is minimized.

Paging wherein in paging group is physically not adjacent to each other in three-dimensional/two-dimentional NAND array.

In an embodiment, the first paging group and the second paging group have the checkerboard pattern offset relative to each other.Thereby, Physically neighbouring paging will not be directed to and perform programming operation.

Allow to access and make the minimized example of access for programming and read operation.In an embodiment, in three dimensional NAND The memory cell within the first paging group in the erasing block of array allows programming operation, and in the erasing block of this array The second paging group within the programming operation of memory cell be minimized.In another embodiment, in three dimensional NAND array Allow read operation in the memory cell within the first paging group in erasing block, and the in the erasing block of this array The read operation of memory cell within two paging groups is minimized.

By being wiped with logic erasing rather than an entity to respond an erasing order of a paging, and wiped in collective afterwards Except such a paging, the various embodiments of this technology reduce the sum for the erasing operation performed by erasing block.By according to This mode reduces the sum of erasing operation, can extension fixture life-span.In the embodiment of this technology, for the first paging group institute One erasing instruction is to cause the paging with a disarmed state, this disarmed state be indicate (i) paging delay wipe with And (ii) paging is for reading and writing can not using for storage operation, untill at least delay erasing of paging.Herein In another embodiment of technology, when both first and second paging groups have been received by erasing instruction, including the two pagings The erasing block of group is to be wiped free of, and is removed for the disarmed state of all multiple paging groups.Remove disarmed state it Afterwards, read and programming operation is in order to which at least this reason is no longer prevented in real time.

In certain embodiments, paging is included in the physically neighbouring storage of more strings in three-dimensional/two-dimentional NAND array Unit.

Following three/two embodiments change the storage list of the paging between three/two different spaces axles The physical direction of member.

In an embodiment, the physically neighbouring memory cell gone here and there more is arranged to make the paging in multiple pagings Including multiple memory cell in a same memory cell layer of this array, accessed by a same word line, and by different positions Line is accessed, and any two paging of first paging group of plurality of paging group is physically mutually non-conterminous, due under At least one stated：

(i) at least intermediary's wordline position is between two pagings,

(ii) an at least intermediate storage layer position be between two pagings, and

(iii) two pagings are positioned in different memory cell layers and accessed by different wordline.

In another embodiment, the physically neighbouring memory cell gone here and there more is arranged to make one point in multiple pagings Multiple memory cell that page is included in the different layers of this array are accessed by a same word line,

Any two paging of first paging group of plurality of paging group is physically mutually non-conterminous, due to following At least one：

(i) at least intermediary's wordline position is between two pagings,

(ii) an at least intervening memory string lamination position is between two pagings, and

(iii) two pagings are shared no memory string and accessed by different wordline.

In a still further embodiment, the physically neighbouring memory cell gone here and there more is arranged to make in multiple pagings A paging include multiple memory cell in an identical layer of this array and accessed by different wordline.

Any two paging of first paging group of plurality of paging group is physically mutually non-conterminous, due to following At least one：

(i) an at least intermediate storage layer position be between two pagings,

(ii) an at least intervening memory string lamination position is between two pagings, and

(iii) two pagings are positioned in different memory cell layers and are positioned in different memory string laminations In.

Another technology for implementing pattern is a computing device, and it includes a processor, three-dimensional/two-dimentional NAND array and control Circuit processed.This memory includes multiple pagings, and it is divided into multiple paging groups.It is coupled at least one of processor and this array Control circuit allow one first paging group of multiple paging groups of the access in an erasing block of three-dimensional/two-dimentional NAND array Within multiple memory cell, but make the one the of multiple paging groups of the access in the erasing block of three-dimensional/two-dimentional NAND array The access of multiple memory cell within two paging groups is minimized.Virtual erasure block in multiple virtual erasure blocks is to be reflected As into multiple paging groups one of them.Multiple paging groups in these paging groups are included in three-dimensional/two-dimentional NAND array Physically mutually multiple pagings of these non-conterminous pagings.Paging in paging group is entity in three-dimensional/two-dimentional NAND array It is upper not adjacent to each other.

The further technology for implementing pattern is a computer-readable non-transitory store media, and it is implemented for bag Include the multiple instruction of three-dimensional/two-dimentional NAND array of multiple pagings.Three-dimensional/two-dimentional NAND array is divided into multiple paging groups. Instruction is completed when executed：

Allow multiple paging groups of the access in an erasing block of three-dimensional/two-dimentional NAND array one first paging group it Interior multiple memory cell, but make the one second of multiple paging groups of the access in the erasing block of three-dimensional/two-dimentional NAND array The access of multiple memory cell within paging group is minimized,

Paging wherein in paging group is physically not adjacent to each other in three-dimensional/two-dimentional NAND array.The present invention its He, which implements pattern and advantage, to recognize in schema, detailed description and the right that inspection is enclosed.

Brief description of the drawings

Fig. 1 is the block diagram of one of storage management system.

Fig. 2 shows an erasing block of multiple pagings, and it is mapped to an erasing block for being divided into multiple paging groups.

Fig. 3 is shown in the configuration of the storage page in a 3 D memory array parallel with a wordline.

Fig. 4 is shown in the configuration of the storage page in a 3 D memory array of the multilayer for extending through NAND string.

Fig. 5 is shown in the configuration along the storage page in a 3 D memory array of NAND string operation.

The idle NAND erasing blocks of Fig. 6 displays, so that all sub-blocks of erasing block are all idle.

The idle NAND erasing blocks of Fig. 7-Fig. 8 displays half, so that an at least sub-block turns into invalid, and remaining sub-district Block is idle.

Fig. 9-Figure 12 shows NAND erasing blocks in use, so that at least one of sub-block is in use, and Other sub-blocks are idle and/or invalid.

Figure 13-Figure 16 shows NAND erasing blocks in use, so that at least one of sub-block is in use, and Other sub-blocks are idle and/or invalid；But unlike Fig. 9-Figure 12, a different sub-block is in use.

Figure 17 shows the life cycle of the simplification of an erasing block.

Figure 18 shows the life cycle of the simplification of an erasing block；Unlike Figure 17, sub-block in use it is different suitable Sequence is as follows.

Figure 19 is the block diagram of one of computer system.

【Symbol description】

100：System

110：Application program

120：Disk file system

125：Flash translation layer

130：Original file system

140：Memory technology device archives

150：Memory/high power capacity 3D NAND Flash arrays

210：Wipe block

212、612、712、812、912：Sub-block 1

214、614、714、814、914：Sub-block 2

300、400、500：3 D memory array/NAND array

610：NAND wipes block

710：NAND wipes block

810：NAND wipes block

910：NAND wipes block

1010：NAND wipes block

1012、1112、1212、1312、1412、1512、1612、1712、1722、1732、1742：Sub-block 1

1014、1114、1214、1314、1414、1514、1614、1714、1724、1734、1744：Sub-block 2

1110、1210、1310、1410、1510、1610、1710：NAND wipes block

1720、1740、1840：Erasing block in use

1730、1830：Half idle erasing block

1750：Distribute sub-block 1

1760：Virtual erasure sub-block 1

1770：Distribute sub-block 2

1780：Entity wipes sub-block 1 and 2

1810：Idle erasing block

1820：Wipe block

1850：Distribute sub-block 2

1860：Virtual erasure sub-block 2

1870：Distribute sub-block 1

1880：Entity wipes sub-block 1 and 2

1910：Computer system

1912：Bus subsystem

1914：Processor subsystem

1916：Network interface subsystem

1918：Communication network/computer network

1920：User interface output device

1922：User interface input equipment

1924：Storage subsystem

1926：Memory sub-system

1928：Archival storage subsystem

1930：Main random access memory (RAM)

1931：Flash memory

1932：Read-only storage (ROM)

Embodiment

Refer to the attached drawing provides the detailed description of embodiment.

Fig. 1 is a data handling system 100 for combining memory (such as 3D NAND Flashes array 150 of high power capacity) Functional layer block diagram.Memory also can be a variety of nand flash memories, NOR flash memory or any suitably depositing with erasing block Reservoir device.It is segmented into this memory entities as multiple sections, so that the area that each entity section is supported by memory The minimum dimension unit of block erasing operation.One erasing block of memory can be corresponded to one or more entity sections.Citing and Speech, the capacity of each entity section of memory can be 16KB.In some examples, an erasing block of memory 150 can Including an entity section, and have and entity section, or multiple entity section identical 16KB capacity, such as 4 entities Section has 64KB total capacity, or 8 entity sections have 128KB total capacity.

To carry out in the memory of paging mode operation, each erasing block of memory may include multiple pagings (page), and each paging can be programmed or read by being stored by supported paging programming and paging read operation. For example, the nand flash memory device of 1-Gbit single-layer types storage memory cells (Single-Level-Cell, a SLC) framework It may include 1K erasing block, each block size of wiping is 128KB, and each erasing block may include 64 pagings, each Paging size is 2KB.Each paging may include for error-correcting code (ECC) or the usable additional storage space of other work((such as 64 bytes).Each erasing block may include additional storage space (such as 4KB) record corrupted paging, erasing times or other Data.

By providing a paging program command or paging reading order and the address for confirming paging to memory, dodge Depositing can be by planning and so that a paging of memory can be programmed or read.Also, by one block erasing order of offer and really Recognize an address of this block to memory, flash memory can be caused by planning memory each block can and be wiped free of.Citing and Speech, each specific paging of the 1-Gbit SLC nand flash memory devices of one can be addressed using the address of 16,16 bit address In 10 highest significant positions be the block for including specific paging address.In this 1-Gbit SLC NAND example, by carrying For a paging reading order or paging program command and confirm that 16 bit address of this paging give 1-Gbit SLC nand flash memories Device, a paging can be programmed or read.In this 1-GbitSLC NAND example, by one block erasing order of offer and really 10 highest significant positions (in 16 bit address forms) for recognizing this erasing block are wiped to 1-Gbit SLC nand flash memory devices, one Except block can be wiped free of.

System 100 includes one or more file system, and it is stored up based on multiple requests from an application program 110 Deposit, capture and update the data that are stored in memory 150.File system in this embodiment includes disk file system 120, it is, for example, file allocation table (File Allocation Table, FAT) file system, the 3rd extension file system (Third Extended File System, EXT3) or New Technology File System (New Technology File System, NTFS).File system in this embodiment also includes a kind of original (native) file system designed for flash memory 130, such as Journaled flash file system version 2 (Journaling Flash File System Version2, JFFS2), Without sequence tile images file system (Unsorted Block Image File System, UBIFS) or another quick flashing again File system (Yet Another Flash File System, YAFFS).File system 120 or 130 is read via such as one Driver (to paging read operation), a driven by program device (to paging programming operation) and an erasing driver (are used for Block erasing operation) device driver access memory 150.One software layer, such as memory technology device archives (Memory Technology Device file) 140, it is possible to provide as file system 120 or 130 and memory 150 it Between, the interface with device driver.Memory technology device archives 140 include one erasing block and sub-block management module with And related status data.Erasing block and sub-block management module, which will be wiped block and regarded as, is divided into multiple sub-blocks, and is holding Before the entity erasing of one of row erasing block, the ineffectivity of this little block in erasing block is managed (invalidation).As discussed below, invalid is software erasing or virtual erasure, and it postpones entity erasing, until Untill multiple sub-blocks physically can be wiped free of together.Memory technology device archives 140 include an operation processor and sky Free space (free space) manager.Operation processor intercepts all operations asked by flash translation layer 125, and passes through The original function provided by the memory technology device archives 140 both deposited is provided, re-established for the physical blocks under it Operation.When in the absence of having enough free spaces to complete the new programming operation from flash translation layer 125, free space Manager administration, distribution and allocation of free space again.

Shown system 100 also includes conduct in disk file system 120 and device driver (or memory technology Device archives 140) between interface flash translation layer (Flash Translation Layer) 125.Flash translation layer 125 It can perform the address conversion between the logical address of disk file system 120 and the physical address of memory 150.

In certain embodiments, flash translation layer 125 and memory technology device archives 140 are placed in as firmware In one stocking system (such as a removable memory card).The modification of the removable file system to higher order of this firmware needs Ask, use the stocking system completed with old system compatible, and enjoy the improvement in the present invention simultaneously.In other embodiments, Memory technology device archives 140 are incorporated into flash translation layer 125 and/or original file system 130.

Fig. 2 shows an erasing block of multiple pagings, and it is mapped to an erasing block for being divided into multiple paging groups.

In three-dimensional/two dimensional memory arrays one erasing block 210 include storage page (paging 0, paging 1, paging 2, point Page 3 ..., paging N).The storage page of erasing block is logically mapped multiple sub-blocks into different paging groups.Institute in figure The sub-block 1212 of the paging group 1 with physically non-conterminous paging is shown as, and there is physically non-conterminous paging The sub-block 2214 of paging group 2.The paging (such as paging 1, paging 3, paging 4, paging 6 etc.) of paging group 1 is in three-dimensional storage It is physically not adjacent to each other in array.The paging (such as paging 0, paging 2, paging 5, paging 7 etc.) of paging group 2 is deposited in three-dimensional It is physically not adjacent to each other in memory array.It is physically non-conterminous to be deposited it is meant that being configured in three-dimensional along x-axis, y-axis and z-axis Paging in memory array and not along any and direct adjacent to each other of x-axis or y-axis or z-axis.It is physically non-conterminous not arrange Except the paging being configured in along x-axis, y-axis and z-axis in 3 D memory array is close to cornerwise configuration, so that same point The position of any two paging in page group differs 1 between the two in appointing for x-axis, y-axis and z-axis.Because point in same group Page is physically non-conterminous relative to each other, therefore for phase caused by the programming operation in any paging in a paging group Programming interference with any other paging in paging group is minimum or nothing.

Although this figure only shows two sub-blocks, an erasing block can be divided into more than two sub-districts by other embodiment Block, each sub-block include the paging of a paging group, and it is physically not adjacent to each other in 3 D memory array.

Fig. 3 is shown in the configuration of the storage page in a kind of 3 D memory array 300 parallel with a wordline.

In shown NAND array 300, the physically neighbouring memory cell of more strings is arranged in a paging：Make One paging includes memory cell in a same memory cell layer of this array, and by same word line and corresponding lines is not accessed. The each of different sub-blocks (such as sub-block shown in Fig. 2) is to be configured checkerboard pattern in figure 3.

For example, the memory cell in paging 0 is to be accessed in identical memory cell layers by wordline 0, and be by Different bit lines (not showing, extend into and stretch out this figure) are accessed.

Due at least one of following reasons, any two pagings of a paging group are physically mutually non-conterminous：

(i) an at least intermediary (intervening) wordline position two pagings (such as the paging 1 that is separated by wordline 1 and point Page 9) between,

(ii) an at least intermediate storage layer position (such as is included the memory cell layers of paging 2 and separated in two pagings Paging 1 and paging 3) between, and

(iii) this two pagings are positioned in different memory cell layers and accessed by different wordline and (such as divide Page 1 and paging 4, wherein paging 1 in higher memory cell layers more next than paging 4, and paging 1 and paging 4 respectively by Wordline 0 and wordline 1 are accessed).

Fig. 4 shows the configuration of storage page in 3 D memory array 400, and it extends through the multilayer of NAND string.

In shown NAND array 400, the physically neighbouring memory cell of more strings is arranged in a paging：Make The memory cell that one paging is included in the different layers of this array is accessed by a same word line.Different sub-block (such as Fig. 2 Shown sub-block) each be disposed on checkerboard pattern in Fig. 4.

For example, the memory cell in paging 0 is to be accessed in the different layers of this array by wordline 0.

Due at least one of following reasons, any two paging of a paging group is physically mutually non-conterminous：

(i) at least intermediary's wordline position is between two pagings (such as the paging 1 and paging 9 separated by wordline 1),

(ii) an at least intervening memory string lamination position two pagings (such as be included paging 2, paging 6, paging 10, The paging 1 and paging 3 that paging M-1 memory string lamination separates) between, and

(iii) this two pagings not shared memory string and accessed by different wordline (such as paging 1 and paging 4, its Middle paging 1 and paging 4 is in different neighbouring memory string laminations；And paging 1 and paging 4 are respectively by wordline 0 and wordline 1 Accessed).The shared identical memory string lamination with paging 5, paging 9 and paging M-2 of paging 1.Paging 4 is shared to be had The identical memory string lamination of paging 0, paging 8 and paging M-3.

Fig. 5 is shown in the configuration along the storage page in a kind of 3 D memory array 500 of NAND string operation.

In shown NAND array 500, the physically neighbouring memory cell of more strings is arranged in a paging：Make The memory cell that one paging is included in an identical layer of this array is accessed by different wordline.Different sub-block (such as Sub-block shown in Fig. 2) each be configured checkerboard pattern in Figure 5.

For example, the memory cell in paging 0 be position in an identical layer of this array, accessed by wordline 0.

Due at least one of following reasons, a paging group appoint watch two pagings be physically mutually it is non-conterminous：

(i) an at least intermediate storage layer position (such as is included an intermediate storage layer of paging 5 in two pagings The paging 1 and paging 9 separated) between,

(ii) an at least intervening memory string lamination position two pagings (such as be included paging 2, paging 6, paging 10 and The paging 1 and paging 3 that the memory string lamination of paging 14 separates) between, and

(iii) this two pagings, it is positioned in different memory cell layers and is positioned in different memory strings and fold In layer (such as paging 1 and paging 4, wherein paging 1 in lower memory cell layers more next than paging 4, and paging 1 and Paging 4 is in different neighbouring memory string laminations).The shared identical with paging 5, paging 9 and paging 13 of paging 1 Memory string lamination.The shared identical memory string lamination with paging 0, paging 8 and paging 12 of paging 4.

Fig. 6 shows the NAND erasing blocks 610 of a free time (free) so that all sub-blocks for wiping block are all empty Not busy.

NAND erasing blocks 610 include sub-block 1612 and sub-block 2614.Sub-block 1612 has physically non-conterminous Paging paging group 1.Sub-block 2614 has the paging group 2 of physically non-conterminous paging.NAND erasing blocks 610 are empty Not busy, because sub-block 1612 has the paging group 1 of only free page, and sub-block 2614 has the paging group of only free page 2。

The NAND erasing blocks of Fig. 7-Fig. 8 displays one and half idle (semi-free) so that an at least sub-block is nothing Effect, and remaining sub-block is idle.

In the figure 7, NAND, which wipes block 710, includes sub-block 1712 and sub-block 2714.Sub-block 1712 has entity The paging group 1 of upper non-conterminous paging.Sub-block 2714 has the paging group 2 of physically non-conterminous paging.NAND scratching areas Block 710 is half idle, because an at least sub-block only includes free page, and at least a sub-block only includes invalid page.Sub-district Block 1712 has the paging group 1 of only invalid page, and sub-block 2714 has the paging group 2 of only free page.

In fig. 8, NAND, which wipes block 810, includes sub-block 1812 and sub-block 2814.Except the son with invalid page Beyond block is exchanged with the sub-block with free page, Fig. 8 is analogous to Fig. 7.

Fig. 9-Figure 12 shows a NAND erasing block in use so that at least one of these sub-blocks is to make In (being sub-block 1 in these cases), and other sub-blocks be it is idle and/or invalid (be sub-district in these cases Block 2).

In fig.9, NAND, which wipes block 910, includes sub-block 1912 and sub-block 2914.Sub-block 1912 has entity The paging group 1 of upper non-conterminous paging.Sub-block 2914 has the paging group 2 of physically non-conterminous paging.NAND scratching areas Block 910 is in use, because an at least sub-block includes an active page.Sub-block 1912 has effective and invalid page paging Group 1, and sub-block 2914 has the paging group 2 of only free page.

In Fig. 10, NAND, which wipes block 1010, includes sub-block 11012 and sub-block 21014.Except in use Beyond the effective and invalid page of each number of sub-block 1 is different, Figure 10 is analogous to Fig. 9.

Fig. 9 and Figure 10 and Figure 11 and Figure 12 differences at least that：Non- sub-block in use in Fig. 9 and Figure 10 It is idle (in this case, being sub-block 2), and is invalid in Figure 11 and Figure 12.

In fig. 11, NAND, which wipes block 1110, includes sub-block 11112 and sub-block 21114.Sub-block 11112 has The paging group 1 of physically non-conterminous paging.Sub-block 21114 has the paging group 2 of physically non-conterminous paging.NAND is wiped Except block 1110 is in use, because an at least sub-block includes an active page.Sub-block 11112 has effectively and empty The paging group 1 of not busy page, and sub-block 21114 has the paging group 2 of only invalid page.

In fig. 12, NAND, which wipes block 1210, includes sub-block 11212 and sub-block 21214.Figure 12 is analogous to figure 10, except effective and invalid page position of sub-block 1 in use is different, and sub-block not in use (in In this case, sub-block 2) it is idle in Fig. 10, and be invalid in fig. 12.

Figure 13-Figure 16 shows a NAND erasings block in use so that at least one of these sub-blocks be In use (being sub-block 2 in these cases), and other sub-blocks be it is idle and/or invalid (be in these cases son Block 1).Unlike Fig. 9-Figure 12, a different sub-block is in use.

In fig. 13, NAND, which wipes block 1310, includes sub-block 11312 and sub-block 21314.In fig. 14, NAND is wiped Except block 1410 includes sub-block 11412 and sub-block 21414.In fig.15, NAND, which wipes block 1510, includes sub-block 11512 and sub-block 21514.In l6 is schemed, NAND erasing blocks 1610 include sub-block 11612 and sub-block 21614.Except Beyond sub-block in use is exchanged with the sub-block in non-use, Figure 13-Figure 16 is to be analogous respectively to Fig. 9-Figure 12.

Figure 17 shows the life cycle of the simplification of an erasing block.

On Figure 17 summary, life cycle is carried out according to following orders：Idle erasing block (sub-block 1 and 2 is idle) 1710；Erasing block (sub-block 1 is in use, sub-block 2 is idle) 1720 in use；Half idle erasing block (sub-district Block 1 is invalid, sub-block 2 is idle) 1730；Erasing block (sub-block 1 is invalid, sub-block 2 is in use) 1740 in use；With And return to the erasing block (sub-block 1 and 2 is idle) 1710 of free time.

Figure 17 more detail discussion is as follows.

Idle NAND erasing blocks 1710 include sub-block 11712 and sub-block 21714.Sub-block 11712 has real The paging group 1 of non-conterminous paging on body.Sub-block 21714 has the paging group 2 of physically non-conterminous paging.NAND is wiped Block 1710 is idle, because all sub-blocks only include free page.Sub-block 11712 has point of only free page Page group 1, and sub-block 21714 has the paging group 2 of only free page.

In 1750, sub-block 1 is distributed.Idle NAND erasing blocks 1710 become the NAND erasing blocks in use 1720。

NAND erasing blocks 1720 in use include sub-block 11722 and sub-block 21724.NAND wipes block 1720 It is in use, because an at least sub-block includes an active page.Sub-block 11722 is allocated and had including at least 1 Imitate page.Sub-block 21724 still has the paging group 2 of only free page.

In 1760, sub-block 1 is virtually wiped free of.Erasing block 1720 in use becomes half idle erasing block 1730.Due to virtual erasure, sub-block 1 has a disarmed state, and this disarmed state is to indicate the paging in (i) sub-block 1 Paging in delay erasing and (ii) sub-block 1 is for reading and writing can not using for storage operation, until at least sub Untill the delay erasing of paging in block 1.

Half idle NAND erasing blocks 1730 include sub-block 11732 and sub-block 21734.NAND wipes block 1730 It is half idle, because at least a sub-block is invalid, and remaining sub-block is idle.Sub-block 11732 has There is the paging group 1 of only invalid page, and sub-block 21734 has the paging group 2 of only free page.

In 1770, sub-block 2 is distributed.Half idle NAND erasing blocks 1730 become the NAND erasing blocks in use 1740。

NAND erasing blocks 1740 in use include sub-block 11742 and sub-block 21744.NAND wipes block 1740 It is in use, because an at least sub-block includes an active page.Sub-block 11742 is invalid.Sub-block 21744 is It is allocated and including at least 1 active page.

In 1780, sub-block 1 and 2 is physically wiped free of, and includes the delay erasing of sub-block 1 invalid always.Use In NAND erasing block 1740 return back to free time NAND erasing block 1710.

Figure 18 shows the life cycle of the simplification of an erasing block；Unlike Figure 17, sub-block in use it is different suitable Sequence is as follows：Before sub-block 1 is allocated to active page, sub-block 2 is distributed into active page first.By sub-district Block 2 is distributed into after active page, and it is to be allocated to have that sub-block 2, which is virtually erased into as invalid page and sub-block 1, Active page.

On Figure 18 summary, life cycle is carried out according to following orders：Idle erasing block (sub-block 1 and 2 is idle) 1810；Distribute sub-block 21850；Erasing block (sub-block 1 is idle, sub-block 2 is in use) 1820 in use；It is virtual to wipe Except sub-block 21860；Half idle erasing block (sub-block 1 is idle, sub-block 2 is invalid) 1830；Distribute sub-block 11870； Erasing block (sub-block 1 is in use, sub-block 2 is invalid) 1840 in use；Entity wipes sub-block 1 and 21880；And Return to the erasing block (sub-block 1 and 2 is idle) 1810 of free time.

In the cycle shown in Figure 17 and Figure 18, generally, two sub-blocks in same block can't use simultaneously In.However, in fig. 17, if using all sub-blocks 1, in response to the requirement of a distribution new block, sub-block 2 can be chosen Select and distribute and be used as this new block.Similarly, in figure 18, if using all sub-blocks 2, in response to a distribution new district The requirement of block, sub-block 1 can be chosen and distribute to be used as this new block.

Figure 19 is the block diagram of computer system 1910, and it may include an erasing block and the sub-block management shown in Fig. 1 Module.

Computer system 1910 generally comprises a processor subsystem 1914, its via bus subsystem 1912 and and some Peripheral device is linked up.These peripheral devices may include that (it includes a memory sub-system 1926 and one to a storage subsystem 1924 Archival storage subsystem 1928), user interface input equipment 1922, the network interface of user interface output device 1920 and one son System 1916.Input and output device allow user to carry out interaction with computer system 1910.Network interface subsystem 1916 carries External network (including one be interfaced to communication network 1918) is interfaced to for one, and other calculating are coupled to via communication network 1918 Corresponding interface arrangement in machine system.Communication network 1918 may include the computer system and communication linkage of many interconnection (1ink).These communication linkages are probably expired air, optical link, wireless link, or any other communication on information Mechanism, but the general communication network that it is a kind of IP address corresponding (IP-based).Although in one embodiment, communication network 1918 be internet (Internet), but in other embodiments, communication network 1918 can be any appropriate computer network Network.

The entity hardware element of network interface be sometimes referred to as network adapter (Network Interface Cards, NIC), although they are not required to the pattern presence with card：For example, they can be the form of integrated circuit (IC) and connector, directly Ground connection is installed on mainboard, or the pattern of huge born of the same parents (macrocell), is produced on other yuan with computer system On the single IC for both chip of part.

User interface input equipment 1922 may include a keyboard, indicator device (such as a mouse, trace ball, touch pad or Drawing board), scanner, one be incorporated to the Touch Screen of display, audio input device (such as speech recognition system, microphone) And the input equipment of other patterns.In general, the use of term " input equipment " is intended to include entering information into meter In calculation machine system 1910 or to the device and method for being possible to pattern on computer network 1918.

User interface output device 1920 may include a display subsystem, a printer, a facsimile machine or non-vision display Device (such as audio output device).Display subsystem may include a cathode-ray tube (CRT), be, for example, a liquid crystal display (LCD) a board device, a projection arrangement or to produce other some mechanism of a visible image.Display subsystem also may be used Non-vision display is provided, such as via audio output device.In general, the use of term " output device " is intended to include Information is exported to user from computer system 1910 or to another machine or the dress for being possible to pattern of computer system Put and method.

Storage subsystem 1924 stores base program and data are formed, and it provides the function of certain embodiments of the present invention. For example, implementing the various modules of the function of certain embodiments of the present invention can be stored in storage subsystem 1924.Citing For, the erasing block and sub-block management module of implementing above-mentioned technology can be stored in storage subsystem 1924.These are soft Part module performs typically by processor subsystem 1914.

Memory sub-system 1926 generally comprises some memories, including for storage instruction and number during program performs According to main random access memory (RAM) 1930, and storage fixed instruction is in read-only storage therein (ROM) 1932. Memory sub-system 1926 also may include a flash memory 1931.Archival storage subsystem 1928 provides persistently for program and data file Storage, and may include a hard drives, floppy drive, a CD ROM light with related movable media Drive, a CD-ROM drive or movable media box (media cartridge).Implement the database of the function of certain embodiments of the present invention And module, it can be arranged on a computer-readable media (such as one or more CD-ROM), and can be by archival storage Stored by subsystem 1928.In addition, host memory subsystem 1926 includes computer instruction, when it is by processor subsystem It is to make computer system operation or perform described function when system 1914 performs.As used herein, it is discussed as " main The program and software performed in machine " or " computer " or thereon, is to be performed on processor subsystem 1914, with response to master Computer in machine memory sub-system 1926 (including Local or Remote storage area of any other this instruction and data) refers to Order and data.

Bus subsystem 1912 provide it is a kind of be used for allow computer system 1910 various elements and subsystem as expected The mechanism of communication with one another.Although bus subsystem 1912 is summarily to be shown as unified bus, the replacement of bus subsystem is real Apply example and multiple buses can be used.

Computer system 1910 itself can be various types, including a personal computer, a pocket computer, a job Stand, a computer terminal, a network computer, a television set, a mainframe computer (mainframe), a server zone (server farm) or any other data handling system or user's set.Due to the continually changing spy of computer techno-stress Property, in Figure 19 the explanation of depicted computer system 1910 simply to illustrate that the purpose of presently preferred embodiments of the present invention, and As a specific examples.A lot of other configurations of computer system 1910 may have the computer more depicted than in Figure 19 The more or less elements of system.

Although the present invention is disclosed with reference to above-mentioned preferred embodiment and example, we will be appreciated that these examples are It is intended to that a kind of illustrative and not limiting meaning is presented.We consider be familiar with art person will readily occur it is a variety of modification and Combination, these modifications and combination will fall within the spirit of the present invention and the category of appended claims.

Claims (19)

1. a kind of operating method of NAND array, the NAND array includes these pagings of multiple pagings, the wherein NAND array It is divided into multiple paging groups, comprises the following steps：

Allow multiple memory cell in one first paging group of multiple paging groups in the erasing block to the NAND array Access, but make multiple storages within one second paging group of these paging groups in the erasing block of the NAND array The access of unit is minimized (minimizing)；

Multiple pagings in wherein the plurality of paging group are not adjacent to each other in the NAND array；

One erasing instruction of one paging group is for the paging group with a disarmed state, and the disarmed state is that instruction (i) should When the storage operation for being read out and writing, these pagings of the paging group can not by the delay erasing of paging group and (ii) Use, untill the paging carries out delay erasing.

2. according to the method for claim 1,

Wherein this allows the step of access to include：Allow for these paging groups in the erasing block of the NAND array The programming operation of multiple memory cell within the first paging group, and

The wherein minimized step of the access includes：Make for these paging groups in the erasing block of the NAND array The programming operation of multiple memory cell within the second paging group is minimized.

3. according to the method for claim 1,

Wherein this allows the step of access to include：Allow for these paging groups in the erasing block of the NAND array The read operation of multiple memory cell within the first paging group, and

The wherein minimized step of the access includes, make these paging groups in the erasing block of the NAND array this The read operation of multiple memory cell within two paging groups is minimized.

4. according to the method for claim 1, wherein when both the first paging group and the second paging group have been received by this During erasing instruction, including the erasing block of the first paging group and the second paging group is to be wiped free of, and for all these The disarmed state of paging group is removed.

5. according to the method for claim 1, wherein the first paging group and the second paging group is with inclined relative to each other The checkerboard pattern of shifting.

6. according to the method for claim 1, wherein the paging in these pagings is included in the neighbour of more strings in the NAND array Near memory cell.

7. according to the method for claim 6,

The neighbouring memory cell of wherein more strings is arranged to：The paging in these pagings is set to be included in the NAND array A same memory cell layer in multiple memory cell, accessed by a same word line, and accessed by different bit lines,

Any two paging of wherein the first paging group of these paging groups is mutually non-conterminous, due at least the one of following reasons Person：

(i) at least intermediary's wordline position is between two pagings,

(ii) an at least intermediate storage layer position be between two pagings, and

(iii) two pagings are positioned in different memory cell layers and accessed by different wordline.

8. according to the method for claim 6,

The neighbouring memory cell of wherein more strings is arranged to：The paging in these pagings is set to be included in the NAND array Different layers in more strings memory cell, accessed by a same word line,

Any two paging of wherein the first paging group of these paging groups is mutually non-conterminous, due at least the one of following reasons Person：

(i) at least intermediary's wordline position is between two pagings,

(ii) an at least intervening memory string lamination position is between two pagings, and

(iii) two pagings are shared no memory string and accessed by different wordline.

9. according to the method for claim 6,

The neighbouring memory cell of wherein more strings is arranged to：The paging in these pagings is set to be included in the NAND array An identical layer in multiple memory cell, accessed by different wordline,

Any two paging of wherein the first paging group of these paging groups is mutually non-conterminous, due at least the one of following reasons Person：

(i) an at least intermediate storage layer position be between two pagings,

(ii) an at least intervening memory string lamination position is between two pagings, and

(iii) two pagings are positioned in different memory cell layers and are positioned in different memory string laminations.

10. a kind of computer-readable non-transitory (non-transitory) store media, it is implemented for including multiple The multiple instruction of one NAND array of paging, the wherein NAND array are divided into multiple paging groups, and these instructions are when executed Carry out：

Allow multiple depositing within one first paging group of multiple paging groups of the access in an erasing block of the NAND array Storage unit, but make multiple storages within one second paging group of these paging groups in the erasing block of the NAND array The access of unit is minimized,

Multiple pagings wherein in the paging group are not adjacent to each other in the NAND array；

One erasing instruction of a wherein paging group is for the paging group with a disarmed state, and the disarmed state is instruction (i) the delay erasing of the paging group and (ii) are when the storage operation for being read out and writing, these points of the paging group Page can not use, untill the paging carries out delay erasing.

11. computer-readable non-transitory store media according to claim 10,

Wherein this allows the step of access to include：Allow for these paging groups in the erasing block of the NAND array The programming operation of multiple memory cell within the first paging group, and

The wherein minimized step of the access includes：Do not allow for these pagings in the erasing block of the NAND array The programming operation of multiple memory cell within the second paging group of group.

12. computer-readable non-transitory store media according to claim 10,

Wherein this allows the step of access to include：Allow for these paging groups in the erasing block of the NAND array The read operation of multiple memory cell within the first paging group, and

The wherein minimized step of the access includes：Do not allow for these pagings in the erasing block of the NAND array The read operation of multiple memory cell within the second paging group of group.

13. computer-readable non-transitory store media according to claim 10,

Wherein, when both the first paging group and the second paging group have been received by the erasing instruction, including first paging The erasing block of group and the second paging group is wiped free of, and is removed for the disarmed state of all these paging groups.

14. computer-readable non-transitory store media according to claim 10, wherein the first paging group and The second paging group has the checkerboard pattern offset relative to each other.

15. computer-readable non-transitory store media according to claim 10, point wherein in these pagings Page is included in the neighbouring memory cell of more strings in the NAND array.

16. computer-readable non-transitory store media according to claim 15,

The neighbouring memory cell of wherein more strings is arranged to：The paging in these pagings is set to be included in the NAND array A same memory cell layer in multiple memory cell, accessed by a same word line, and accessed by different bit lines,

Any two paging of wherein the first paging group of these paging groups is mutually non-conterminous, due to

(i) at least intermediary's wordline position is between two pagings,

(ii) an at least intermediate storage layer position be between two pagings, and

(iii) two pagings be positioned in different memory cell layers and by different wordline access at least within it One.

17. computer-readable non-transitory store media according to claim 15,

The neighbouring memory cell of wherein more strings is arranged to：The paging in these pagings is set to be included in the NAND array Multiple memory cell in different layers, are accessed by a same word line,

Any two paging of wherein the first paging group of these paging groups is mutually non-conterminous, due to

(i) at least intermediary's wordline position is between two pagings,

(ii) an at least intervening memory string lamination position is between two pagings, and

(iii) two pagings share no memory string and access at least one by different wordline.

18. computer-readable non-transitory store media according to claim 15,

The neighbouring memory cell of wherein more strings is arranged to：The paging in these pagings is set to be included in the NAND array Multiple memory cell in one identical layer, are accessed by different wordline,

Any two paging of wherein the first paging group of these paging groups is mutually non-conterminous, due to：

(i) an at least intermediate storage layer position be between two pagings,

(ii) an at least intervening memory string lamination position is between two pagings, and

(iii) two pagings are positioned in different memory cell layers and are positioned in different memory string laminations extremely It is one of few.

19. a kind of computing device, including：

One processor；

These pagings of one NAND array, including multiple pagings, the wherein NAND array are divided into multiple paging groups；And

Control circuit, is coupled at least one of the processor and the NAND array, and the control circuit allows access in the NAND Multiple memory cell within one first paging group of multiple paging groups in one erasing block of array, but make access at this The access of multiple memory cell within one second paging group of these paging groups in the erasing block of NAND array is minimum Change,

Virtual erasure block in plurality of virtual erasure block is mapped into one of these paging groups, these points Paging group in page group includes the paging come in these pagings mutually not adjacent to each other in the comfortable NAND array；

Paging in these paging groups is not adjacent to each other in the NAND array；And

One erasing instruction of one paging group is for the paging group with a disarmed state, and the disarmed state is that instruction (i) should When the storage operation for being read out and writing, these pagings of the paging group can not by the delay erasing of paging group and (ii) Use, untill the paging carries out delay erasing.