CN104076811A - Test device and method of simulation iic chip - Google Patents
Test device and method of simulation iic chip Download PDFInfo
- Publication number
- CN104076811A CN104076811A CN201410259698.9A CN201410259698A CN104076811A CN 104076811 A CN104076811 A CN 104076811A CN 201410259698 A CN201410259698 A CN 201410259698A CN 104076811 A CN104076811 A CN 104076811A
- Authority
- CN
- China
- Prior art keywords
- iic
- unit
- equipment
- analog
- checked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention discloses a test device of a simulation iic chip. The test device of the simulation iic chip comprises a control unit, a communication unit, a configuration unit and an iic simulation response unit, wherein three communication ends of the control unit are connected with the communication unit, the configuration unit and the iic simulation response unit respectively, the iic simulation response unit is connected with an iic secondary interface unit, and the iic secondary interface unit carries out data communication with an iic main interface unit of equipment to be tested through an iic bus. The test device of the simulation iic chip can reduce interference of actual iic peripheral equipment devices, various iic peripheral equipment devices can be simulated through the equipment, and the efficiency of detecting whether the embedded equipment is normal or not is obviously improved.
Description
Technical field
The present invention relates to iic (Inter-Integrated Circuit, IC bus) testing of equipment technical field, refer to particularly a kind of testing apparatus and method of the iic of simulation chip.
Background technology
Iic bus is applied very extensive in embedded system, for the control iic peripherals of verifying that can embedded device correct, in research and development, test, the production phase of embedded device, embedded device all will be tested and verify for these iic peripherals.Current conventional method is that the iic interface of embedded device is directly connected and is detected with the iic interface of corresponding various iic peripherals, but iic type of peripheral device is a lot, be difficult to various iic peripherals all to carry out connecting test, and which needs manual physical connection, and detection efficiency is low.
Summary of the invention
Object of the present invention is exactly a kind of testing apparatus and the method that the iic of simulation chip will be provided, this equipment and method can reduce the intervention of actual iic peripherals device, just can simulate various iic peripherals devices by an equipment, obviously improve the whether normal efficiency of detection embedded device.
For realizing this object, the testing apparatus of the designed simulation iic chip of the present invention, it is characterized in that: it comprises control module, communication unit, dispensing unit and iic analog response unit, wherein, control module connects respectively communication unit, dispensing unit and iic analog response unit, described iic analog response unit is connected with iic from interface unit, and described iic can carry out data communication by the iic master interface unit of iic bus and equipment to be checked from interface unit.
The method of the testing apparatus of utilizing above-mentioned simulation iic chip to testing equipment to be checked, is characterized in that, it comprises the steps:
Step 1: the testing apparatus electrifying startup of simulation iic chip, the testing apparatus of this simulation iic chip is worked from the mode of equipment with iic, and equipment to be checked is worked in the mode of iic main equipment;
Step 2: the iic peripherals that host computer is simulated as required generates corresponding analog device configuration information, and above-mentioned analog device configuration information is stored in dispensing unit by communication unit and by control module;
Step 3: control module is loaded into the analog device configuration information of storing in dispensing unit in iic analog response unit, now iic analog response unit can be according to above-mentioned analog device configuration information iic peripherals that is virtually reality like reality;
Step 4: the iic peripherals type that equipment to be checked is simulated as required sends addressed command to iic analog response unit by iic bus;
Step 5:iic analog response unit receives after addressed command, compare with the device type address information in analog device configuration information in iic analog response unit, as the device type address information in addressed command and analog device configuration information matches, iic analog response unit is to device replied acknowledge character to be checked, otherwise do not reply, now test process finishes;
Step 6: equipment to be checked passes through iic bus to the transmit operation order of iic analog response unit, the data content that aforesaid operations order is replied is determined in iic analog response unit according to described analog device configuration information, and by reply bus frequency that the content of data press the definite reply data of analog device configuration information by iic bus transfer to equipment to be checked;
Step 7: equipment to be checked receives above-mentioned reply data and completes test process.
After above-mentioned steps 7 completes, repeat step 4～step 7, complete the response test to the various iic devices of equipment to be checked.
Beneficial effect of the present invention:
1, the present invention, by import analog device configuration information in the testing apparatus of simulation iic chip, makes the testing apparatus of iic chip can simulate various real simulation iic devices, avoids in development& testing, uses true device to connect.The iic peripherals that can simulate as required by host computer generates corresponding analog device configuration information, has reached the object of simulation polytype device.
2, the present invention can reduce the intervention of practical devices, does not rely on concrete device physics, simulates the testing apparatus of iic peripherals by access, reaches the demand that meets exploitation and pressure test.Sometimes cannot obtain the concrete model of iic peripherals, while only having analog device configuration information, this equipment is alternative meeting the demands also.
3, the testing apparatus self of simulation iic chip of the present invention is independently-powered, the problem of the chip operating voltage that will consider while thering is no true device access.
Brief description of the drawings
Fig. 1 is the structural representation of the present invention while using;
Wherein, 1-control module, 2-communication unit, 3-dispensing unit, 4-iic analog response unit, 5-iic are from interface unit, 6-equipment to be checked, 7-iic master interface unit, 8-iic bus, 9-host computer.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail:
A kind of testing apparatus of simulating iic chip as shown in Figure 1, it comprises control module 1, communication unit 2, dispensing unit 3 and iic analog response unit 4, wherein, control module 1 connects respectively communication unit 2, dispensing unit 3 and iic analog response unit 4, described iic analog response unit 4 is connected with iic from interface unit 5, described iic is from interface unit 5 can by iic bus 8, (equipment 6 to be checked be embedded device with equipment 6 to be checked, there is the function of iic main equipment, externally be connected from equipment with iic by iic bus) iic master interface unit 7 carry out data communication.Described communication unit 2 is for realizing the data communication between host computer 9 and control module 1.
In technique scheme, iic analog response unit 4 is for simulating iic peripherals, and the iic protocol package that equipment 6 to be checked is sent by iic bus 8 is responded.Iic analog response unit 4 is a FPGA (Field-Programmable Gate Array, field programmable gate array), iic analog response unit 4 is stored in local dispensing unit 3 from host computer 9 receives analog device configuration information by communication unit 2, using the default configuration starting as next time, by data bus, config update is arrived to iic analog response unit 4 simultaneously.
The iic protocol package that iic analog response unit 4 sends equipment 6 to be checked is analyzed, and according to analog device configuration information, it is responded.Iic analog response unit 4 uses field programmable gate array to realize, to guarantee multipath concurrence execution.Sampling to clock bus in iic analog response unit 4, determines clock frequency according to clock bus sampled value, and take out according to this data in bidirectional data line, and determine the bus frequency of reply content and reply data according to analog device configuration information.
The method of the testing apparatus of utilizing above-mentioned simulation iic chip to testing equipment to be checked, it comprises the steps:
Step 1: the testing apparatus electrifying startup of simulation iic chip, the testing apparatus of this simulation iic chip is worked from the mode of equipment with iic, and equipment 6 to be checked is worked in the mode of iic main equipment;
Step 2: the iic peripherals that host computer 9 is simulated as required generates corresponding analog device configuration information, and above-mentioned analog device configuration information is stored in dispensing unit 3 by communication unit 2 and by control module 1;
Step 3: control module 1 is loaded into the analog device configuration information of dispensing unit 3 interior storages in iic analog response unit 4, now iic analog response unit 4 can be according to above-mentioned analog device configuration information iic peripherals that is virtually reality like reality;
Step 4: the iic peripherals type that equipment 6 to be checked is simulated as required sends addressed command by iic bus 8 to iic analog response unit 4;
Step 5:iic analog response unit 4 receives after addressed command, compare with the device type address information in analog device configuration information in iic analog response unit 4, as the device type address information in addressed command and analog device configuration information matches, acknowledge character is replied to equipment 6 to be checked in iic analog response unit 4, otherwise do not reply, now test process finishes (now can not save the resource of system to equipment 6 return informations to be checked);
Step 6: equipment 6 to be checked passes through iic bus 8 to the 4 transmit operation orders of iic analog response unit, the data content that aforesaid operations order is replied is determined in iic analog response unit 4 according to described analog device configuration information, and the content of replying data is transferred to equipment 6 to be checked by the bus frequency of the definite reply data of analog device configuration information by iic bus 8;
Step 7: equipment 6 to be checked receives above-mentioned reply data and completes test process.
In technique scheme, analog device configuration information comprises device type address information, bus frequency information and addressing address information.
After above-mentioned steps 7 completes, repeat step 4～step 7, complete the response test to the various iic devices of equipment to be checked.
The content that this instructions is not described in detail belongs to the known prior art of professional and technical personnel in the field.
Claims (4)
1. simulate the testing apparatus of iic chip for one kind, it is characterized in that: it comprises control module (1), communication unit (2), dispensing unit (3) and iic analog response unit (4), wherein, control module (1) connects respectively communication unit (2), dispensing unit (3) and iic analog response unit (4), described iic analog response unit (4) is connected with iic from interface unit (5), described iic can carry out data communication by iic bus (8) and the iic master interface unit (7) of equipment to be checked (6) from interface unit (5).
2. the testing apparatus of simulation iic chip according to claim 1, is characterized in that: described communication unit (2) is for realizing the data communication between host computer (9) and control module (1).
3. utilize described in claim 2 and simulate the testing apparatus of iic chip to a method for testing equipment to be checked, it is characterized in that, it comprises the steps:
Step 1: the testing apparatus electrifying startup of simulation iic chip, the testing apparatus of this simulation iic chip is worked from the mode of equipment with iic, and equipment to be checked (6) is worked in the mode of iic main equipment;
Step 2: the iic peripherals that host computer (9) is simulated as required generates corresponding analog device configuration information, and above-mentioned analog device configuration information is stored in dispensing unit (3) by communication unit (2) and by control module (1);
Step 3: control module (1) is loaded into the analog device configuration information of storage in dispensing unit (3) in iic analog response unit (4), and now iic analog response unit (4) can be according to above-mentioned analog device configuration information iic peripherals that is virtually reality like reality;
Step 4: the iic peripherals type that equipment to be checked (6) is simulated as required sends addressed command to iic analog response unit (4) by iic bus (8);
Step 5:iic analog response unit (4) receives after addressed command, with iic analog response unit (4) in analog device configuration information in device type address information compare, as the device type address information in addressed command and analog device configuration information matches, iic analog response unit (4) reply acknowledge character to equipment to be checked (6), otherwise do not reply, now test process finishes;
Step 6: equipment to be checked (6) passes through iic bus (8) to iic analog response unit (4) transmit operation order, the data content that aforesaid operations order is replied is determined in iic analog response unit (4) according to described analog device configuration information, and the content of replying data is transferred to equipment to be checked (6) by the bus frequency of the definite reply data of analog device configuration information by iic bus (8);
Step 7: equipment to be checked (6) receives above-mentioned reply data and completes test process.
4. method of testing according to claim 3, is characterized in that: after above-mentioned steps 7 completes, repeat step 4～step 7, complete the response test to the various iic devices of equipment to be checked.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410259698.9A CN104076811B (en) | 2014-06-12 | 2014-06-12 | Test device and method of simulation iic chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410259698.9A CN104076811B (en) | 2014-06-12 | 2014-06-12 | Test device and method of simulation iic chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104076811A true CN104076811A (en) | 2014-10-01 |
| CN104076811B CN104076811B (en) | 2017-01-25 |
Family
ID=51598133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410259698.9A Active CN104076811B (en) | 2014-06-12 | 2014-06-12 | Test device and method of simulation iic chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104076811B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114048520A (en) * | 2022-01-11 | 2022-02-15 | 沐曦集成电路(上海)有限公司 | Detection system for cross-chip access control |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101158708A (en) * | 2007-10-23 | 2008-04-09 | 无锡汉柏信息技术有限公司 | Multiple chips automatic test method based on programmable logic device |
| CN101398467A (en) * | 2007-09-26 | 2009-04-01 | 鸿富锦精密工业（深圳）有限公司 | Internal integrate circuit bus interface test system and method |
| CN201876522U (en) * | 2009-12-31 | 2011-06-22 | 杭州士兰微电子股份有限公司 | General test equipment |
-
2014
- 2014-06-12 CN CN201410259698.9A patent/CN104076811B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101398467A (en) * | 2007-09-26 | 2009-04-01 | 鸿富锦精密工业（深圳）有限公司 | Internal integrate circuit bus interface test system and method |
| CN101158708A (en) * | 2007-10-23 | 2008-04-09 | 无锡汉柏信息技术有限公司 | Multiple chips automatic test method based on programmable logic device |
| CN201876522U (en) * | 2009-12-31 | 2011-06-22 | 杭州士兰微电子股份有限公司 | General test equipment |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114048520A (en) * | 2022-01-11 | 2022-02-15 | 沐曦集成电路(上海)有限公司 | Detection system for cross-chip access control |
| CN114048520B (en) * | 2022-01-11 | 2022-04-08 | 沐曦集成电路(上海)有限公司 | Detection system for cross-chip access control |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104076811B (en) | 2017-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7848899B2 (en) | Systems and methods for testing integrated circuit devices | |
| CN105738854B (en) | The analog memory test board system and test method of intelligent electric meter Embedded Application | |
| CN105446847B (en) | A kind of automatization test system and its method of ARINC659 buses | |
| CN105091927A (en) | All-liquid-crystal automobile instrument automatic test platform | |
| CN103308846B (en) | Method and device for detecting functional performance of integrated chip based on model identification | |
| CN113407393B (en) | Chip verification method, terminal device, verification platform and storage medium | |
| CN114662427B (en) | Debugging method and device for logic system design | |
| CN103778038A (en) | Method and system for verifying cloud test and remote monitoring integrated circuit device | |
| CN106842152A (en) | Airborne fire control radar online system failure diagnosis | |
| CN103514074A (en) | MVB network card development method and platform | |
| US20230035673A1 (en) | Information processing system, information processing apparatus, use method of information processing apparatus, user terminal, and program therefor | |
| WO2016184170A1 (en) | Smi interface device debugging apparatus and method, and storage medium | |
| CN104076811A (en) | Test device and method of simulation iic chip | |
| CN102436186B (en) | Performer simulator and satellite closed loop simulation system with performer simulator | |
| CN204244262U (en) | Based on the consistency test device of IEC 61850 configuration file of NI CRIO platform | |
| CN104717093B (en) | Method for managing an electrical device and a system for managing such a device | |
| US20140215106A1 (en) | Svid data test system and method | |
| CN103165405A (en) | Mutli-dimensional variable code real-time generation method through general purpose interface bus (GPIB) interface | |
| CN111541589B (en) | Method, device and equipment for testing expansion module interface of intelligent terminal | |
| CN104731671B (en) | A kind of verification device and method of wrong plug device and method, error-correcting code circuit | |
| CN111124897B (en) | Method for generating reusable simulation interface model | |
| CN103870368A (en) | SAS (Serial Attached SCSI (small computer system interface)) expander testing system and method | |
| CN102411527B (en) | Detecting method for image-processing chip, developing plate and detecting system | |
| CN105376117A (en) | FC switch chip data monitoring test method | |
| TWI486595B (en) | Wireless one-to-many testing system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Hubei Province, Wuhan City, South Lake Road 430070 Hongshan District No. 53 WCMC agricultural city shop floor 4 Patentee after: Wuhan fine test electronics group Limited by Share Ltd Address before: Hubei Province, Wuhan City, South Lake Road 430070 Hongshan District No. 53 WCMC agricultural city shop floor 4 Patentee before: Wuhan Jingce Electronic Technology Co., Ltd. |