CN104051528B - Intra-band tunnel FET - Google Patents

Intra-band tunnel FET Download PDF

Info

Publication number
CN104051528B
CN104051528B CN201310303452.2A CN201310303452A CN104051528B CN 104051528 B CN104051528 B CN 104051528B CN 201310303452 A CN201310303452 A CN 201310303452A CN 104051528 B CN104051528 B CN 104051528B
Authority
CN
China
Prior art keywords
source area
drain region
channel region
band
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310303452.2A
Other languages
Chinese (zh)
Other versions
CN104051528A (en
Inventor
戈本·多恩伯斯
克里希纳·库马尔·布瓦尔卡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/863,489 external-priority patent/US9711632B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN104051528A publication Critical patent/CN104051528A/en
Application granted granted Critical
Publication of CN104051528B publication Critical patent/CN104051528B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/068—Nanowires or nanotubes comprising a junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66469—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present disclosure relates to an intra-band tunnel FET, which has a symmetric FET that is able to provide for a high drive current. In some embodiments, the disclosed intra-band tunnel FET has a source region having a first doping type and a drain region having the first doping type. The source region and the drain region are separated by a channel region. A gate region may generate an electric field that varies the position of a valence band and/or a conduction band in the channel region. By controlling the position of the valence band and/or the conduction band of the channel region, quantum mechanical tunneling of charge carries between the conduction band in the source region and in the drain region or between the valence band in the source region and in the drain region can be controlled.

Description

Band inner tunnel FET
The reference of related application
The application is that requirement Gerben Doornbos and Krishna Kumar Bhuwalka were carried on March 13rd, 2013 The provisional application Ser.No of entitled " the Intra-Band Tunnel FET " that hand over is the non-provisional of 61/778,634 priority Application, entire contents are hereby expressly incorporated by reference.
Technical field
This invention relates generally to technical field of semiconductors, more particularly, to semiconductor devices and forming method thereof.
Background technology
Field-effect transistor（FET）In being widely used in integrated chip.FET includes source electrode, drain and gate.By biasing Apply to grid, the electric current between source electrode and drain electrode can be controlled.When transistor is in subthreshold region（That is, for less than threshold The gate source voltage of threshold voltage）When interior, the subthreshold value drain current of FET is the electric current flowed between the source electrode of FET and drain electrode.By The ratio between conducting electric current and cut-off current is improved in very big sub-threshold slope, so it is oblique to it is generally desirable to very big subthreshold value Rate（That is, the subthreshold value of very little swings）, it therefore reduces leakage current.
As semi-conductor industry reduces the size of transistor, supply voltage is also reduced, to reduce power consumption and retainer The reliability of part.Reduce the grid swing that supply voltage is reduced between the conducting of device and cut-off state.For preventing property Can reduce, threshold voltage can be reduced.However, threshold voltage reduction is the function of subthreshold value drain current, therefore, according to subthreshold The finiteness that value swings is defined to threshold voltage reduction.
The content of the invention
Defect in the presence of in order to solve prior art, according to an aspect of the present invention, there is provided a kind of band inner tunnel Field-effect transistor（TFET）Device, including：Source area, is spaced apart by channel region with drain region, wherein, the source area, The drain region and the channel region have the energy band that energy barrier is formed between the source area and the drain region to have There is conduction band offset amount different from valence band offset amount；And gate regions, it is configured to generate the electricity for changing the energy barrier , to selectively allow for the quantum mechanics tunnelling of the electronics in conduction band, or the amount for selectively allowing for hole in valence band Sub- mechanics tunnelling.
At this with interior TFET devices, the gate regions are located at the raceway groove between the source area and the drain region At position above area.
At this with interior TFET devices, the gate regions are parallel with the flowing of the electric charge carrier in the channel region Length on direction is between about 4nm and about 10nm.
At this with interior TFET devices, the gate region is in by the source area or the drain region and the raceway groove At the position that interval separates.
At this with interior TFET devices, the first doping type of the channel region and the source area and the drain region Second doping type is contrary.
In this is with interior TFET devices, the value of the conduction band offset amount is in about 0.1eV（Electron-volt）About between 0.2eV In the range of, and the value of the valence band offset amount is greater than about 0.5eV.
At this with interior TFET devices, the source area and the drain region have N-shaped doping content；And the source electrode The valence band offset amount between area and the channel region is the conduction band offset between the source area and the channel region At least twice of amount.
At this with interior TFET devices, the source area and the drain region include GaAs or antimony GaAs；And institute Channel region is stated including aluminium arsenide, selenizing or indium phosphide.
At this with interior TFET devices, the source area and the drain region have p-type doping content；And the source electrode Conduction band offset amount between area and the channel region be valence band offset amount between the source area and the channel region at least Twice.
At this with interior TFET devices, the source area and the drain region include indium arsenide aluminium or indium arsenide；And institute Channel region is stated including indium phosphide or antimony aluminium arsenide.
According to a further aspect in the invention, there is provided a kind of band inner tunnel field-effect transistor（TFET）Device, including：Source Polar region, including the source electrode compound with two or more semiconductor elements, the source area has the first doping type and the One band gap magnitude；Drain region, including the drain electrode compound with two or more semiconductor elements, the source area has described One doping type and the second band gap magnitude；Channel region, including the raceway groove compound with two or more semiconductor elements and is located at Between the source area and the drain region, the 3rd band gap magnitude of the channel region is more than first band gap magnitude and described second Band gap magnitude, the 3rd band gap magnitude forms energy barrier between the source area and the drain region；And gate regions, matched somebody with somebody Be set to generation electric field, the conduction band in conduction band and the drain region of the electric field controls electric charge carrier in the source area it Between or the source area in valence band and the drain region in valence band between quantum mechanics tunnelling.
At this with interior TFET devices, the gate regions are located at the raceway groove between the source area and the drain region At position above area.
At this with interior TFET devices, the gate region is in by the source area or the drain region and the raceway groove At the position that interval separates.
In this is with interior TFET devices, wherein, the source area and the drain region are included selected from GaAs, antimony arsenic Two or more semiconductor elements in the group that gallium, indium arsenide aluminium or indium arsenide are constituted.
In this is with interior TFET devices, wherein, the channel region is included selected from aluminium arsenide, zinc selenide, indium phosphide or antimony Two or more semiconductor element in the group that aluminium arsenide is constituted.
At this with interior TFET devices, the source area is included at the position extended along the rotary shaft with substrate transverse Semiconductor body over the substrate is set；The channel region is positioned adjacent at the position of the semiconductor body, described Channel region opens the radius bigger than the semiconductor body with the new ro-tational axis；And the drain region is positioned adjacent to institute State at the position of channel region, the radius bigger than the channel region is opened in the drain region with the new ro-tational axis.
This is further included with interior TFET devices：First distance piece, is arranged between the substrate and the drain region；With And second distance piece, it is arranged between the semiconductor body and the channel layer and drain contacts, the drain contacts It is electrically connected to the drain region.
According to another aspect of the invention, an a kind of method of the formation with inner tunnel field-effect transistor has been put forward, including：Shape Into the source area with the first doping type；Form the drain region with the first doping type；Formed be located at the source area and Channel region between the drain region；And gate regions are formed, the gate regions are configured to generate control electronics or hole exists The electric field of the quantum mechanics tunnelling between the source area and the drain region, wherein, the source area, the drain region and The channel region has the conduction band offset amount different from valence band offset amount, to be formed between the source area and the drain region Energy barrier, so as to selectively allowing for the quantum mechanics tunnelling of the electronics in conduction band or selectively allowing in the valence band The quantum mechanics tunnelling in hole.
In the method, the value of the conduction band offset amount is between about 0.1eV and about 0.2eV and described The value of valence band offset amount is greater than about 0.5eV.
In the method, the source area, the drain region and the channel region include partly being led with two or more The compound of element of volume.
Description of the drawings
Fig. 1 illustrates the interband shown for during conducting state and cut-off state（inter-band）Tunnel field-effect is brilliant Body pipe（FET）Energy band diagram band diagram.
Fig. 2 is illustrated in disclosed band（intra-band）The block diagram of some embodiments of tunnel FET.
Fig. 3 A to Fig. 3 C illustrate some embodiments of N-shaped with inner tunnel FET.
Fig. 4 A to Fig. 4 C illustrate some embodiments of p-type with inner tunnel FET.
Fig. 5 A and Fig. 5 B are illustrated and are configured to perform linear tunnel（line tunneling）Disclosed band inner tunnel Some embodiments of FET.
Fig. 6 A and Fig. 6 B are illustrated including some embodiments with inner tunnel FET disclosed in nano wire.
Fig. 7 is the flow chart of some embodiments of the method with inner tunnel FET to form disclosed.
Specific embodiment
It is described with reference to the drawings herein, wherein, similar reference number is generally used for specifying similar component, and various Structure has not necessarily been drawn to scale.In the following description, for purposes of explanation, a large amount of details are illustrated, in order to manage Solution.It should be understood that the details of accompanying drawing is not intended to limit of the invention, but non-limiting example.For example, however, this area is general Lead to it is to be understood by the skilled artisans that one or more sides specifically described herein can be realized by these details of less degree Face.In other instances, known structure and device are shown in form of a block diagram, in order to understand.
Currently, the scale down of CMOS technology is faced due to mos field effect transistor（MOSFET）Device The sub-threshold slope of part（SS）The challenge that brought of non-telescoping property.The device of the feature with precipitous sub-threshold slope is presented Fast transition and extendible supply voltage between cut-off state and conducting state.However, due to temperature dependency（That is, exist Subthreshold value is limited under room temperature by KT/q to swing to be about 60mV/dec）Caused by conventional MOSFET device sub-threshold slope Limited.
In traditional FET, subthreshold value swings and be never less than about at room temperature 60mV/decade（Decade）Thermoae limit Value.In the FET that switching is caused by quantum mechanics tunnelling, the thermoae limit value can be suppressed.So as to as conventional MOS FET crystal The potential selection of pipe, the interband tunnel FET worked based on quantum mechanics tunnelling is arisen at the historic moment.Interband tunnel FET has without temperature Dependent low subthreshold value swings, and thus allows high switch speed and supply voltage scaling.Interband tunnel FET includes the poles of PIN bis- Pipe, the PIN diode has the source area of the first doping type and with second doping type contrary with the first doping type Drain region.Channel region is located between source area and drain region, and gate region is in channel region top.Source area, channel region And drain region can have the band gap of formed objects so that channel region forms homojunction with source area and drain region.
Fig. 1 illustrates the energy band diagram 100 and 110 of the operation for showing interband tunnel FET.Including electronics 112 and the electricity in hole 114 Sub- hole is to being formed in the source area 102 and drain region 106 of interband FET.
If shown in band Figure 100, under " cut-off state ", due to the energy barrier in channel region 104 for conduction band CB and It is too wide for interband tunnelling 108 between valence band VB, so electric charge carrier（That is, electronics 112 and hole 114）Can not be from source electrode The tunnelling of area 102（tunnel）Reach drain region 106.However, working as suitable bias voltage（For example, very big positive bias）It is applied to grid During terminal, electric field is generated, the electric field makes the conduction band CB in channel region 104 and the bending of valence band VB, to reduce the width of energy barrier, And interband TFET is changed into " conducting state ".In the on-state, valence band of the electric charge carrier in source area 102（VB）With The conduction band of drain region 106（CB）Between quantum mechanics tunnelling 116.Electronics 112 is driven to right side, and hole 114 is driven to Left side, so as to each contribute to the driving current of interband FET.
Although interband tunnel FET has the sub-threshold slope for being independent of temperature, due between valence band VB and conduction band CB Low tunneling rate（For example, less than 30%）, cause interband tunnel FET to face the basic restriction to driving current.And, interband tunnel Road FET is substantially asymmetric so that source area and drain region can not exchange.The asymmetry of interband tunnel FET will be designed The use with inner tunnel FET is forced in restriction.
So as to the present invention relates to band inner tunnel FET, it includes that the asymmetric tunnel FET of high driving current can be provided.One In a little embodiments, disclosed band inner tunnel FET includes：Source area with the first doping type and with the first doping type Drain region.Source area and drain region are spaced apart by channel region.Gate regions are configured to generate the valence band changed in channel region And/or the electric field of the position of conduction band.The position of valence band and/or conduction band in by controlling channel region, can control charge carriers The quantum mechanics tunnel between valence band between conduction band of the son in source area and in drain region or in source area and in drain region Wear.
Fig. 2 illustrates disclosed band inner tunnel field-effect transistor（FET）The block diagram of 200 some embodiments.
Band inner tunnel FET200 includes source area 202 and drain region 206.Source area 202 and drain region 206 have first to mix Miscellany type（For example, N-shaped doping or p-type doping）.In certain embodiments, source area 202 and drain region 206 can include having The identical material of the first doping type.Channel region 204 is arranged between source area 202 and drain region 206, generates asymmetric tunnel FET（This is because source area 202 and drain region 206 have identical doping type）.In certain embodiments, channel region 204 The intrinsically doped semi-conducting material that there is no obvious dopant can be included.In other embodiments, channel region 204 can be with Including with the first doping type（For example, forming N+/N/N+ devices）Semi-conducting material.In other embodiments, raceway groove Area 204 can include the second doping type for having different from the first doping type（For example, p-type doping or N-shaped doping）Half Conductor material.
Gate regions 208 are configured to the electric charge carrier of the position for controlling to be located between source area 202 and drain region 206 Flowing.In certain embodiments, gate regions 208 can have grid length Ig, its along with electric charge carrier in channel region 204 The direction that the direction of middle flowing is parallel extends, between about 4nm and about 10nm.In certain embodiments, channel region 204 thickness tcBetween about 4nm and about 40nm.
In certain embodiments, channel region 204 has the first band gap, and the band gap of source area 202 and drain region 206 is less than First band gap of channel region 204.The different band gap of channel region 204 cause between source area 202 and channel region 204 and channel region Double heterojunction between 204 and drain region 206.In certain embodiments, source area 202 has identical band gap with drain region 206. In other embodiments, source area 202 and drain region 206 can have the different band gap different from the first band gap.
The energy band of source area 202, channel region 204 and drain region 206 has the shape between source area 202 and drain region 206 Into the feature of energy barrier（For example, band gap and fermi level）.Energy barrier is asymmetric so that it has for conduction band First offset value（That is, conduction band offset amount）With the second different offset value for valence band（That is, valence band offset amount）.One In a little embodiments, conduction band offset amount is at least twice of valence band offset amount.For example, the value of conduction band offset amount can be more than 0.5eV （Electron-volts）, and the value of valence band offset amount can be between about 0.1eV and 0.2eV.In other embodiments, valence band is inclined Shifting amount is at least twice of conduction band offset amount.For example, the value of conduction band offset amount can be between about 0.1eV and 0.2eV, and valency Value with side-play amount can be more than 0.5eV.
Gate contact is configured to grid voltage VGIt is selectively provided to gate regions 208.Grid voltage VGSo that grid Polar region 208 generates the electric field of the energy of the dependence position of the conduction band in control channel region 204 and/or valence band.By controlling conduction band, The electron energy barrier between source electrode and drain electrode can be changed.By controlling valence band, thus it is possible to vary the sky between source electrode and drain electrode Cave energy barrier.
Conduction band offset amount and valence band offset amount correspond respectively between source area 202 and drain region 206 for electronics and The size of the energy barrier in hole.By the size for changing energy barrier, the electric charge carrier between the region of band can be controlled Tunnelling.For example, the tunnelling of the electronics between the source area of conduction band and drain region, or the source that valence band can be controlled can be controlled The tunnelling in the hole between polar region and drain region.Tunnelling between the region of control band can make band inner tunnel FET by with interior Tunnelling（That is, the tunnelling in tunnelling or valence band in conduction band）Transmission electric charge carrier, it is provided for giving high driving current High tunneling rate.
Fig. 3 A to Fig. 3 C illustrate some embodiments of N-shaped with inner tunnel FET.
Fig. 3 A illustrate some embodiments of block diagram of the N-shaped with inner tunnel FET300.Band inner tunnel FET300 is included with N-shaped Impure source area 302 and the drain region 306 with N-shaped doping.Channel region 304 is located at n-type source area 302 and n-type drain area Between 306.In certain embodiments, it is worth the source bias V for 0sSource area 302 can be applied to, and be worth the drain electrode more than 0 Bias VdDrain region 306 can be applied to.
In certain embodiments, source area 302 and drain region 306 are configured to have the lattice similar with channel region 304 Constant.For example, source area 302 and drain region 306 can be with the Lattice Matchings of channel region 306（That is, with identical lattice paprmeter）. By keeping the similar lattice paprmeter between the drain region 306 of source area 302/ and channel region 304, in reducing channel region 304 Strain, so as to reduce channel region 304 in defect.
In certain embodiments, source area 302, drain region 306 and channel region 304 can include thering is two or more The compound of element.For example, in certain embodiments, source area 302, drain region 306 and channel region 304 can include binary Compound（For example, including two kinds of semiconductor elements）.Using for binary compound is allowed by two kinds of semiconductor elements of change A kind of semiconductor element concentration with controlled manner change source electrode, drain electrode and/or channel region lattice paprmeter.This can be in source Lattice Matching is realized between polar region 302, drain region 306 and channel region 304.In other embodiments, source area 302, drain electrode One or more in area 306 and/or channel region 306 can include binary compound, and other regions can include it is ternary Compound（For example, including three kinds of semiconductor elements）.For example, source area 302 and drain region 306 can include ternary compound, and Channel region 304 can include binary compound, and or vice versa.
The top of channel region 304 is located at position of the gate regions 308 between source area 302 and channel region 306.Gate regions 308 are configured to generate the electric field of the conduction band energy and Valence-band changed in channel region 304.In certain embodiments, grid Area 308 can include metal gates, and the metal gates include aluminium, chromium, titanium or metalloid.In other embodiments, gate regions 308 can include polysilicon gate material.
In certain embodiments, gate dielectric 310 is arranged between channel region 304 and gate regions 308.In some enforcements In example, gate dielectric 310 can include oxide（For example, aluminum oxide（Al2O3））, hafnium oxide（HfO2）, tantalum oxide（Ta2O5） Deng）.
Fig. 3 B illustrate the energy band diagram 312 and 322 for showing operation of the N-shaped with inner tunnel FET300.If band Figure 31 2 and 322 Shown in, source area 302 has the first band gap BG1, channel region 304 is with the second band gap B G2, and drain region 306 has the 3rd Band gap B G3.First band gap BG1With the 3rd band gap B G3Less than the second band gap B G2。
Energy band diagram 312 illustrates the N-shaped band inner tunnel FET300 under " conducting state ".In the on-state, equal to source The conduction band offset amount of the electrical potential difference between the conduction band CB in conduction band CB and channel region 304 in polar region 302 and/or drain region 306 CBO is comparatively small（For example, between 0.1eV and 0.2eV）.Comparatively small conduction band offset amount CBO allows electronics 314 in source Via channel region 304 with high tunneling rate quantum mechanics tunnelling between the conduction band CB in conduction band CB and drain region 306 in polar region 302 316、318。
In various embodiments, the electronics 314 in conduction band CB can be according to the length of channel region 304, by direct tunnelling 316 and/or by Fowler-Nordheim tunnelling（Fowler Nordheim tunneling）318 and quantum mechanics tunnelling. Directly in tunnelling 316, electronics 314 reaches drain region from source area 302 when there is electric field by the whole length of channel region 304 306 and tunnelling.In Fowler-Nordheim tunnelling 318, electronics 314 passes through part raceway groove when there is electric field from source area 302 Area 304 reach channel region 304 conduction band and tunnelling, then, electronics 314 from channel region 304 flow into drain region 306.
In the on-state, equal to the valence band in valence band VB and channel region 304 in source area 302 and/or drain region 306 Valence band offset amount VBO of the electrical potential difference between VB is relatively very big（That is, more than 0.5eV）.Relatively very big valence band offset amount VBO is prevented Only hole quantum mechanics tunnelling 320 between source area 302 and drain region 306（I.e. so that electronics is used as N-shaped band inner tunnel Electric charge carrier in FET300）.
If shown in band Figure 32 2, under " cut-off state ", negative gate bias are applied to gate regions 308, generate and change raceway groove The electric field of the position of conduction band CB and valence band VB in area 304.The change of the position of conduction band CB changes source area 302 and drain region The height of the electron energy barrier between 406（According to line 324）So that electron energy barrier becomes relatively very big.It is relatively very big Electron energy barrier prevent the quantum mechanics tunnelling 326 between source area 302 and drain region 306 of electronics 314.The position of valence band CB That what is put changes the shape of hole energy barrier（According to line 328）, however, two independent potential barriers continue to prevent hole The quantum mechanics tunnelling between source area 302 and drain region 306.
Fig. 3 C are illustrated and be can be used for source area 302 of the p-type with inner tunnel FET300, channel region 304 and drain region 306 The form 332 of some embodiments of material.
In certain embodiments, it is expert at shown in 334, source area and drain region can include the GaAs that n adulterates （GaAs）, while channel region includes aluminium arsenide（AlAs）.The GaAs of n doping has 5.65 angstroms of lattice paprmeter.AlAs has 5.66 angstroms of less lattice paprmeter, thus reduces between source area 302 and raceway groove 304 and/or drain region 306 and channel region 304 Between strain and defect.Such material provides the conduction band offset amount of 0.2eV and the valence band offset amount of 0.5eV, thus provides The valence band offset amount bigger than conduction band offset amount.
In other embodiments, it is expert at shown in 336, source area and drain region can include the GaAs that n adulterates （GaAs）, and channel region includes zinc selenide（ZnSe）.The GaAs of n doping has 5.65 angstroms of lattice paprmeter.ZnSe has 5.66 Angstrom less lattice paprmeter.Such material provides the conduction band offset amount of 0.2eV and the valence band offset amount of 0.9eV, thus provides The conduction band offset amount bigger than valence band offset amount.
In other embodiments, it is expert at shown in 338, source area and drain region can include antimony GaAs（GaAsSb）, And channel region includes indium phosphide（InP）.According to As/Sb ratios, the GaAsSb of n doping can have about 5.87 angstroms of lattice normal Number.InP has 5.87 angstroms of similar lattice paprmeter.Such material provides the conduction band offset amount of 0.1eV and the valence band of 0.5eV is inclined Shifting amount, thus provides the conduction band offset amount bigger than valence band offset amount.
Fig. 4 A to Fig. 4 C illustrate some embodiments of p-type with inner tunnel FET.
Fig. 4 A illustrate some embodiments of block diagram of the p-type with inner tunnel FET400.P-type band inner tunnel FET400 includes having The source area 402 of p-type doping content and the drain region 406 with p-type doping content.Channel region 404 is located at p impure sources area Between the drain region 406 of 402 and p doping.In certain embodiments, it is worth the source bias V for 0sSource area can be applied to 402, and it is worth the drain bias V less than 0dDrain region 406 can be applied to.
The top of channel region 404 is located at position of the gate regions 408 between source area 402 and drain region 406.Gate regions 408 are configured to based on bias VGGenerate the electric field of the conduction band energy and Valence-band changed in channel region.In some embodiments In, gate regions 408 can include the metal gates comprising aluminium or titanium.Gate regions can be by gate dielectric 410 and channel region 404 are spaced apart.In certain embodiments, gate dielectric 410 can include oxide（For example, Al2O3And/or HfO2）.
Fig. 4 B illustrate the energy band diagram 412 and 422 for showing operation of the p-type with inner tunnel FET400.If band Figure 41 2 and 422 Shown, source area 402 has the first band gap BG1, channel region 404 is with the second band gap B G2, and drain region 406 is with the 3rd band Gap BG3.First band gap BG1With the 3rd band gap B G3Less than the second band gap B G2。
Energy band diagram 412 illustrates the p-type band inner tunnel FET400 under " conducting state ".In the on-state, equal to source electrode Valence band offset amount VBO of the electrical potential difference between valence band VB in valence band VB and channel region 404 in area 402 and/or drain region 406 It is comparatively small（For example, between 0.1eV and 0.2eV）.Comparatively small valence band offset amount VBO allows hole 414（That is, make Obtain hole and be used as p-type with the electric charge carrier in inner tunnel FET400）, in the valence band and drain region 406 in source area 402 Via channel region 404 with high tunneling rates quantum mechanics tunnelling 416,418 between valence band.In various embodiments, hole 414 can With according to the length of channel region by direct tunnelling 418 and/or by the quantum mechanics tunnelling of Fowler-Nordheim tunnelling 416.
Energy band diagram 412 also illustrate that equal to the conduction band CB and channel region 404 in source area 402 and/or drain region 406 in lead Conduction band offset amount CBO with the electrical potential difference between CB.Between source area 402 and channel region 404 and drain region 406 and channel region Conduction band offset amount CBO between 404 is relatively very big（That is, more than VBO）.Relatively very big conduction band offset amount CBO prevents electronics from existing Quantum mechanics tunnelling 420 between source area 402 and drain region 406.
If shown in band Figure 42 2, under " cut-off state ", the electric field generated by gate regions 408 is changed in channel region 404 Valence band VB and conduction band CB position.The change of the position of valence band VB changes source area 402 and drain region 406（According to line 424）Between hole energy barrier height so that hole barrier height is relatively very big（For example, more than 0.5eV）.Relatively very Big hole barrier height prevents quantum mechanics tunnelling 426 of the hole 414 between source area 402 and drain region 406.Conduction band CB The change of position have also been changed the shape of electron energy barrier（According to line 428）, but two independent potential barriers continue to prevent Only electronics quantum mechanics tunnelling between source area 402 and drain region 406.
Fig. 4 C are illustrated and be can be used for source area 402 of the p-type with inner tunnel FET400, channel region 404 and drain region 406 The form 432 of some embodiments of material.
In certain embodiments, it is expert in 434 and illustrates, source area and drain region can includes the indium arsenide aluminium of p doping （InAlAs）, and channel region includes indium phosphide（InP）.According to In/Al ratios, the lattice paprmeter of the InAlAs of p doping can be with class The lattice paprmeter of InP is similar to, it has 5.87 angstroms of lattice paprmeter.Such material provides the conduction band offset amount more than 0.5eV With the valence band offset amount of 0.1eV, the conduction band offset amount bigger than valence band offset amount is thus provided.
In other embodiments, it is expert in 436 and illustrates, source area and drain region can includes the indium arsenide of p doping （InAs）, and channel region includes antimony aluminium arsenide（AlAsSb）.According to As/Sb ratios, the InAs of p doping has 6.06 angstroms of lattice Constant, the lattice paprmeter can be similar to the lattice paprmeter of AlAsSb.Such material provides the conduction band offset amount peace treaty of 0.9eV The valence band offset amount of 0.1eV, thus provides the conduction band offset amount bigger than valence band offset amount.
In other embodiments, it is expert in 438 and illustrates, source area 402 and drain region 406 can includes the arsenic of p doping Indium（InAs）, and channel region includes the indium phosphide of strain（InP）.The InAs of p doping has 6.06 angstroms of lattice paprmeter.InP has There is 5.87 angstroms of lattice paprmeter, it forms the InP raceway grooves of strain on InAs source electrodes or drain electrode.The InP materials of strain form phase To very thin channel region（For example, about between 4nm and 10nm）.Such material provide the conduction band offset amount of 0.6eV and The valence band offset amount of 0.1eV, thus provides the conduction band offset amount bigger than valence band offset amount.
Fig. 5 A and Fig. 5 B are illustrated and are configured to disclosed some enforcements with inner tunnel FET500 for performing linear tunnel Example.
Band inner tunnel FET500 includes source area 502, channel region 504 and drain region 506.Channel region 504 is located at source electrode In area 502, and drain region 506 is located on channel region 504.In certain embodiments, gate regions 508 are located on drain region 506 Side so that gate regions 508 are located at the position being spaced apart with channel region 504 by drain region 506.In other embodiments, grid Polar region 508 may be located at the lower section of source area 502 so that gate regions 508 are located at and are spaced with channel region 504 by source area 502 At the position opened.
As shown in band inner tunnel FET500, gate regions 508 are configured to generation and extend through drain region 506 and channel region 504 electric field.Because gate regions 508 are located at the top of drain region 506, so electric field changes in drain region 506 and channel region 504 The position of conduction band and valence band.Electric field can on the direction of grid length band inner tunnel FET500 internediate quantum mechanicses ground Tunnelling.For example, in fig. 5, grid length 510 extension along a first direction, and tunnelling occurs along second direction 512.This quilt Referred to as linear tunnel.
Fig. 5 B illustrate the energy band diagram 514 and 522 for showing the operation with inner tunnel FET500.If band Figure 51 4 and 522 institutes Show, source area 502 has the first band gap, channel region 504 has the second band gap, and drain region 506 has the 3rd band gap, its In, the second band gap is more than the first band gap and the 3rd band gap.
Energy band diagram 514 illustrates the N-shaped band inner tunnel FET500 under " conducting state ".In the on-state, the He of source area 502 Conduction band offset amount CBO between channel region 504 and between drain region 506 and channel region 504 is comparatively small, causes source electrode 502 And the very low electron energy barrier between drain electrode 506.Comparatively small electron energy barrier allows electronics in source area 502 Via the quantum mechanics tunnelling of channel region 504 between conduction band CB in conduction band CB and drain region 506.Source area 502 and channel region 504 Between and valence band offset amount VBO between drain region 506 and channel region 504 it is relatively very big（That is, more than CBO）, cause source electrode Very high hole energy barrier between 502 and drain electrode 506.Relatively very high hole energy barrier prevents hole in source area 502 In valence band VB and drain region 506 in valence band VB between via the quantum mechanics tunnelling of channel region 504（I.e. so that electronics is used as n Type is with the electric charge carrier in inner tunnel FET500）.
If shown in band Figure 52 2, under " cut-off state ", bias is applied to gate regions 508 so that gate regions 508 generate Electric field.Electric field changes the position of channel region 504 and the conduction band CB in drain region 506 and valence band VB.The change of the position of conduction band CB Prevent electronics between source area 502 and drain region 506 via the quantum mechanics tunnelling of channel region 504.
Fig. 6 A and Fig. 6 B are illustrated and are configured to some embodiments with inner tunnel FET600 and 618 for performing linear tunnel.
Fig. 6 A illustrate the N-shaped band inner tunnel FET600 for being configured to perform linear tunnel.N-shaped band inner tunnel FET600 includes N impure sources area, it includes arranging semiconductor body 604 on substrate 602.In certain embodiments, semiconductor body 604 nano wires 604 that can extend including the rotary shaft 606 that can be arranged along perpendicular to substrate, and nano wire Radius t1 can be between about 20nm and about 100nm.Nano wire 604 has height h, and it is far longer than radius t1。 In certain embodiments, nano wire 604 can include being formed in indium phosphide（InP）Antimony GaAs on substrate（GaAsSb）Nanometer Line.
Channel region 608 is positioned proximate to nano wire 604.In certain embodiments, channel region 608 includes covering nano wire 604 outer peripheral concentric shell.Channel region 608 is radially positioned at the position outside nano wire 604（That is, it is positioned at ratio Nano wire 604 is at the bigger radius of rotary shaft）.In certain embodiments, channel region 608 can include that intrinsic doping is dense Degree, while in other embodiments, channel region 608 can include N-shaped or p-type doping content.The thickness t of channel region 6082Can be with Between about 4nm and about 10nm.In certain embodiments, channel region 608 can include indium phosphide（InP）.
The drain region 610 of n doping is radially positioned at the position outside channel region 608 and is positioned proximate to channel region 608.In certain embodiments, drain region 610 includes covering the concentric shell of nano wire 604 and channel region 608.In some enforcements In example, the thickness t of drain region 6103Can be between about 4nm and about 10nm.In certain embodiments, drain region 610 can include antimony GaAs（GaAsSb）.
Gate regions 612 are radially positioned the outside of the drain region 610 of n doping.Gate regions 612 can pass through gate dielectric Layer 614 is spaced apart with the drain region 610 of n doping.
First distance piece 616a and the second compartment 616b are configured to the drain electrode for preventing from being adulterated in substrate 602 and n respectively Between area 610 and n doping nano wire 604（That is, source electrode）And the undesirable fax between the drain region 610 of n doping Lead.For example, distance piece 616a is located between the drain region 610 that substrate 602 and n adulterate, and distance piece 616b is located in side Nano wire 604 and channel layer 608 and the drain contacts 611 in opposite side（It is electrically connected to the drain region 610 of n doping）It Between.In certain embodiments, the first distance piece 616a and the second distance piece 616b can include dielectric material（For example, aoxidize Thing）.
Fig. 6 B illustrate the p-type band inner tunnel FET618 for being configured to perform tunnelling.P-type band inner tunnel FET618 mixes including p Miscellaneous source area, p impure sources area includes the nano wire 622 being arranged on substrate 620.In certain embodiments, Ke Yiyan Rotary shaft 624 and nano wire 622, and the radius t of nano wire are set1Can be between about 20nm and about 100nm. The height h of nano wire 622 is far longer than radius t1.In certain embodiments, nano wire 622 can include being formed in indium arsenide （InAs）Indium arsenide on substrate（InAs）Nano wire.
Channel region 626 is positioned proximate to nano wire 622.In certain embodiments, channel region 626 includes covering nano wire 622 outer peripheral concentric shell.Channel region 626 is located at the position being radially positioned outside nano wire 622.One In a little embodiments, channel region 608 can include intrinsic doping content, and in other embodiments, channel region 608 can include n Type or p-type doping content.The thickness t of channel region 6262Can be between about 4nm and about 10nm.In some embodiments In, channel region 608 can include antimony aluminium arsenide（AlAsSb）.
The drain region 628 of p doping is radially positioned at the position outside channel region 626 and is positioned proximate to channel region 626.In certain embodiments, the thickness t of drain region 6283Can be between about 4nm and about 10nm.In some realities In applying example, drain region 628 can include indium arsenide（InAs）.
Gate regions 630 are radially positioned the outside of the drain region 628 of p doping.Gate regions 630 can pass through gate dielectric Layer 632 is spaced apart with the drain region 628 of p doping.
First distance piece 634a and the second distance piece 634b are configured to the drain electrode for preventing from adulterating in substrate 620 and p respectively Between area 628 and p doping nano wire 622（That is, source electrode）And the undesirable electrical conduction between the drain region 628 of p doping. For example, distance piece 634a is located between the drain region 628 that substrate 620 and p adulterate, and distance piece 634b is located at the p in side The nano wire 622 and channel layer 626 of doping and the drain contacts 629 in opposite side（It is electrically connected to the drain region 628 of p doping） Between.In certain embodiments, the first distance piece 634a and the second distance piece 634b can include dielectric material（For example, aoxidize Thing）.
Fig. 7 is the flow chart of some embodiments of the method 700 with inner tunnel FET to form disclosed.
Although disclosed method 700 is shown below and is described as series of steps（act）Or event, but should manage Solution, such step or the shown order of event should not be construed as limited to meaning.For example, some steps can be suitable with difference Sequence occurs and/or occurs simultaneously with other steps or event in addition to step shown and/or described herein.In addition, not It is required that all shown steps may be used to the one or more aspects or embodiment of the description for realizing herein.And, can To realize one or more steps specifically described herein in one or more independent processes and/or stage.
In a step 702, the source area with the first doping type is formed.In certain embodiments, using depositing operation In Grown source area.For example, depositing operation can include PVD or chemical vapor deposition（HVCVD、 MOCVD etc.）.
In step 704, channel region is formed at the position of neighbouring source area.In certain embodiments, for example, by bag Include PVD or chemical vapor deposition（HVCVD, MOCVD etc.）Depositing operation, channel region is formed on source area. In some embodiments, channel region has similar lattice paprmeter with source area（For example, source area and channel region have the crystalline substance of matching Lattice）So that channel region can be grown on source area without defect.
Channel region has the band gap bigger than source area.Larger band gap causes channel region to form hetero-junctions with source area. In some embodiments, channel region can include intrinsic doping content, and in other embodiments, channel region can have first to mix Miscellany type（For example, N-shaped doping）Or second doping type（For example, p-type doping）.
In step 706, at the position of neighbouring channel region the drain region with the first doping type is formed.In some enforcements In example, for example, by including PVD or chemical vapor deposition（HVCVD, MOCVD etc.）Depositing operation in channel region Upper formation drain region.In certain embodiments, drain region has similar lattice paprmeter with channel region（For example, channel region and leakage Polar region has the lattice of matching）So that drain region can be over the channel region grown without defect.
Drain region has less band gap than channel region.Smaller strip gap causes channel region to form double with source area and drain region Hetero-junctions.Interface between source area and channel region and in drain region and the shape of the double heterojunction of the interface of channel region Into the energy barrier caused between source area and drain region.Energy barrier is asymmetric so that it has for the of conduction band One offset value（That is, conduction band offset amount）And for the second different offset value of valence band（That is, valence band offset amount）.
In certain embodiments, wherein, the difference in band gap of tunnel FET including N-shaped tunnel FET, channel region and source/drain regions Form the conduction band offset amount less than valence band offset amount.In other embodiments, wherein, tunnel FET include p-type tunnel FET, ditch Difference in band gap between road area and source/drain regions forms the conduction band offset amount bigger than valence band offset amount.
It is square into gate regions over the channel region in step 708.Gate regions are configured to generate the conduction band changed in channel region With the electric field of the position of valence band.The position of conduction band and valence band in by changing channel region, thus it is possible to vary electronics and hole barrier. By changing electronics and hole barrier, can be efficiently controlled in can be with interior（For example, in conduction band or in valence band）From source area To the quantum mechanics tunnelling of drain region.
It should be appreciated that, although refer to exemplary knot through this document when many aspects of method specifically described herein are discussed Structure, but whether pass through proposed corresponding construction limiting those methods.But, method and structure will be considered as mutual nothing Close and can be independent, and any particular aspects shown in the drawings are not considered realizing these method and structures.
Additionally, the reading and/or understanding based on specification and drawings, can send out to those skilled in the art The equivalent change of life and/or modification.Disclosure herein includes all such modifications and changes and be generally not intended to limit Due to this.For example, although accompanying drawing presented herein is shown and described as with specific doping type, but should manage Solution, such as it will be understood by those skilled in the art that optional doping type can be utilized.
In addition, though disclose special characteristic or aspect already in connection with one of various implementations, but such feature Or aspect can with such as may expect other implementations one or more other features and/or in terms of combined.And, In a way, term " including " used herein, " having ", " having ", " carrying " and/or its variant, such art Language is intended to express the meaning for including（As " including（comprising）" equally）.And, " exemplary " simply means to a reality Example, rather than preferred example.It should also be understood that for understanding simply and readily, part specifically described herein, layer and/or unit Part by relative specific dimensions and/or it is qualitative be illustrated, and actual size and/or orientation can be differently configured from herein shown in Size and/or orientation.
Therefore, the present invention relates to band inner tunnel FET, it includes that the asymmetric tunnel FET for high driving current can be provided.
In certain embodiments, the present invention relates to band inner tunnel field-effect transistor（TFET）Device.With interior TFET devices Including the source area being spaced apart with drain region by channel region, wherein, source area, drain region and channel region have energy band, its Energy barrier is formed between the source area with the conduction band offset amount different from valence band offset amount and drain region.Matched somebody with somebody gate regions It is set to and generates the electric field for changing energy barrier, selectively allows for quantum mechanics tunnelling or the selectivity of the electronics in conduction band Ground allows the quantum mechanics tunnelling in the hole in valence band.
In other embodiments, the present invention relates to band inner tunnel field-effect transistor（TFET）Device.With interior TFET devices Including source area, it includes the source electrode compound with two or more semiconductor elements, wherein, source area is with the first doping Type and the first band gap magnitude.Drain region is further included with interior TFET devices, it includes thering is two or more semiconductor elements Drain electrode compound, wherein, source area has the first doping type and the second band gap magnitude.Ditch is further included with interior TFET devices Road area, it includes being located between source area and drain region and with threeth band bigger than the first band gap magnitude and the second band gap magnitude The raceway groove compound with two or more semiconductor elements of gap value, wherein, the 3rd band gap magnitude source area and drain region it Between form energy barrier.Gate regions are further included with interior TFET devices, is configured to generate in control source area and drain region In conduction band between or source area in and drain region in valence band between electric charge carrier quantum mechanics tunnelling.
In other embodiments, the present invention relates to form the method with inner tunnel field-effect transistor.The method includes：Shape Into the source area with the first doping type.The method is further included：Form the drain region with the first doping type.The party Method is further included：Form the channel region being located between source area and drain region.The method is further included：Formation is configured to Generate the electric field of the quantum mechanics tunnelling for controlling electronics or hole between source area and drain region.Source area, drain region and ditch Road area has the conduction band offset amount different from valence band offset amount, to form energy barrier between source area and drain region, selects Property ground allow the quantum mechanics tunnelling of the electronics in conduction band, or the quantum mechanics tunnel for selectively allowing for hole in valence band Wear.

Claims (20)

1. a kind of band inner tunnel field-effect transistor (TFET) device, including：
Source area, is spaced apart by channel region with drain region, wherein, the source area, the drain region and channel region tool Have can band, it is described to form the first monoergic potential barrier in conduction band of the band between the source area and the drain region, and The second monoergic potential barrier is formed in valence band between the source area and the drain region, wherein, the first monoergic potential barrier Conduction band offset amount with the valence band offset amount different from the second monoergic potential barrier；And
Gate regions, are configured to generate the electric field for changing the energy barrier, to selectively allow for the amount of the electronics in conduction band Sub- mechanics tunnelling, or selectively allow for the quantum mechanics tunnelling in hole in valence band.
2. according to claim 1 with inner tunnel FET device, wherein, the gate regions are in the source area It is located at the position above the channel region and the drain region between.
3. according to claim 1 with inner tunnel FET device, wherein,
Length of the gate regions on the direction parallel with the flowing of the electric charge carrier in the channel region is in about 4nm peace treaties Between 10nm.
4. according to claim 1 with inner tunnel FET device, wherein, the gate region is in by described At the position that source area or the drain region are spaced apart with the channel region.
5. according to claim 1 with inner tunnel FET device, wherein,
First doping type of the channel region is contrary with the second doping type of the source area and the drain region.
6. according to claim 1 with inner tunnel FET device, wherein, the value of the conduction band offset amount is about Between 0.1eV (electron-volt) and about 0.2eV, and the value of the valence band offset amount is greater than about 0.5eV.
7. according to claim 1 with inner tunnel FET device, wherein,
The source area and the drain region have N-shaped doping content；And
The valence band offset amount between the source area and the channel region is between the source area and the channel region At least twice of the conduction band offset amount.
8. according to claim 7 with inner tunnel FET device, wherein,
The source area and the drain region include GaAs or antimony GaAs；And
The channel region includes aluminium arsenide, selenizing or indium phosphide.
9. according to claim 1 with inner tunnel FET device, wherein,
The source area and the drain region have p-type doping content；And
Conduction band offset amount between the source area and the channel region is the valence band between the source area and the channel region At least twice of side-play amount.
10. according to claim 9 with inner tunnel FET device, wherein,
The source area and the drain region include indium arsenide aluminium or indium arsenide；And
The channel region includes indium phosphide or antimony aluminium arsenide.
A kind of 11. band inner tunnel field-effect transistor (TFET) devices, including：
Source area, including the source electrode compound with two or more semiconductor elements, the source area has the first doping class Type and the first band gap magnitude；
Drain region, including the drain electrode compound with two or more semiconductor elements, the source area has described first to mix Miscellany type and the second band gap magnitude；
Channel region, including the raceway groove compound with two or more semiconductor elements and positioned at the source area and the drain electrode Between area, the 3rd band gap magnitude of the channel region is more than first band gap magnitude and second band gap magnitude, the 3rd band gap Value forms the first monoergic potential barrier for electronics and the second list for hole between the source area and the drain region Energy barrier；And
Gate regions, are configured to generate electric field, conduction band of the electric field controls electric charge carrier in the source area and described The quantum mechanics tunnel between the valence band in valence band and the drain region between conduction band in drain region or in the source area Wear.
12. band inner tunnel FET devices according to claim 11, wherein, the gate regions are in the source electrode It is located at the position above the channel region between area and the drain region.
13. band inner tunnel FET devices according to claim 11, wherein, the gate region is in by institute State at the position that source area or the drain region are spaced apart with the channel region.
14. band inner tunnel FET devices according to claim 11,
Wherein, the source area and the drain region are included selected from GaAs, antimony GaAs, indium arsenide aluminium or indium arsenide institute group Into group in two or more semiconductor elements.
15. band inner tunnel FET devices according to claim 14,
Wherein, the channel region includes two kinds in the group constituted selected from aluminium arsenide, zinc selenide, indium phosphide or antimony aluminium arsenide Semiconductor element above.
16. band inner tunnel FET devices according to claim 11, wherein,
The source area is included at the position extended along the rotary shaft with substrate transverse and arranges partly leading over the substrate Body body；
The channel region is positioned adjacent at the position of the semiconductor body, and the channel region opens ratio with the new ro-tational axis The bigger radius of the semiconductor body；And
The drain region is positioned adjacent at the position of the channel region, and the drain region is opened than described with the new ro-tational axis The bigger radius of channel region.
17. band inner tunnel FET devices according to claim 11, further include：
First distance piece, is arranged between substrate and the drain region；And
Second distance piece, is arranged between the semiconductor body and the channel layer and drain contacts, the drain contact Part is electrically connected to the drain region.
A kind of 18. methods of the formation with inner tunnel field-effect transistor, including：
Form the source area with the first doping type；
Form the drain region with the first doping type；
Form the channel region being located between the source area and the drain region；And
Form gate regions, the gate regions be configured to generate control electronics or hole the source area and the drain region it Between quantum mechanics tunnelling electric field,
Wherein, the source area, the drain region and the channel region have the conduction band offset amount different from valence band offset amount, To form the first monoergic potential barrier for electronics and the second list for hole between the source area and the drain region Energy barrier, so as to selectively allowing for the quantum mechanics tunnelling of the electronics in conduction band or selectively allowing in the valence band The quantum mechanics tunnelling in hole.
19. methods according to claim 18, wherein, the value of the conduction band offset amount is in about 0.1eV and about between 0.2eV In the range of, and the value of the valence band offset amount is greater than about 0.5eV.
20. methods according to claim 18, wherein, the source area, the drain region and the channel region include Compound with two or more semiconductor elements.
CN201310303452.2A 2013-03-13 2013-07-18 Intra-band tunnel FET Active CN104051528B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201361778634P 2013-03-13 2013-03-13
US61/778,634 2013-03-13
US13/863,489 US9711632B2 (en) 2013-03-13 2013-04-16 Intra-band tunnel FET
US13/863,489 2013-04-16

Publications (2)

Publication Number Publication Date
CN104051528A CN104051528A (en) 2014-09-17
CN104051528B true CN104051528B (en) 2017-04-12

Family

ID=51504146

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310303452.2A Active CN104051528B (en) 2013-03-13 2013-07-18 Intra-band tunnel FET

Country Status (1)

Country Link
CN (1) CN104051528B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016048306A1 (en) * 2014-09-24 2016-03-31 Intel Corporation Scaled tfet transistor formed using nanowire with surface termination
KR102232755B1 (en) * 2015-04-07 2021-03-26 삼성전자주식회사 Electronic device using 2-dimensional material and method of manufacturing the same
CN105047719B (en) * 2015-08-11 2018-03-06 西安电子科技大学 Staggered hetero-junctions tunneling field-effect transistor based on InAsN GaAsSb materials
WO2018170770A1 (en) * 2017-03-22 2018-09-27 华为技术有限公司 Tunnel field effect transistor and method for fabrication thereof
CN108321197A (en) * 2018-02-24 2018-07-24 中国科学院微电子研究所 A kind of tunnel field-effect transistor and its manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504347A (en) * 1994-10-17 1996-04-02 Texas Instruments Incorporated Lateral resonant tunneling device having gate electrode aligned with tunneling barriers
CN102694026A (en) * 2011-03-25 2012-09-26 株式会社东芝 Field effect transistor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7936040B2 (en) * 2008-10-26 2011-05-03 Koucheng Wu Schottky barrier quantum well resonant tunneling transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504347A (en) * 1994-10-17 1996-04-02 Texas Instruments Incorporated Lateral resonant tunneling device having gate electrode aligned with tunneling barriers
CN102694026A (en) * 2011-03-25 2012-09-26 株式会社东芝 Field effect transistor

Also Published As

Publication number Publication date
CN104051528A (en) 2014-09-17

Similar Documents

Publication Publication Date Title
CN103715259B (en) Tunneling field-effect transistor including graphene-channel
US9741848B2 (en) Multi-gate tunnel field-effect transistor (TFET)
CN104051528B (en) Intra-band tunnel FET
US8288798B2 (en) Step doping in extensions of III-V family semiconductor devices
US9136363B2 (en) Compound tunneling field effect transistor integrated on silicon substrate and method for fabricating the same
US9711632B2 (en) Intra-band tunnel FET
US20120019284A1 (en) Normally-Off Field Effect Transistor, a Manufacturing Method Therefor and a Method for Programming a Power Field Effect Transistor
EP2528099A1 (en) Line- tunneling Tunnel Field-Effect Transistor (TFET) and manufacturing method
CN102148255B (en) Grid-control schottky junction field effect transistor with tunneling dielectric layer and formation method
KR102053027B1 (en) P-type Graphene Base Transistor
KR20150008770A (en) Tunneling device and method of manufacturing the same
US9768289B2 (en) Field effect transistor with conduction band electron channel and uni-terminal response
CN103262243A (en) Nanowire field-effect device with multiple gates
CN106030817B (en) Tunneling field-effect transistor with variable bandgap channel
CN110943121A (en) Tunneling field effect transistor
KR101424755B1 (en) Independent and Different Work Fuction Double Gated electron-hole Bilayer Tunnel Field Effect Transistor and its Fabrication Method
KR102352906B1 (en) Complementary transistors and semiconductor devices
Tomioka et al. Vertical gate-all-around tunnel FETs using InGaAs nanowire/Si with core-multishell structure
KR102093141B1 (en) Natural Heterojunction Tunnel Field-Effect Transistor
CN109980015B (en) Tunneling field effect transistor capable of effectively increasing on-state current
JP7164204B2 (en) tunnel field effect transistor and electronic device
JP2010040972A (en) Semiconductor device, and manufacturing method thereof
US11621340B2 (en) Field-effect transistor structure and fabrication method
Usha et al. Evolution of Heterojunction Tunnel Field Effect Transistor and its Advantages
CN102593177B (en) Tunneling transistor with horizontal quasi coaxial cable structure and forming method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant