CN104049203A - Pin with boundary scanning and testing function and integrated circuit with same - Google Patents
Pin with boundary scanning and testing function and integrated circuit with same Download PDFInfo
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- CN104049203A CN104049203A CN201410171098.7A CN201410171098A CN104049203A CN 104049203 A CN104049203 A CN 104049203A CN 201410171098 A CN201410171098 A CN 201410171098A CN 104049203 A CN104049203 A CN 104049203A
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Abstract
The invention discloses a pin with a boundary scanning and testing function and an integrated circuit with the pin. The pin comprises at least one boundary scanning register, a boundary scanning signal input pin, a boundary scanning signal output pin and a TAP control signal end receiving boundary scanning control signals from a TAP controller. Due to the fact that the boundary scanning register is integrated in the pin, insertion of JTAG testing logic of the input, output and control signals of the pin outside the pin is reduced in the chip implementation process, meanwhile, negative influence caused by the position of the JTAG testing logic of the input, output and control signals of the pin on the timing sequence can be avoided in the locating and wiring process, and rapid convergence of the timing sequence is facilitated.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly, relate to a kind of pin of built-in boundary scan register and comprise the integrated circuit of this pin.
Background technology
Boundary scan technique is a kind of testability construction design method that is applied to digital integrated circuit device.So-called " border " refers to that test circuit is arranged on the surrounding of integrated circuit (IC)-components logic function circuit, is positioned at the boundary near device input, output and control pin.So-called " scanning " refers to that the test circuit of each input of interface unit, output and control pin is actually one group of serial shift register, this serial shift register is called " scanning pattern ", along this paths, can input the various codings that formed by " 0 " and " 1 ", circuit is carried out to " scanning " formula and detect, from Output rusults, judge that whether it is correct.
Fig. 1 is the schematic diagram that the top level structure of the integrated circuit (IC) chip based on prior art is shown.As shown in Figure 1, at each, be all furnished with the boundary scan register (BSR:boundary scan register) being formed by register and combinational logic near by tested pin (PAD), meanwhile, according to pin, be single input, single output, input and output or tri-state pin and the quantity of the boundary scan register of arranging is in its vicinity also different.For example, for the tri-state pin with input pin input, output pin output and control pin control as shown in Figure 2, near it, should arrange three boundary scan register.
As shown in Figure 1, all boundary scan register are all connected to integrated circuit signal internal logic (Core), and all boundary scan register are according to mobile being linked in sequence, thereby form a JTAG scan chain.For test data input (TDI), test clock input (TCK), the test pattern of JTAG sweep test, select (TMS), test reset input (TRST) and test data output (TDO) relevant signal to provide or be input to TAP controller by test access port (TAP) controller, thereby by TAP controller, realized the control of JTAG scan chain, thereby realize the test of input, output and the control signal of pin.The TDI of external drive by TAP controller is shifted successively and enters each boundary scan register, then the input pin of tested PAD applied to excitation and tests, and finally test result shifted out or parallel from tested PAD output pin output from TDO successively.Output rusults by observation TDO and tested PAD output pin, judges whether the connection of PAD goes wrong.
As mentioned above, each boundary scan register is to consist of register and combinational logic, and combinational logic separates feature path and test path, and can under functional mode and test pattern, carry out the switching in path.Feature path is the access path between pin and internal logic, due to the insertion of boundary scan register, have a plurality of boundary scan register unit between pin and internal logic, so feature path has been subject to the impact of boundary scan register position.
For better sequential with do not affect feature path, in placement-and-routing's process of integrated circuit, boundary scan register must be placed on to the side of each tested pin, the combinational logic of boundary scan register inside particularly, because combinational logic is by handoff functionality path and test path, the position of combinational logic directly affects feature path, if the distance pin that the combinational logic of routing is placed is far, feature path will be greatly affected so.
Summary of the invention
In view of the above-mentioned problems in the prior art, the invention provides a kind of pin of integrated boundary scan testing function and comprise the integrated circuit of this pin.
According to an aspect of the present invention, a kind of pin for integrated circuit is provided, and described pin comprises at least one boundary scan register, boundary scan signal input pin, boundary scan signal output pin and the TAP control signal end that receives boundary scan control signal from test access port (TAP) controller.
Preferably, described TAP control signal end comprises from the test clock input end of TAP controller receive clock signal and from TAP controller, receives the test pattern selecting side of test mode select signal.
Preferably, when described pin is input pin, described pin comprises for receiving the signal input pin of signal, and described at least one boundary scan register comprises an input boundary scan register that is connected to described input pin.
Preferably, when described pin is output pin, described pin also comprises for output signal leg signal output pin, and described at least one boundary scan register comprises an output boundary scan register that is connected to described output pin.
Preferably, when described pin is I/O pin, described pin also comprises for receiving the signal input pin of signal and for output signal leg signal output pin, and described at least one boundary scan register comprises input boundary scan register and the output boundary scan register that is connected respectively to input pin and output pin.
Preferably, when described pin is tri-state pin, described pin also comprises signal input pin for receiving signal, for output signal leg signal output pin with for the control signal pin of reception control signal, and described at least one boundary scan register comprises and is connected respectively to input boundary scan register, the output boundary scan register of described input pin, output pin and control signal pin and controls boundary scan register.
Preferably, described at least one boundary scan register is the boundary scan register based on JTAG sweep test.
Preferably, at least one boundary scan register is connected and is formed for JTAG scan chain with other pin with boundary scan signal output pin via described boundary scan signal input pin.
According to a further aspect in the invention, provide a kind of integrated circuit with pin as above.
Due to according to integrated boundary scan register in pin provided by the present invention, thereby reduced the jtag test logic of input, output and the control signal of pin in chip implementation procedure in pin insertion in addition, simultaneously in placement-and-routing, can avoid the negative effect of the sequential aspect that the position of the jtag test logic of input, output and control signal due to pin brings, be conducive to the Fast Convergent of sequential.
Accompanying drawing explanation
By the description of embodiment being carried out below in conjunction with accompanying drawing, these and/or other aspect of the present invention and advantage will become clear and be easier to and understand, wherein:
Fig. 1 is the schematic diagram that the top level structure of the integrated circuit (IC) chip based on prior art is shown;
Fig. 2 is the schematic diagram that tri-state supervisor is shown;
Fig. 3 is the diagram illustrating according to the pin of the integrated boundary scan register of exemplary embodiment of the present invention;
Fig. 4 A, Fig. 4 B and Fig. 4 C are for illustrating respectively the schematic diagram of controlling boundary scan register, output boundary scan register and input boundary scan register;
Fig. 5 is the schematic diagram of top level structure that the integrated circuit of the pin integrated with boundary scan register according to exemplary embodiment of the present invention is shown.
Embodiment
Now the embodiment of the present invention is described in detail, in the accompanying drawings, wherein, identical label represents same parts to its example shown all the time.Below with reference to the accompanying drawings embodiment is described to explain the present invention.
According to technical scheme of the present invention, in designing integrated circuit or pin (PAD) library unit design process, boundary scan register (BSR) is integrated in PAD, and the BSR of PAD inside completes the connection that local J TAG scanning connects, therefore in chip design process, only need the insensitive TAP steering logic in insertion position, and the BSR coherent signal of PAD is coupled together and can realize boundary scan test circuit.
Fig. 3 is the diagram illustrating according to the pin of the integrated boundary scan register of exemplary embodiment of the present invention.Pin PAD shown in Fig. 3 is tri-state pin, that is, it has comprised input pin input, output pin output and has controlled pin control.
In addition, boundary scan register that pin PAD shown in Fig. 3 is also integrated, that is, described pin PAD also comprised be connected to control pin control the first boundary scan register 110, be connected to the second boundary scan register 120 of output pin output and be connected to the 3rd boundary scan register 130 of input pin input.
In Fig. 3, the first boundary scan register 110, the second boundary scan register 120 and the 3rd boundary scan register 130 can be implemented as respectively the input boundary scan register shown in control boundary scan register, the output boundary scan register shown in Fig. 4 B and Fig. 4 C as shown in Figure 4 A.Structural similarity due to the control boundary scan register of using in the output boundary scan register shown in the control boundary scan register shown in Fig. 4 A, Fig. 4 B and the input boundary scan register shown in Fig. 4 C and prior art, output boundary scan register and input boundary scan register, does not therefore repeat them here.
In addition, the pin PAD shown in Fig. 3 also can comprise boundary scan signal input pin SI and boundary scan signal output pin SO.Described boundary scan signal input pin SI and boundary scan signal output pin SO carry out signal exchange for other pin, that is, via described boundary scan signal input pin SI, from other pin, signal is received to pin PAD and via described boundary scan signal output pin SO signal is outputed to other pin from described pin PAD.
In addition, the pin PAD shown in Fig. 3 also can comprise the TAP control signal end CLOCK/MODE that receives boundary scan control signal from TAP controller.For example, described TAP control signal end CLOCK/MODE comprises from the test clock input pin of TAP controller receive clock signal and selects pin from the test pattern of TAP controller reception test mode select signal.
The embodiment of the tri-state pin of having described boundary scan register integrated in conjunction with Fig. 3 above.Technical scheme described in conjunction with Figure 3 can be applicable to only have input pin, only have output pin and have the pin of input and output pin.
For example,, when pin is that while only having the pin of input pin, it can only comprise the input boundary scan register of the 3rd boundary scan register 130 as shown in Figure 3 that is connected to input pin.
For example,, when pin is that while only having the pin of output pin, it can only comprise the output boundary scan register of the second boundary scan register 120 as shown in Figure 3 that is connected to output pin.
For example, when pin is while having the pin of input pin and output pin, it can comprise the input boundary scan register of the 3rd boundary scan register 130 as shown in Figure 3 that is connected to input pin and the output boundary scan register that is connected to the second boundary scan register 120 as shown in Figure 3 of output pin.
Below, in conjunction with Fig. 5, describe and to have there is the integrated circuit of boundary scan register integrated.Fig. 5 is the schematic diagram that the integrated circuit integrated with boundary scan register according to the embodiment of the present invention is shown.
As shown in Figure 5, according to the integrated circuit of the embodiment of the present invention, internal logic CORE, test access port (TAP) controller 200 and a plurality of pin have been comprised, wherein, described a plurality of pin comprises above with reference to the described input pin of Fig. 3, output pin, input and output pin and tri-state pin.
Here, TAP controller 200 has for JTAG sweep test test input input (TDI) pin, test clock input (TCK) pin, test pattern are selected (TMS) pin, test reset input (TRST) pin and test data output (TDO) pin.Due to TAP control 200 and pin can be realized by TAP controller and the pin thereof of prior art, therefore omit the description to it.
Meanwhile, as mentioned above, described integrated each pin in a plurality of pin PAD of boundary scan register has included boundary scan signal input pin SI and boundary scan signal output pin SO.
The included boundary scan register of a plurality of pins of the integrated circuit shown in Fig. 5 is sequentially connected by boundary scan signal input pin SI and boundary scan signal output pin SO separately, thereby form a JTAG scan chain,, formed the JTAG scan chain of TDO of TDI pin → SI → SO → SI........... → SO → SI → SO → TAP controller of TAP controller, here, SI and SO represent respectively to the scanning input of boundary scan register or export from the scanning of boundary scan register.
Because the JTAG scanning technique of prior art can be applicable to the JTAG scanning of integrated circuit as shown in Figure 5, so omit the description to the JTAG sweeping scheme of the integrated circuit shown in Fig. 5.
According in technical scheme of the present invention, due to boundary scan register (BSR) has been integrated into pin (PAD), therefore it is inner that the position of the combinational logic of boundary scan register and inside thereof has been limited in PAD, so in placement-and-routing's process of integrated circuit, do not need to consider the placement of BSR interrelated logic, feature path can not be affected due to the position of combinational logic, is more conducive to sequential Fast Convergent.
Although represented and described some embodiments of the present invention, it should be appreciated by those skilled in the art that in the situation that do not depart from principle of the present invention and the spirit that is limited its scope by claim and equivalent thereof, can modify to these embodiment.
Claims (9)
1. for a pin for integrated circuit, it is characterized in that comprising:
At least one boundary scan register;
Boundary scan signal input pin;
Boundary scan signal output pin; And
From test access port controller, receive the test access port control signal end of boundary scan control signal.
2. pin according to claim 1, it is characterized in that, described test access port control signal end comprises from the test clock input end of test access port controller receive clock signal and from test access port controller, receives the test pattern selecting side of test mode select signal.
3. pin according to claim 1, it is characterized in that, when described pin is input pin, described pin comprises for receiving the signal input pin of signal, and described at least one boundary scan register comprises an input boundary scan register that is connected to described input pin.
4. pin according to claim 1, it is characterized in that, when described pin is output pin, described pin also comprises for output signal leg signal output pin, and described at least one boundary scan register comprises an output boundary scan register that is connected to described output pin.
5. pin according to claim 1, it is characterized in that, when described pin is I/O pin, described pin also comprises for receiving the signal input pin of signal and for output signal leg signal output pin, and described at least one boundary scan register comprises input boundary scan register and the output boundary scan register that is connected respectively to input pin and output pin.
6. pin according to claim 1, it is characterized in that, when described pin is tri-state pin, described pin also comprises signal input pin for receiving signal, for output signal leg signal output pin with for the control signal pin of reception control signal, and described at least one boundary scan register comprises and is connected respectively to input boundary scan register, the output boundary scan register of described input pin, output pin and control signal pin and controls boundary scan register.
7. pin according to claim 1, is characterized in that, described at least one boundary scan register is the boundary scan register based on JTAG sweep test.
8. pin according to claim 7, is characterized in that, at least one boundary scan register is connected and is formed for JTAG scan chain with other pin with boundary scan signal output pin via described boundary scan signal input pin.
9. an integrated circuit with the pin as described in the arbitrary claim in claim 1-8.
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| CN201410171098.7A CN104049203B (en) | 2014-04-25 | 2014-04-25 | Pin with boundary scanning and testing function and integrated circuit with same |
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| CN201410171098.7A CN104049203B (en) | 2014-04-25 | 2014-04-25 | Pin with boundary scanning and testing function and integrated circuit with same |
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Cited By (6)
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| CN106483950A (en) * | 2016-12-21 | 2017-03-08 | 中国南方航空工业(集团)有限公司 | PLD detection method and device |
| CN109154633A (en) * | 2016-04-29 | 2019-01-04 | 德州仪器公司 | Full pad covering boundary scan |
| CN109192240A (en) * | 2018-08-28 | 2019-01-11 | 长鑫存储技术有限公司 | Marginal testing circuit, memory and marginal testing method |
| CN109387774A (en) * | 2018-12-05 | 2019-02-26 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of general-purpose circuit board suitable for boundary scan testing |
| CN113702798A (en) * | 2020-05-22 | 2021-11-26 | Oppo广东移动通信有限公司 | Boundary scan test method, device, equipment, chip and storage medium |
| CN113740710A (en) * | 2021-09-02 | 2021-12-03 | 展讯通信（上海）有限公司 | Output test circuit and chip |
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| CN109387774A (en) * | 2018-12-05 | 2019-02-26 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of general-purpose circuit board suitable for boundary scan testing |
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