CN104022120B - Three-dimensional semiconductor device and method for manufacturing the same - Google Patents
Three-dimensional semiconductor device and method for manufacturing the same Download PDFInfo
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- Non-Volatile Memory (AREA)
Abstract
A three-dimensional semiconductor device comprising a plurality of memory cells, each comprising: the channel layers are distributed along the direction vertical to the surface of the substrate; a plurality of interlayer insulating layers and a plurality of gate conductive layers alternately stacked along sidewalls of the channel layer; a gate dielectric layer between the plurality of interlayer insulating layers and sidewalls of the channel layer; the drain electrode is positioned on the top of the channel layer; and a source electrode located in the substrate between two adjacent memory cells of the plurality of memory cells; the memory device further comprises a plurality of second gate dielectric layers and a plurality of second channel layers around each of the plurality of memory cells, wherein the second gate dielectric layers comprise a tunneling layer, a memory layer and a blocking layer. According to the three-dimensional semiconductor memory device and the manufacturing method thereof, the current channel formed by stacking the auxiliary memory cell strings is formed around the vertical channel, so that the space utilization rate, the on-state current and the current of the memory string are effectively improved, and the reading current and the reading speed of the memory array are improved.
Description
Technical field
The present invention relates to a kind of semiconductor devices and its manufacture method, more particularly to a kind of three-dimensional semiconductor memory device
And its manufacture method.
Background technology
In order to improve the density of memory device, industry is directed to the memory cell that research and development reduce two-dimensional arrangement extensively
Size method.With the memory cell dimensions continual reductions of two-dimentional (2D) memory device, signal conflict and interference can show
Increase is write, so that being difficult to carry out multi-level-cell (MLC) operation.In order to overcome the limitation of 2D memory devices, industry has been ground
The memory device with three-dimensional (3D) structure has been sent out, it is integrated to improve by the way that memory cell is three-dimensionally disposed in into substrate
Density.
Specifically, can be deposited first on substrate multi-layer laminate structure (such as oxide and nitride it is alternately multiple
ONO structure)；Multi-layer laminate structure etching on substrate is formed along memory cell word by anisotropic etching technics
The distribution of line (WL) bearing of trend, perpendicular to multiple raceway groove through holes of substrate surface, (can go directly substrate surface or has certain mistake
Etching)；The material such as deposit polycrystalline silicon forms column raceway groove in raceway groove through hole；Formed along WL directions etching multi-layer laminate structure
The groove of through substrate, expose be enclosed in it is multilayer laminated around column raceway groove；Wet method removes a certain types of material in lamination
(such as hot phosphoric acid goes silicon nitride, or HF to remove silicon), the raised structures of cross direction profiles are left around column raceway groove；
The side wall deposition gate dielectric layer (such as high K medium material) of raised structures and grid conducting layer in groove (such as Ti, W,
Cu, Mo etc.) form gate stack；Perpendicular magnetic anisotropy etching removes the gate stack outside projection side plane, until exposing prominent
Play the gate dielectric layer of side；Etching stack structure forms source and drain and contacts and complete back end fabrication.Now, laminated construction exists
A part of projection that column trench sidewalls leave forms the separation layer between gate electrode, and the gate stack left be folded in it is more
Coordination electrode is used as between individual separation layer.When a voltage is applied to the gate electrode, the fringe field of grid can cause such as polysilicon material
Sensing forms source-drain area in the column trench sidewalls of material, thus forms the gate array that multiple series-parallel MOSFET are formed and records
The logic state stored.
Wherein, in order to which the multiple connection in series-parallel MOSFET signals of cellular zone are drawn, filling polycrystalline is deposited in column channel top
Silicon materials form drain region, and form the metal contact plug that is electrically connected with drain region with the bit line (bit- above being further electrically coupled to
Line, BL).In addition, the shared source region with Metal-silicides Contact is formed in substrate between multiple vertical pillar raceway grooves.
Under unit conducting state, electric current (is connected) from the vertical channel region around shared source region flow direction in control gate with wordline WL
Multiple source-drain areas that generation is sensed in vertical-channel are upward through under the control voltage effect of application, pass through the drain region of channel top
And further towards the bit line of top.However, due in polysilicon vertical-channel storage string number it is more, such as usually 14
The MOSFET structure of stacking, off-state current and electric current are opened than smaller so that reading electric current is smaller, reading speed is relatively low, nothing
Method is applied to high density, storage unit in high speed.
On the other hand, in order in vertical-channel side wall formation control gate, it usually needs be initially formed the vertical of exposed substrate
Groove but cross side etching off remove a certain layer in gate stack and left remaining as being dielectrically separated between control gate
Layer.Now, vertical trench occupies larger area, is unfavorable for the raising of integrated level.
The content of the invention
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, propose that a kind of innovative 3 D semiconductor is deposited
Memory device manufacture method.
Therefore, the invention provides a kind of three-dimensional semiconductor device, including multiple memory cell, the multiple memory cell
Each include：Channel layer, along the directional spreding perpendicular to substrate surface；Multiple interlayer insulating films and multiple Gate Electrode Conductives
Layer, it is alternately laminated along the side wall of the channel layer；Gate dielectric layer, positioned at the multiple interlayer insulating film and the channel layer
Side wall between；Drain electrode, positioned at the top of the channel layer；And source electrode, positioned at the two neighboring of the multiple memory cell
In substrate between memory cell；Around each of the multiple memory cell, further comprise that multiple second grids are situated between
Matter layer and multiple second channel layers, wherein, the second grid dielectric layer includes tunnel layer, accumulation layer, barrier layer.
Wherein, the cross sectional shape parallel to substrate surface of the channel layer and/or the second channel layer include selected from rectangle,
The geometry of square, rhombus, circle, semicircle, ellipse, triangle, pentagon, pentagon, hexagon, octagon and combinations thereof
Shape, and the solid geometric figure including developing to obtain selected from the geometry, hollow annular geometric figure or hollow
Ring-type perisphere and the composite figure at insulating barrier center.
Wherein, the gate dielectric layer further comprises tunnel layer, accumulation layer, barrier layer.
Wherein, nitridation is also included between gate dielectric layer and/or the second grid dielectric layer and the grid conducting layer
The barrier layer of thing.
Wherein, second channel layer and the channel layer material are identical or different.
Wherein, the source electrode, channel layer and drain electrode form the first current channel, the source electrode, the second channel layer and position
The second drain electrode at the top of the second channel layer forms multiple second current channels to increase ON state current and on-off ratio.
Present invention also offers a kind of manufacture method of three-dimensional semiconductor device, including step：Lining in memory cell areas
The stacked structure of first material layer and second material layer is formed on bottom；Etch the stacked structure and form multiple hole slots；Described
Gate dielectric layer and channel layer are formed in multiple hole slots；Fill and drain electrode is formed at the top of the channel layer；Selective etch removes the
Two material layers, leave the vertical trench of multiple horizontal grooves and exposure substrate；Grid conducting layer is formed in the groove；
Source electrode is formed in the substrate of the vertical trench bottom；In the vertical trench, between the multiple first material layer,
Multiple second grid dielectric layers and the second channel layer are formed on the source electrode, the second grid dielectric layer includes tunnel layer, deposited
Reservoir, barrier layer.
Wherein, the gate dielectric layer further comprises tunnel layer, accumulation layer, barrier layer.
Wherein, the barrier layer of nitride is also included between the gate dielectric layer and the grid conducting layer.
Wherein, second channel layer and the channel layer material are identical or different.
According to further embodiment, the invention provides a kind of manufacture method of three-dimensional semiconductor device, including step：
The stacked structure of first material layer and second material layer is formed on the substrate of memory cell areas；Etch the stacked structure formed it is more
Individual hole slot；Gate dielectric layer and channel layer are formed in the multiple hole slot；Fill and drain electrode is formed at the top of the channel layer；Selection
Property etching remove second material layer, leave multiple horizontal grooves and exposure substrate vertical trench；The shape in the groove
Into grid conducting layer；Shared source electrode is formed in the substrate of the vertical trench bottom；In the vertical trench, described
Multiple second grid dielectric layers and the second channel layer are formed between multiple first material layers, on the source electrode.
Wherein, the gate dielectric layer and the second grid medium Rotating fields are identical with material.
Wherein, further comprise forming drain electrode at the top of the channel layer, and/or formed at the top of second channel layer
Second drain electrode.
Wherein, the source electrode, channel layer and drain electrode form the first current channel, the source electrode, the second channel layer and position
The second drain electrode at the top of the second channel layer forms multiple second current channels, and the first current channel is in parallel with the second current channel
To improve device density while increase ON state current and on-off ratio.
Wherein, the multiple channel layer and the multiple second channel layer are arranged in a straight line or staggeredly, that is, from parallel
Seen in the plane of the substrate, be arranged in the multiple channel layer first group of ranks, arrange with the multiple second channel layer
Second group of ranks is arranged into overlap or interlock.
According to the three-dimensional semiconductor memory device and its manufacture method of the present invention, auxiliary storage is formed around vertical-channel
Unit string stacks the current channel formed, and the ON state current and electric current for effectively increasing space availability ratio and storage string become,
So as to improve the reading electric current of storage array and reading speed.
Brief description of the drawings
Describe technical scheme in detail referring to the drawings, wherein：
Fig. 1 to Fig. 9 be according to the present invention three-dimensional semiconductor memory device manufacture method each step sectional view and/
Or top view.
Embodiment
Referring to the drawings and schematical embodiment is combined to describe the feature of technical solution of the present invention and its skill in detail
Art effect, disclose the semiconductor storage unit and its manufacturer that read electric current and reading speed for effectively improving storage array
Method.It is pointed out that similar reference represents similar structure, term use herein " first ", " second ",
" on ", " under " etc. can be used for modifying various device architectures or manufacturing process.These modifications do not imply that institute unless stated otherwise
Modify space, order or the hierarchical relationship of device architecture or manufacturing process.
As shown in figure 1, first material layer 2A and second material layer 2B stacked structure 2 are alternatively formed on substrate 1.Substrate
1 material can include body silicon (bulk Si), body germanium (bulk Ge), silicon-on-insulator (SOI), germanium on insulator (GeOI) or
It is other compound semiconductor substrates, such as SiGe, SiC, GaN, GaAs, InP etc., and the combination of these materials.In order to
It is compatible with existing IC manufacturing process, the substrate of the preferably siliceous material of substrate 1, such as Si, SOI, SiGe, Si:C etc..Heap
The combination selected from following material of stack structure 2 and comprise at least a kind of dielectric：Such as silica, silicon nitride, amorphous carbon, class
Diamond amorphous carbon (DLC), germanium oxide, aluminum oxide, etc. and combinations thereof.First material layer 2A has the first Etch selectivity,
Second material layer 2B has the second Etch selectivity and is different from the first Etch selectivity.In a preferred embodiment of the invention
In, laminated construction 2A/2B is insulating materials, the combination of layer 2A/ layers 2B combination such as silica and silicon nitride, silica with
Combination of combination, silica or silicon nitride and amorphous carbon of polysilicon or non-crystalline silicon etc..In another preferred embodiment of the present invention
In, layer 2A and layer 2B are in wet etching condition or have under the conditions of oxygen plasma dry etching larger etching selection ratio
(it is greater than 5:1).Layer 2A, layer 2B deposition process include PECVD, LPCVD, HDPCVD, MOCVD, MBE, ALD, thermal oxide,
The various techniques such as evaporation, sputtering.
As shown in Fig. 2 cut away left side view, etching stacked structure 2 forms vertical break-through stacked structure up to exposing substrate 1
Hole slot 2TP is for definition channel region.Preferably, using RIE's or dry plasma etch anisotropic etching layer 2A/ layers 2B
Stacked structure 2, expose the side wall for the layer 2A/ layers 2B being alternately stacked on substrate 1 and substrate 1.It is highly preferred that control anisotropy
The process conditions of stacked structure 2 are etched to cause lateral etching speed to obtain high-aspect-ratio significantly less than longitudinal etching speed
(such as depth-to-width ratio AR is more than or equal to 10:1) vertical deep hole or deep trouth 2TP.The hole slot 2TP cut parallel to the surface of substrate 1
Cross sectional shape can be rectangle, square, rhombus, circle, semicircle, ellipse, triangle, pentagon, pentagon, six sides
The various geometries of shape, octagon etc..On the right side of Fig. 2 shown in top view, in a preferred embodiment of the invention, hole slot
2TP cross sectional shapes are circle, and multiple hole slots are arranged into Two-Dimensional Moment along parallel to wordline (WL) direction and/or bit line (BL) direction
Battle array.
As shown in figure 3, form gate dielectric layer stacked structure 3 in hole slot 2TP side walls.Deposition process include PECVD,
HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering etc..Not shown in figure, layer 3 preferably further comprises multiple sublayers,
Such as tunnel layer, accumulation layer, barrier layer.Wherein tunnel layer includes SiO2Or high-g value, wherein high-g value include but is not limited to
Nitride (such as SiN, AlN, TiN), metal oxide (predominantly subgroup and lanthanide element oxide, such as MgO,
Al2O3、Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3), nitrogen oxides (such as HfSiON), Perovskite Phase oxide
(such as PbZrxTi1-xO3(PZT)、BaxSr1-xTiO3(BST)) etc., tunnel layer can be the single layer structure or multilayer of above-mentioned material
Stacked structure.Accumulation layer is the dielectric material for having electric charge capture ability, such as SiN, HfO, ZrO etc. and combinations thereof, equally may be used
To be the single layer structure or multilayer lamination structure of above-mentioned material.Barrier layer can be the medium material such as silica, aluminum oxide, hafnium oxide
The single layer structure or multilayer lamination structure of material.In an embodiment of the invention, gate dielectric layer stacked structure 3 is, for example, to aoxidize
Silicon, silicon nitride, the ONO structure of silica composition.
As shown in figure 4, in hole slot 2TP, channel layer 4 is formed on gate dielectric layer stacked structure 3.The material of channel layer 4
Monocrystalline silicon, non-crystalline silicon, polysilicon, microcrystal silicon, monocrystalline germanium, SiGe, Si can be included:C、SiGe:C、SiGe:The semiconductor material such as H
Material, depositing operation are as described above.In one embodiment shown in Fig. 4 of the present invention, the depositional mode of channel layer 4 is to be locally filled with hole
Groove 2TP side wall and be formed as the hollow cylindrical with air-gap.In other embodiment not shown in figure of the present invention, selection
The depositional mode of channel layer 4 is formed in solid post, cavity ring or cavity ring and filled fully or partly to fill hole slot 2TP
The core of insulating barrier (not shown) -- shell mechanism.The shape of the horizontal cross-section of channel layer 4 is similar with hole slot 2TP and preferably
It is conformal, can be solid rectangle, square, rhombus, circle, semicircle, ellipse, triangle, pentagon, pentagon, six sides
The various geometries of shape, octagon etc., or develop to obtain for above-mentioned geometry hollow ring-type, barrel-like structure (simultaneously
And insulating barrier can be filled inside it)., can be further in channel layer 4 preferably for the hollow structure of column channel layer 4
Dielectric isolation layer 5 is filled in inner side, such as the layer 5 of such as silica material is formed by techniques such as LPCVD, PECVD, HDPCVD,
For the simultaneously isolating trenches channel layer 4 that supports, insulate.Hereafter, in the deposited atop drain region 4D of channel layer 4.Preferably, using with channel layer 4
Material it is same or similar (such as with Si similar in material SiGe, SiC etc., improve carrier to finely tune lattice constant and move
Shifting rate, so as to control unit device driveability) material be deposited on hole slot 2TP top and formed memory device unit crystalline substance
The drain region 4D of body pipe.If naturally, different from shown in Fig. 4, channel layer 4 is complete filling of solid construction, then channel layer 4 is whole
The part of individual top device then forms corresponding drain region 4D without extra drain region deposition step.
As shown in figure 5, selective etch to remove second material layer 2B, leaves by first material layer 2A, grid on substrate 1
The discrete vertical stratification that pole dielectric layer 3, channel layer 4, dielectric isolation layer 5 are formed.It is different according to layer 2A/ layers 2B material, can
Layer 2B is removed isotropically to etch with selective wet etching liquid.Specifically, for layer 2B materials, for silica material
Matter takes HF base corrosive liquids, uses hot phosphoric acid corrosion liquid for silicon nitride material, KOH is used for polysilicon or non-crystalline silicon material
Or the alkali corrosion liquid such as TMAH.Oxygen plasma dry method is selected it can in addition contain the layer 2B for the carbon-based material such as amorphous carbon, DLC
Etching so that O and C reacts to form gas and extract out.Further, using anisotropic dry etch process, for example, etc. from
Sub- dry etching, RIE etc., the first material layer 2A left along wordline WL bearing of trends etching, form the ribbon along WL directions
Structure.After removing layer 2B, left between multiple first material layer 2A laterally (parallel to the horizontal direction of substrate surface)
Multiple grooves, for forming coordination electrode later.It is worth noting that, in an embodiment of the invention, such as Fig. 5 institutes
Show, in order to which preferably selective etch removes horizontal layer 2B, exposed lining first can be formed using anisotropic etching technics
Multiple vertical openings or groove 2TP ' at bottom 1, these vertical openings or channel bottom will form shared source electrode, then from vertical
Opening or the side wall of groove start sideetching to remove horizontal layer 2B completely.In the prior art, in order that obtaining different hang down
4 lateral mechanical strength of vertical furrow channel layer is dielectrically separated from and improved between straight flute channel layer 4, is generally backfilled in open groove 2TP '
The isolation materials such as silica.But the vertical openings or groove of these oxidized silicon backfills occupy larger area so that make
Density for the channel layer 4 of memory cell areas reduces, and is unfavorable for effectively improving utilization rate.Therefore, the present invention is effectively utilized altogether
With the region above source electrode to form the second memory transistor, while area utilization is improved also effectively increasing device opens
State electric current and switching current ratio.
As shown in fig. 6, deposition filling forms grid conducting layer 6 in multiple grooves of transverse direction.Grid conducting layer 6 can be
Polysilicon, poly-SiGe or metal, wherein metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr,
W, the nitride of the metal simple-substance such as Ir, Eu, Nd, Er, La or the alloy of these metals and these metals, in grid conducting layer 6
Work function can also be adjusted doped with elements such as C, F, N, O, B, P, As.Between gate dielectric layer 3 and grid conducting layer 6 further preferably
The barrier layer (not shown) of nitride is formed by conventional methods such as PVD, CVD, ALD, barrier layer material is MxNy、MxSiyNz、
MxAlyNz、MaAlxSiyNz, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.Similarly, layer 6 can be single layer structure
It can be multilayer lamination structure.Now, first material layer 2A of multiple grid conducting layers about 6 is the dielectric material of insulation,
Therefore the dielectric isolation layer between grid conducting layer 6 is constituted.As shown in Fig. 6 cut away left side view, discrete multiple vertical stackings
There is space between structure, namely multiple stacked verticals first material layer 2A in the horizontal direction between there is space.
As shown in fig. 7, shared source region 1S is formed in substrate 1.It can enter by ion implantation doping and preferably
One step forms metal silicide (not shown) on surface and forms source region 1S.Metal silicide such as NiSi2-y、Ni1- xPtxSi2-y、CoSi2-yOr Ni1-xCoxSi2-y, wherein x be all higher than 0 less than 1, y be all higher than be equal to 0 be less than 1.Then, use and grid
The similar technique of pole dielectric layer 3 and material, auxiliary transistor is formed in the side periphery of first material layer 2A and grid conducting layer 6
Second grid dielectric layer 7, along vertical substrates directional spreding on the side of first material layer 2A and grid conducting layer 6.At this
Invent in a preferred embodiment, second grid dielectric layer 7 is preferably to be fully equivalent to the first memory transistor grid dielectric layer 4
Stacked structure, namely layer 7 includes tunnel layer, accumulation layer and barrier layer stack stack structure as described above.Then, in second gate
The second channel layer 8 of auxiliary transistor, its material are formed in the side of pole dielectric layer 7 and substrate 1 on common-source 1S surfaces
It is identical or different from channel layer 4 with preparation technology.That is, the silicon oxide insulation that the second channel layer 8 instead of prior art is situated between
Matter and be filled with vertical trench 2TP ', so as to improve device density and improve device drive ability.
As shown in figure 8, the second channel layer of etching seprating assistant transistor.Specifically, one is removed along WL directions etching
Point the second channel layer 8, remaining second channel layer 8 are folded in the matrix of the composition of channel layer 4, its width along WL directions,
Away from identical with channel layer 4, along the width and spacing in BL directions according to the electrology characteristic demand of auxiliary transistor depending on, namely according to
Depending on raising ON state current and reading speed need.
Hereafter, etch to form multiple contact holes for being sequentially connected each grid conducting layer 6 according to existing technique, filling gold
Category plug completes electrical connection, and is formed and 8 top of the second channel layer the second drain region 8D.Thus in cell memory array structure raceway groove
The stacked structure of the auxiliary transistor comprising the second channel layer 8 and second grid dielectric layer 7 is formd around layer 4 so that lead
Logical state next part electric current can flow to the drain region 8D at top, and and then inflow bit line from source electrode 1S by the second channel layer 8
BL (not shown), effectively increase space availability ratio and further increase ON state current and switching current ratio.
Although second channel layer be present in each both sides of channel layer 4 it is worth noting that, illustrate only in Fig. 8
8-- namely constitute dual current path structure, but between each channel layer 4 that can essentially rationally arrange spacing so as to
Inserted between each two channel layer 4 multiple second channel layers 8-- namely may be constructed three, four, five even more electric currents
Channel design.Although being arranged in a straight line in addition, illustrate only the second channel layer 8 in Fig. 8 with the first channel layer 4 along BL directions,
It is that can also actually be staggered.In addition, the cross sectional shape of the second channel layer 8 can be identical with the section of the first channel layer 4.
As shown in figure 9, ranks of second channel layer 8 along BL2 directions stagger with ranks of first channel layer 4 along BL1 directions
Certain distance.Thus, it is possible to the storage crystal pipe unit belonging to these channel layers is accessed by different bit line BL.It is similar
, the threshold voltage of the USG of selection transistor in vertical storage strings of transistors can be controlled to carry out share bit lines BL, or pass through two
The combination of individual selection transistor carrys out share bit lines BL.
According to the three-dimensional semiconductor memory device and its manufacture method of the present invention, auxiliary storage is formed around vertical-channel
Unit string stacks the current channel formed, and the ON state current and electric current for effectively increasing space availability ratio and storage string become,
So as to improve the reading electric current of storage array and reading speed.
Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art could be aware that need not
Depart from the scope of the invention and various suitable changes and equivalents are made to device architecture or method flow.It is in addition, public by institute
The teaching opened, which can make many, can be adapted to the modification of particular condition or material without departing from the scope of the invention.Therefore, it is of the invention
Purpose do not lie in and be limited to as realizing the preferred forms of the present invention and disclosed specific embodiment, it is and disclosed
Device architecture and its manufacture method by all embodiments including falling within the scope of the present invention.
Claims (10)
1. a kind of three-dimensional semiconductor device, including multiple memory cell, each of the multiple memory cell include：
Channel layer, along the directional spreding perpendicular to substrate surface；
Multiple interlayer insulating films and multiple grid conducting layers, it is alternately laminated along the side wall of the channel layer；
Gate dielectric layer, between the side wall of the multiple interlayer insulating film and the channel layer；
Drain electrode, positioned at the top of the channel layer；And
Source electrode, in the substrate between the two neighboring memory cell of the multiple memory cell；
Around each of the multiple memory cell, further comprise multiple second grid dielectric layers and multiple second raceway grooves
Layer, wherein, the second grid dielectric layer includes tunnel layer, accumulation layer, barrier layer, and the second channel layer directly contacts source electrode.
2. three-dimensional semiconductor device as claimed in claim 1, wherein, the channel layer and/or the second channel layer parallel to
The cross sectional shape of substrate surface is included selected from rectangle, square, rhombus, circle, semicircle, ellipse, triangle, pentagon, five
The geometry of angular, hexagon, octagon and combinations thereof, and it is solid several including developing to obtain selected from the geometry
What figure, hollow annular geometric figure or hollow annular perisphere and the composite figure at insulating barrier center.
3. three-dimensional semiconductor device as claimed in claim 1, wherein, the gate dielectric layer further comprises tunnel layer, deposited
Reservoir, barrier layer.
4. three-dimensional semiconductor device as claimed in claim 3, wherein, gate dielectric layer and/or the second grid dielectric layer
Also include the barrier layer of nitride between the grid conducting layer.
5. three-dimensional semiconductor device as claimed in claim 1, wherein, second channel layer is identical with the channel layer material
It is or different.
6. three-dimensional semiconductor device as claimed in claim 1, wherein, the source electrode, channel layer and drain electrode form the first electric current
Passage, the source electrode, the second channel layer and the second drain electrode at the top of the second channel layer form multiple second current channels
To increase ON state current and on-off ratio.
7. a kind of manufacture method of three-dimensional semiconductor device, including step：
The stacked structure of first material layer and second material layer is formed on the substrate of memory cell areas；
Etch the stacked structure and form multiple hole slots；
Gate dielectric layer and channel layer are formed in the multiple hole slot；
Fill and drain electrode is formed at the top of the channel layer；
Selective etch removes second material layer, leaves the vertical trench of multiple horizontal grooves and exposure substrate；
Grid conducting layer is formed in the groove；
Source electrode is formed in the substrate of the vertical trench bottom；
In the vertical trench, multiple second grid media are formed between the multiple first material layer, on the source electrode
Layer and the second channel layer, the second grid dielectric layer include tunnel layer, accumulation layer, barrier layer, and the second channel layer directly contacts
Source electrode.
8. three-dimensional semiconductor device manufacture method as claimed in claim 7, wherein, the gate dielectric layer further comprises tunnel
Wear layer, accumulation layer, barrier layer.
9. three-dimensional semiconductor device manufacture method as claimed in claim 7, wherein, the gate dielectric layer is led with the grid
Also include the barrier layer of nitride between electric layer.
10. three-dimensional semiconductor device manufacture method as claimed in claim 7, wherein, second channel layer and the raceway groove
Layer material is identical or different.
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| US9397113B2 (en) * | 2014-12-23 | 2016-07-19 | Macronix International Co., Ltd. | Memory architecture of array with single gate memory devices |
| CN105226066B (en) | 2015-08-20 | 2018-05-15 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN105097822B (en) * | 2015-09-12 | 2018-09-18 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN105355602B (en) * | 2015-10-19 | 2018-09-18 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and method for manufacturing the same |
| CN105261617B (en) * | 2015-10-28 | 2018-03-30 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and method for manufacturing the same |
| CN106340521B (en) * | 2016-09-30 | 2018-06-12 | 中国科学院微电子研究所 | Memory device, method of manufacturing the same, and electronic apparatus including the same |
| CN106298679A (en) * | 2016-09-30 | 2017-01-04 | 中国科学院微电子研究所 | Memory device, method of manufacturing the same, and electronic apparatus including the same |
| KR20180073161A (en) * | 2016-12-22 | 2018-07-02 | 삼성전자주식회사 | Vertical memory devices |
| KR102369654B1 (en) * | 2017-06-21 | 2022-03-03 | 삼성전자주식회사 | Semiconductor devices |
| CN107658311B (en) | 2017-08-28 | 2018-12-14 | 长江存储科技有限责任公司 | Three-dimensional storage |
| US10825867B2 (en) * | 2018-04-24 | 2020-11-03 | Micron Technology, Inc. | Cross-point memory array and related fabrication techniques |
| CN109037226B (en) * | 2018-09-19 | 2024-05-10 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| KR102674883B1 (en) * | 2018-12-21 | 2024-06-14 | 에스케이하이닉스 주식회사 | Non-Volatile Memory Device Having Stacked Cell Transistors and Methods of Operating the Same |
| US10930669B2 (en) * | 2019-02-12 | 2021-02-23 | Macronix International Co., Ltd. | Three dimensional memory device and method for fabricating the same |
| CN116209259B (en) * | 2022-11-01 | 2024-03-15 | 北京超弦存储器研究院 | Memory cell array structure and preparation method |
| CN115954381B (en) * | 2023-03-13 | 2023-06-06 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
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