CN105679761B - Three-dimensional semiconductor device and its manufacturing method - Google Patents
Three-dimensional semiconductor device and its manufacturing method Download PDFInfo
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- CN105679761B CN105679761B CN201610052951.2A CN201610052951A CN105679761B CN 105679761 B CN105679761 B CN 105679761B CN 201610052951 A CN201610052951 A CN 201610052951A CN 105679761 B CN105679761 B CN 105679761B
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
A kind of three-dimensional semiconductor device manufacturing method, comprising: the mask layer that alternate multiple first, second mask layers are constituted is formed on the substrate and stacks；Etch mask layer stacks to form channel hole, exposure substrate top, the first and second mask layer side walls；A part of the second mask layer is removed to form recess；Barrier layer is conformally formed in channel hole and recess；Accumulation layer is formed over the barrier layer；A part of selective etch removal accumulation layer；Tunnel layer is conformally formed in channel hole and recess.According to three-dimensional semiconductor memory device and its manufacturing method of the invention, the access of horizontal proliferation is truncated, using isolated accumulation layer structure so as to improve data retention characteristics.
Description
Technical field
The present invention relates to a kind of semiconductor devices and its manufacturing methods, more particularly to a kind of three-dimensional semiconductor memory device
And its manufacturing method.
Background technique
In order to improve the density of memory device, industry is dedicated to the memory cell that research and development reduce two-dimensional arrangement extensively
Size method.With the memory cell dimensions continual reductions of two-dimentional (2D) memory device, signal conflict and interference can be shown
It writes and increases, so that being difficult to carry out multi-level-cell (MLC) operation.In order to overcome the limitation of 2D memory device, industry has been ground
The memory device with three-dimensional (3D) structure has been sent out, it is integrated to improve by the way that memory cell is three-dimensionally disposed in substrate
Density.
Specifically, can deposit on substrate first multi-layer laminate structure (such as oxide and nitride it is alternately multiple
ONO structure)；Multi-layer laminate structure etching on substrate is formed along memory cell word by anisotropic etching technics
Line (WL) extending direction distribution, perpendicular to substrate surface multiple channel through-holes (can go directly substrate surface or have certain mistake
Etching)；The laminated construction of selective etch channel through-hole side wall is to form multiple recess, such as partly etching removal ONO knot
A part of nitride in structure and in upper layer and lower layer oxide formed recess, then sequentially form in the valley barrier layer,
The stacked dielectric layer that accumulation layer, tunnel layer are constituted；The materials such as deposit polycrystalline silicon form column channel in channel through-hole；Along WL
Direction etching multi-layer laminate structure forms the groove of through substrate, and exposing is enclosed in multilayer laminated around column channel；Wet process
A certain types of material (such as completely removing oxide in ONO structure, only retain nitride) in removal lamination, in column ditch
The raised structures of cross direction profiles are left around road；Side wall deposition gate dielectric layer (such as the high K medium of raised structures in the trench
Material) and grid conducting layer (such as Ti, W, Cu, Mo etc.) form gate stack, for example including bottom selection grid polar curve, illusory
Grid line, wordline, top selection grid polar curve；Gate stack except perpendicular magnetic anisotropy etching removal protrusion side plane, until
Expose the gate dielectric layer of protrusion side；Etching stack structure forms source and drain and contacts and complete back end fabrication.At this point, lamination
Structure forms the separation layer between gate electrode in a part of protrusion that column trench sidewalls leave, and the gate stack folder left
It is located between multiple separation layers as coordination electrode.When a voltage is applied to the gate electrode, the fringe field of grid can make for example more
Induction forms source-drain area in the column trench sidewalls of crystal silicon material, thus constitutes the gate array that multiple series-parallel MOSFET are constituted
And record stored logic state.By controlling the voltage of grid, so that distribution of charges changes in accumulation layer, thus right
It should be in the change of logic state.
However, as shown in Figure 1, in the local structure figure of above-mentioned device, the charge (semicircular area accumulated in accumulation layer
It is shown) over time threshold voltage shift shown in Fig. 2 can be caused gradually to external diffusion.Wherein, 1. curve in Fig. 2
It drifts about corresponding to Vt caused by the charge spread perpendicular to channel distribution arrangement in Fig. 1 to control grid, barrier insulating layer.It removes
Except this, the charge accumulated in accumulation layer can not only be spread to directly corresponding grid direction, can also be further to adjacent
The corresponding charge storaging area diffusion of (along channel distribution arrangement namely vertical direction) grid, causes erasing hole and programs electronics
Between unnecessary neutralization, lead to the bigger Vt drift as shown in 1.+2. curve in Fig. 2.
Summary of the invention
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, propose that a kind of innovative 3 D semiconductor is deposited
The access of horizontal proliferation is truncated using isolated accumulation layer structure for memory device and its manufacturing method, so as to improve data holding
Characteristic.
For this purpose, one aspect of the present invention provides a kind of three-dimensional semiconductor device manufacturing method, comprising: friendship is formed on the substrate
The mask layer that multiple first, second mask layers replaced are constituted stacks；Etch mask layer stacks to form channel hole, exposure substrate top
Portion, the first and second mask layer side walls；A part of the second mask layer is removed to form recess；It is conformal in channel hole and recess
Ground forms barrier layer；Accumulation layer is formed over the barrier layer；A part of selective etch removal accumulation layer；In channel hole and recess
In be conformally formed tunnel layer.
Wherein, the first mask layer is insulating materials, and the second mask layer is semiconductor material or insulating materials；Preferably, absolutely
Edge material be silicon nitride, silica, silicon oxynitride, amorphous carbon, carbonitride of silicium, silicon oxide carbide, boron nitride, aluminium oxide it is any
Or combinations thereof；Preferably, semiconductor material is silicon, germanium or combinations thereof；Preferably, semiconductor material is polycrystalline, amorphous, crystallite.
Wherein, the step of forming barrier layer further comprises: being conformally formed adhesion layer in channel hole and recess；It executes
Oxidation and/or nitriding process, convert barrier layer at least part of adhesion layer；Preferably, oxidation technology ISSG,
FRE--RTO, chemical oxidation；Preferably, adhesion layer material is same or similar with the second mask layer material.
Wherein, the step of a part of selective etch removal accumulation layer further comprises: in channel hole and recess altogether
Form to shape sacrifice bed course；Oxidation and/or nitriding process are executed, is converted into sacrificial layer while backing layer portion will be sacrificed, in the valley
Accumulation layer on leave protective layer；Remove sacrificial layer；Selective etch removes a part of accumulation layer, and reservation is covered by protective layer
The remaining accumulation layer of lid.
Wherein, it formed before being recessed, form channel hole and further comprise later: the epitaxial growth in the base substrate of channel hole
Form epitaxial layer.
Wherein, the material of barrier layer and/or tunnel layer is silica or high-g value；Optionally, accumulation layer material is nitridation
Silicon, hafnium oxide, zirconium oxide, yttrium oxide or combinations thereof.
Wherein, forming tunnel layer further comprises later step: forming channel layer in channel hole and recess；In channel layer
Drain electrode is formed on top；Etch mask layer stacks to form vertical openings, the remaining second mask layer side wall of exposure and substrate top；Choosing
Selecting property etching removes remaining second mask layer, leaves groove；Common source is formed in vertical openings bottom；Control is formed in a groove
Grid processed；Form source and drain deriving structure.
The present invention also provides a kind of three-dimensional semiconductor devices, comprising: channel layer, along the direction point perpendicular to substrate surface
Cloth；Multiple insulating layers, it is alternately laminated along the side wall of channel layer；Grid is controlled, is folded between adjacent insulating layer；Grid is exhausted
Edge layer stacks, and is distributed between channel layer and control grid, including barrier layer, accumulation layer and tunnel layer, wherein barrier layer and tunnel
Wear that layer is continuously distributed and accumulation layer Disjunct distribution.
It wherein, further include drain electrode, positioned at the top of channel layer；And source electrode, positioned at the two neighboring of multiple storage units
In substrate between storage unit.
Wherein, the material of barrier layer and/or tunnel layer is silica or high-g value；Optionally, accumulation layer material is nitridation
Silicon, hafnium oxide, zirconium oxide, yttrium oxide or combinations thereof.
According to three-dimensional semiconductor memory device and its manufacturing method of the invention, it is truncated using isolated accumulation layer structure
The access of horizontal proliferation, so as to improve data retention characteristics.
Detailed description of the invention
Carry out the technical solution that the present invention will be described in detail referring to the drawings, in which:
Fig. 1 is the partial sectional view of prior art 3D memory device；
Fig. 2 is the Vt drift schematic diagram of device shown in Fig. 1；
Fig. 3 A to Fig. 3 J is each step according to the three-dimensional semiconductor memory device manufacturing method of the embodiment of the present invention
Cross-sectional view；
Fig. 4 is the partial enlarged view of structure shown in Fig. 3 J；
Fig. 5 is the schematic flow chart according to the three-dimensional semiconductor memory device manufacturing method of the embodiment of the present invention.
Specific embodiment
Come the feature and its skill of the present invention will be described in detail technical solution referring to the drawings and in conjunction with schematical embodiment
Art effect discloses the semiconductor storage unit and its manufacturing method for effectively improving data retention characteristics.It should be pointed out that
Similar appended drawing reference indicates similar structure, and term " first " use herein, " second ", "upper", "lower" etc. can
For modifying various device architectures or manufacturing process.These modifications do not imply that modified device architecture or system unless stated otherwise
Make space, order or the hierarchical relationship of process.
As shown in Figure 3A, multiple channel holes and epitaxial substrate are etched.
There is provided substrate 1, material may include body silicon (bulk Si), body germanium (bulk Ge), silicon-on-insulator (SOI),
Germanium on insulator (GeOI) either other compound semiconductor substrates, such as SiGe, SiC, GaN, GaAs, InP etc., and
The combination of these substances.In order to compatible with existing IC manufacturing process, the substrate preferably substrate containing silicon material, such as Si,
SOI, SiGe, Si:C etc..
Using for example including LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering, oxidation etc.
Film-forming process, form mask layer and stack 2, including alternately stacked multiple first mask layer 2A and multiple second mask layer 2B.
Preferably, material is insulating materials and mutually different between adjacent sublayers: such as layer 2A is silica
SiOx, layer 2B is silicon oxynitride SiOxNyOr silicon nitride SiNy；Or layer 2A is silicon oxide or silicon nitride or nitrogen oxidation
Silicon, layer 2B are amorphous carbon, fire sand, silicon oxide carbide, boron nitride, aluminium oxide etc.；Or each sublayer 2A/2B general formula is
SiOxNy, but ON atom ratio difference is between adjacent layer to obtain different Etch selectivities.In one preferred implementation of the present invention
In example, the first mask layer 2A is silica, and the second mask layer 2B is silicon nitride.In other preferred embodiments of the invention, layer 2B
Or the semiconductor materials such as polysilicon/germanium, amorphous silicon/germanium, microcrystal silicon/germanium, and layer 2A is then above-mentioned insulating materials, as long as
There is biggish Etch selectivity between adjacent layer.
Preferably, the number of the first mask layer 2A is one more than the second mask layer 2B, for example, stacking lowest level and most push up
Layer is the first mask layer 2A, and it is further preferred that the first mask layer 2A thickness of top will be significantly greater than remaining
First mask layer 2A or the second mask layer 2B.For example, other than the 2A of top, remaining layer of 2A, 2B thickness is 10~
200nm, and the 2A of top is entire for use as the etch hardmask at top, protective layer or covering with a thickness of 300~1000nm
The dielectric isolation layer of chip.
Mask layer stacks 2A/2B in etched substrate, and the multiple deep hole 2T for forming exposure stacking side wall (only show one in Fig. 3 A
It is a).Anisotropic etch process is selected, such as selects the fluorine-based (C of carbonxHyFzConstitute fluorohydrocarbon) plasma as etching gas
Body dry etching or RIE etch aforementioned mask layer heap vertically downward and fold 2A/2B, until exposure 1 surface of substrate, forms multiple depths
Hole or groove 2T (although Fig. 3 A only shows one, can actually exist multiple in the plan view, correspond to multiple storages
Device unit), deep hole or groove 2T expose the side wall of multiple mask layer 2A and 2B, will be used to be subsequently formed charge storage structure with
And channel layer, therefore also it is referred to as channel hole 2T.The cross sectional shape for being parallel to the channel hole 2T cut on 1 surface of substrate can be square
Shape, rectangular, diamond shape, circle, semicircle, ellipse, triangle, pentagon, pentagon, hexagon, octagon etc. are various several
What shape.Preferably, channel hole 2T gos deep under 1 surface of substrate, namely executes over etching, in order to increase subsequently epitaxial growing
The growth area and depth of channel layer or epitaxial layer improve epitaxial growth quality and mechanical support intensity.
Optionally, epitaxial layer 1E is formed using epitaxial growth technology in the bottom of each channel hole 2T.Epitaxy technique can be with
Using techniques such as PECVD, HDPCVD, MBE, ALD, UHVCVD, MOCVD, the lattice constant of epitaxial layer 1E material can be with substrate 1
It is same or similar, such as epitaxial layer 1E material is Si, SiGe, SiC, SiGeC etc..Epitaxial layer 1E will act as the common source of future device
The channel region of area or bottom selection transistor.As shown in Figure 3A, at least more than one the first mask layer of the thickness of epitaxial layer 1E
The second top mask layer 2B of the bottom is crossed at the top of the sum of 2A and second mask layer 2B thickness namely epitaxial layer 1E
On, enable the bottom control grid of the second mask layer 2B of substitution to cross over lift when the selection transistor of bottom in order to be subsequently formed
The channel region risen.
As shown in Figure 3B, the laterally etched mask layer of selectivity stacks 2A/2B, and the second of the removal channel hole side 2T exposure is covered
A part of mold layer 2B forms multiple lateral concave 2R.In a preferred embodiment of the invention, using the fluorine-based etching gas of carbon
Plasma dry etch process, reduce C:F atomic ratio and etching made to tend to isotropism, and further preferably adjust
H:F atomic ratio to increase the Etch selectivity between adjacent sublayers, namely the first mask layer 2A of etching speed it is substantially zeroed or
5% of speed less than the second mask layer 2B of etching.Further, it is also possible to select wet etching liquid, such as hot phosphoric acid is for nitridation
Silicon, HF acid are directed to silica, strong oxidizer (hydrogen peroxide, deionized water ozoniferous) and strong acid (sulfuric acid, nitric acid) mixture needle
To silicon oxynitride, SiGe etc., TMAH is directed to the silicon materials of each crystal form, different, each crystal orientation using chemical property between material
Etching speed is different and targetedly etches a part of the second mask layer 2B of removal.The shape of finally formed recess 2B is unlimited
The rectangle shown in Fig. 3 B, or other shapes, such as triangle, rectangle, rectangular, trapezoidal, inverted trapezoidal, Σ shape (multistage
Broken line is connected), C-shaped (more than 1/2 curved surface, curved surface can be disc, ellipsoid, hyperboloid), (1/2 curved surface, curved surface can be with for D-shaped
It is disc, ellipsoid, hyperboloid) etc..
As shown in Fig. 3 C, 3D, barrier layer 2D is formed.
In an embodiment of the invention, barrier layer 2D is silica or high-g value (including but not limited to AlOx、AlNx、
HfOx、HfAlxOy, HfSiON etc.), using the techniques such as HDPCVD, MBE, ALD be conformally deposited on channel hole 2T side and
Bottom and the side for the 2R that is recessed, cover multiple first mask layer 2A, multiple second mask layer 2B and epitaxial layer 2E.
Due to the presence for the 2R that is recessed, when barrier layer 2D material differs greatly with the second mask layer 2B material, barrier layer 2D
It is not sufficiently good in the recess side 2R and the possible step coverage in the second interface mask layer 2B, in order to further increase barrier layer 2D
Conformability and step coverage, the application preferably formed using two-step process shown in Fig. 3 C, 3D in another embodiment
Barrier layer 2D.
As shown in Figure 3 C, the adhesion layer 2C of the techniques conformal deposited isolation material such as HDPCVD, MBE, ALD, material are utilized
It is same or similar with the second mask layer 2B material, such as the second mask layer 2B is that then adhesion layer 2C is silicon nitride, nitrogen oxygen to silicon nitride
SiClx, fire sand, or be silicon oxynitride but N and O atom ratio difference.
Then as shown in Figure 3D, barrier layer 2D is converted by adhesion layer 2C.For example, by using ISSG, (steam in situ generates oxygen
Change), FRE--RTO (free radical rapid thermal oxidation), chemical oxidation (such as deionized water ozoniferous or hydrogen peroxide wet-treating,
Or ozone, oxygen gas plasma dry process) etc. oxidation technologies silicon nitride, silicon oxynitride, fire sand are converted into oxidation
Silicon, or silica, silicon oxide carbide, silicon oxynitride are converted to by nitridation using nitriding process (annealing in nitrogen containing atmosphere high temperature)
Silicon.Particularly, for the purpose for further increasing barrier film quality, reducing conversion process median surface defect, it is preferred to use
ISSG executes oxidation technology, thus avoids adhesion layer 2C and the second mask layer 2B interface excessive erosion and removes or rupture.By
This barrier layer 2D thinner thickness (such as 1~10nm) formed and can simultaneously by the passivation of the sharp corner of the 2R that is recessed or sphering,
To improve the step coverage of deposition, reduce the electric field grotesque in corner, device reliability is further increased.It is further preferred that
The conversion of adhesion layer 2C to barrier layer 2D can be partly namely the part adhesion layer 2C on surface is converted into barrier layer 2D,
And it remains remaining part adhesion layer 2C (not shown) and is collectively formed with barrier layer 2D and stop stacked structure to effectively improve resistance
Keep off effect and interlayer adhesion force.
Then deposition accumulation layer 2E, is covered on the 2D of barrier layer, namely has been partially filled with the side of channel hole 2T, the 2R that is recessed
Wall.Using the techniques conformal deposited accumulation layer 2E such as HDPCVD, MBE, ALD, material is can be in the interface with barrier layer 2D
And any dielectric material with the interface storage charge of the following tunnel layer 4, such as silicon nitride SiNx, hafnium oxide HfOx, oxidation
Zirconium ZrOx, yttrium oxide YOxOr combinations thereof.As shown in FIGURE 3 E, accumulation layer 2E is continuously distributed at the beginning.
As shown in Fig. 3 E~Fig. 3 G, protective layer 3A is formed on accumulation layer 2E, in recess 2R.As shown in FIGURE 3 E, in channel
At least partly (or completely) deposited sacrificial bed course 3A can also leave part at least to fill recess 2R in hole 2T and recess 2R
Channel hole 2T is not filled with raising subsequent oxidation/nitriding process speed.Depositing operation is that HDPCVD, MBE, ALD etc. are conformal
Technique, sacrifice bed course 3A material are polysilicon/germanium, amorphous silicon/germanium, microcrystal silicon/germanium or amorphous carbon.Execute oxidation or nitridation
Sacrifice bed course 3A is partially converted into the sacrificial layer 3B of oxide or nitride by technique.Due to the presence for the 2R that is recessed, work is converted
Skill can not convert completely the sacrifice bed course 3A for the depths 2R that is recessed, therefore in recess 2R other than the sacrificial layer 3B converted
Partial sacrifice bed course 3A as illustrated in Figure 3 F is also retained, which will be used to protect the part accumulation layer of its side
2E.Then as shown in Figure 3 G, etching removal sacrificial layer 3B is to expose remaining sacrifice bed course namely protective layer 3A, for example, by using HF
Sacrificial layer 3B of the acid for oxidation silicon material.As shown in Figure 3 G, multiple protective layer 3A are distributed in multiple recess 2R, are covered and are deposited
A part of reservoir 2E.
As shown in figure 3h, selective etch removes part accumulation layer 2E, is formed and is separated by the first mask layer 2A, barrier layer 2D
The multiple accumulation layer sections opened.Isotropic dry etching or wet etching, such as hot phosphoric acid can be used for nitridation
The accumulation layer 2E of silicon material, or adjust etching gas and match so that the etching speed for accumulation layer 2E is noticeably greater than to other
The etching speed (such as big 5 times, 10 times or even 20 times or more) of adjacent materials.In the process, since accumulation layer 2E is protected
The part layer 3A covers, therefore will be retained by the part accumulation layer 2E covered, and exposed rest part is etched removal, namely
So that accumulation layer 2E quilt " pinch off ", to avoid the lateral transfer of charge between adjacent storage layers 2E, reduce threshold voltage at any time
Between the drift that changes, as shown in Figure 4.
As shown in fig. 31, etching removal protective layer 3A.Isotropic dry etching or wet etching, example can be used
It, will be on each accumulation layer section 2E if TMAH is for silicon materials or oxygen plasma the etching removal amorphous carbon etc. of various crystal forms
Protective layer 3A completely remove.
Finally, as shown in figure 3j, forming tunnel layer 4 in channel hole 2T and recess 2R.Utilize HDPCVD, MBE, ALD etc.
Technique conformal deposited tunnel layer 4, material includes SiO2Or high-g value, wherein high-g value include but is not limited to nitride (such as
SiN, AlN, TiN, TaN), metal oxide (predominantly subgroup and lanthanide element oxide, such as MgO, Al2O3、
Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3), nitrogen oxides (such as SiON, HfSiON), Perovskite Phase oxide
(such as PbZrxTi1--xO3(PZT)、BaxSr1--xTiO3(BST)) etc., tunnel layer can be the single layer structure or more of above-mentioned material
Layer heap stack structure.
Hereafter, 3D memory construction is continuously formed.
For example, being conformally formed perpendicular to substrate surface and prolonging using techniques such as MOCVD, MBE, ALD in the 2T of channel hole
The channel layer (being not shown below) stretched.Channel layer is semiconductor material, equal or close with epitaxial layer 1E lattice constant.Channel
Layer material can be selected from IV race element semiconductor, IV compound semiconductor, III--V race or II--VI compound semiconductor,
Si, Ge, SiGe, SiC, GeC, GeSn, InSn, InN, InP, GaN, GaP, GaSn, GaAs etc. and combinations thereof.Channel layer
Depositional mode is the hollow cylindrical for being locally filled with the side wall of channel hole 2T and being formed to have air-gap.Do not show in figure of the present invention
In other embodiments out, the depositional mode of channel layer is selected fully or partly to fill channel hole 2T, forms solid post, sky
Core -- the shell mechanism of filling insulating layer in thimble or cavity ring.The shape and channel hole 2T of the horizontal cross-section of channel layer
It is similar and preferably conformal, it can be solid rectangle, rectangular, diamond shape, circle, semicircle, ellipse, triangle, five sides
The various geometries of shape, pentagon, hexagon, octagon etc., or the hollow ring to develop for above-mentioned geometry
Shape, barrel-like structure (and insulating layer can be filled inside it).Preferably for hollow column channel layer structure, Ke Yijin
One step fills dielectric isolation layer on the inside of channel layer, such as forms such as silica by techniques such as LPCVD, PECVD, HDPCVD
The layer of material is used to support, insulate simultaneously isolating trenches channel layer 6A.
Hereafter, drain region is deposited at the top of channel layer.Preferably, using it is same or similar with channel layer material (such as with
Material amorphous Si, polycrystalline Si, SiGe, SiC etc. similar in Si, improve carrier mobility to finely tune lattice constant, thus
The driveability of control unit device) material be deposited on the top of channel hole 2T and doping forms memory device unit transistor
Drain region.Naturally, channel layer is then constituted in the part of entire top device if channel layer is fully filled solid construction
Corresponding drain region is without additional drain region deposition step.In other embodiments of the present invention, drain region may be metal, metal
Nitride, metal silicide, such as W, WN, WSi etc. are any or combinations thereof, constitute half contact of gold and form Schottky at top
Type device.
It forms interlayer dielectric layer (ILD is not shown) and etches exposing substrate.ILD can be CVD or the oxygen of oxidizing process formation
The low-k materials that the techniques such as SiClx or spin coating, spraying, silk-screen printing are formed, low-k materials include but is not limited to organic low-k materials
(such as organic polymer containing aryl or polynary ring), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen are thin
Film, fluorine silica glass, BSG, PSG, BPSG), porous low k material (such as Quito hole two silicon three oxygen alkane (SSQ) low-k materials, porous two
Silica, porous SiOCH, it mixes C silica, mix the porous amorphous carbon of F, porous diamond, porous organic polymer).It is preferred that
Ground, cmp planarization ILD.Anisotropic etch process is executed using photoresist mask graph (not shown), successively vertical etch
ILD, mask stack 2A/2B, until exposure 1 surface of substrate, forms multiple vertical openings (not shown).Multiple vertical openings will enclose
Averagely have 2~6 vertical openings around periphery around each vertical-channel, such as each vertical-channel.The section shape of opening
Shape can be identical as channel hole 2T.Exposure is stacked the side away from channel region of 2A/2B by vertical openings, so as to then selective
The second mask layer 2B of etching removal.
Isotropic etching technique is selected, selective etch removes the second mask layer 2B.It is different according to each sublayer material,
Wet etching liquid be can choose isotropically to etch the required sublayer of removal.Specifically, HF is taken for oxidation silicon material
Base corrosive liquid uses hot phosphoric acid corrosion liquid for silicon nitride material, for polysilicon or amorphous silicon material using KOH or TMAH etc.
Alkali corrosion liquid.In addition it can select oxygen plasma dry etching for carbon-based materials such as amorphous carbon, DLC, so that O and C
Reaction forms gas and extracts out.After removing the second mask layer 2B, transverse direction is left between the first mask layer 2A and (is parallel to lining
The horizontal direction of bottom surface) multiple groove (not shown), with for forming coordination electrode later.
Common-source (not shown) is then formed in vertical openings base substrate 1.Such as ion implantation technology is selected, from
1 bottom of vertical injection substrate of alignment forms multiple common-sources, and preferably further forms metal silication on surface
Object (not shown) is to reduce surface contacted resistance.Metal silicide such as NiSi2--y、Ni1--xPtxSi2--y、CoSi2--yOr Ni1-- xCoxSi2--y, wherein x is all larger than 0 and is all larger than equal to 0 less than 1, y less than 1.Common source area has different doping types from substrate,
Different carrier paths is formed hence for erasable read operation.
The depositional control grid in transverse concave groove.The step coverages such as depositing operation such as HDPCVD, MOCVD, MBE, ALD
Well, the high conformal film-forming process of filling rate.Polysilicon, the amorphous silicon, microcrystal silicon of grid material such as (n or p) doping are controlled,
It is also possible to metal, metal alloy, conductive metal nitride and/or oxide and/or silicide, can be the list of these materials
Layer structure, is also possible to the multilayered structure (such as stack) of these materials, for example, metal be selected from Co, Ni, Cu, Al, Pd, Pt, Ru,
Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La's is any or combinations thereof.Control grid in can also doped with C, F, N,
O, the elements such as B, P, As are to adjust work function.Preferably, control gate extremely metal_based material.
Finally, completing device line.Filling forms the deriving structure of source region in vertical openings.Such as elder generation CVD or oxidation/
Nitriding process formed insulation material layer and anisotropic etching removal bottom expose source electrode and formed side wall to avoid with bit line
Control gate is extremely short to be connect, and the soruce terminal of metal material, material are then formed by techniques such as MOCVD, ALD, evaporation, sputterings
Such as metal, it may include the metals such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La
The conductive nitride or conductive oxide of the alloy and these metals of simple substance or these metals.Preferably, cmp planarization draws
Outlet is until exposure ILD.Then etching ILD is until exposure drain region, fills the material similar with lead-out wire and form bit line lead-out wire.
The device section view partial enlarged view finally realized is as shown in figure 4, a kind of three-dimensional semiconductor device, including multiple storages
Unit, each of multiple storage units include: channel layer (not shown), along the directional spreding perpendicular to substrate surface；It is multiple
(the first mask) insulating layer 2A is alternately laminated along the side wall of channel layer；Control grid (position of the second mask layer 2B of substitution) folder
It is located between adjacent insulating layer 2A；Gate insulator stack is distributed between channel layer and control grid, including barrier layer
2D, accumulation layer 2E and tunnel layer 4, wherein barrier layer 2D and tunnel layer 4 is continuously distributed and accumulation layer 2E Disjunct distribution.Further,
Device further includes drain electrode, positioned at the top of channel layer；And source electrode, positioned at multiple storage units two neighboring storage unit it
Between substrate in.The material and construction feature of other each layers are as described in process part, and details are not described herein.
According to three-dimensional semiconductor memory device and its manufacturing method of the invention, it is truncated using isolated accumulation layer structure
The access of horizontal proliferation, so as to improve data retention characteristics.
Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art, which could be aware that, to be not necessarily to
It is detached from the scope of the invention and various suitable changes and equivalents is made to device architecture or method flow.In addition, public by institute
The introduction opened, which can make many, can be adapted to the modification of particular condition or material without departing from the scope of the invention.Therefore, of the invention
Purpose do not lie in and be limited to as the disclosed specific embodiment for realizing preferred forms of the invention, and it is disclosed
Device architecture and its manufacturing method will include all embodiments for falling within the scope of the present invention.
Claims (12)
1. a kind of three-dimensional semiconductor device manufacturing method, comprising:
The mask layer that alternate multiple first, second mask layers are constituted is formed on the substrate to stack；Etch mask layer stacks to be formed
Channel hole, exposure substrate top, the first and second mask layer side walls；
A part of the second mask layer is removed to form recess；
Barrier layer is conformally formed in channel hole and recess；
Accumulation layer is formed over the barrier layer；
Selective etch removes a part of accumulation layer with pinch off accumulation layer, further comprises, conformal in channel hole and recess
Ground, which is formed, sacrifices bed course, executes oxidation and/or nitriding process, is converted into sacrificial layer with sacrificing backing layer portion, in the valley
Protective layer is left in accumulation layer, removes sacrificial layer, and selective etch removes a part of accumulation layer, and reservation is covered by protective layer
Remaining accumulation layer；
Tunnel layer is conformally formed in channel hole and recess.
2. three-dimensional semiconductor device manufacturing method as claimed in claim 1, wherein the first mask layer is insulating materials, the second mask
Layer is semiconductor material or insulating materials.
3. three-dimensional semiconductor device manufacturing method as claimed in claim 2, wherein insulating materials is silicon nitride, silica, nitrogen oxidation
Silicon, amorphous carbon, carbonitride of silicium, silicon oxide carbide, boron nitride, aluminium oxide it is any or combinations thereof.
4. three-dimensional semiconductor device manufacturing method as claimed in claim 2, wherein semiconductor material is silicon, germanium or combinations thereof.
5. three-dimensional semiconductor device manufacturing method as claimed in claim 2, wherein semiconductor material is polycrystalline, amorphous, crystallite.
6. three-dimensional semiconductor device manufacturing method as claimed in claim 1, wherein the step of forming barrier layer further comprises:
Adhesion layer is conformally formed in channel hole and recess；Oxidation and/or nitriding process are executed, at least part of adhesion layer is converted
For barrier layer.
7. three-dimensional semiconductor device manufacturing method as claimed in claim 6, wherein oxidation technology ISSG, FRE-RTO, chemical oxygen
Change.
8. three-dimensional semiconductor device manufacturing method as claimed in claim 6, wherein adhesion layer material is identical as the second mask layer material
Or it is close.
9. three-dimensional semiconductor device manufacturing method as claimed in claim 1, wherein before forming recess, form the laggard of channel hole
One step includes: to be epitaxially-formed epitaxial layer in the base substrate of channel hole.
10. three-dimensional semiconductor device manufacturing method as claimed in claim 1, wherein the material of barrier layer and/or tunnel layer is oxidation
Silicon or high-g value.
11. such as the three-dimensional semiconductor device manufacturing method of claim 10, wherein accumulation layer material is silicon nitride, hafnium oxide, oxygen
Change zirconium, yttrium oxide or combinations thereof.
12. three-dimensional semiconductor device manufacturing method as claimed in claim 1, wherein forming tunnel layer further comprises later step:
Channel layer is formed in channel hole and recess；Drain electrode is formed at the top of channel layer；Etch mask layer stacks to form vertical openings, cruelly
Reveal remaining second mask layer side wall and substrate top；Selective etch removes remaining second mask layer, leaves groove；It is hanging down
Common source is formed on straight opening bottom；Control grid is formed in a groove；Form source and drain deriving structure.
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