CN104008997A - 一种超低介电常数绝缘薄膜及其制备方法 - Google Patents
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Abstract
本发明公开了一种超低介电常数绝缘薄膜及其制备方法,该方法包含:步骤1.利用等离子体增强化学气相沉积技术沉积薄膜:MTES和LIMO作为反应源,氦气为载气被导入到化学气相沉积反应腔中,沉积形成50-100nm的绝缘层,MTES和LIMO的流量比=1∶1~1∶2.5;步骤2.采用Ar等离子体对绝缘层表面进行原位处理以形成致密的修饰层;步骤3.重复上述步骤1和2,得到目标厚度的绝缘薄膜;步骤4.对绝缘薄膜进行高温退火,形成超低介电常数绝缘薄膜。本发明创新性地采用了交替等离子体增强化学气相沉积绝缘薄膜和后等离子体处理的方法,工艺简单,沉积速率快,形成的薄膜具有良好的抗吸湿性,与集成工艺相兼容,成膜质量好,能够充分满足先进集成电路对低介电常数材料的电学性能、力学性能以及绝缘性能的要求。
Description
技术领域
本发明属于超大规模集成电路(ULSI)互连技术领域,具体为用于填充互连金属层之间的低介电常数绝缘薄膜的制备方法。
背景技术
随着器件尺寸不断减小到深亚微米,就要求采用多层互连结构,以使由于寄生电阻(R)和电容(C)而产生的延时最小化。由于RC延时的增加,在栅上获得的器件速度的增益被金属互连线之间的传播延时所抵消;参见刘鸣,刘玉玲,刘博等.“低k介质与铜互连集成工艺”.[J].《微纳电子技术》, 2006,10(6):464-469。为了减小ULSI电路中的RC常数,需要互连材料具有低电阻率和膜层间的低电容。众所周知, ,其中是介电常数,A为面积,d为电介质膜层厚度,介电长数等于k和ε0的乘积,ε0为真空的介电常数,k为相对介电常数。考虑低电容情况,通过增加介电层膜厚(引起间隙填充更困难)或减小导线厚度和面积(导致电阻增加)来降低寄生电容是更不容易的。所以,这就要求材料有更低的介电常数,由此产生对低介电常数材料的需求。
超大规模集成电路不断发展,要求采用介电常数更低的材料即k<2.6的介质薄膜,然而材料的介电常数主要与材料的总极化率以及材料的密度相关,目前获得超低介电常数材料主要是通过在介质基体中引入孔隙(介电常数约等于1)来实现的,这主要因为引入孔隙可以有效降低材料本身的密度。根据国内外的文献(如,Miller R.D. 米勒R.D.等In search of low-k dielectrics.低-k介电常数的研究[J]. 《Science科学》, 1999, 286(5439): 421-423)及中国专利(丁士进等,“一种多孔超低介电常数材料薄膜及其制备方法”,公开号CN 101789418 A)报道,多孔薄膜材料中的孔隙通常是在前驱体中添加模板剂,再通过热处理方法除去模板剂,从而获得多孔薄膜材料。此方法例如,Shen等人以正硅酸乙酯(TEOS)为硅源,十六烷基三甲基溴化铵(CTAB)为模板剂,在酸性条件下采用溶胶凝胶方法制备出多孔薄膜材料,孔径为4nm,介电常数为2.5(参考文献J. Shen, A. Luo, L. F. Yao, et al. Low dielectric constant silica films with ordered nanoporous structure [J]. Materials science and Engineering, 2007,27(5-8):1145-1148)。但是上述专利“一种多孔超低介电常数材料薄膜及其制备方法”中提到的低介电常数薄膜的制备方法为旋涂(spin-coating)成膜,旋涂方法制备的薄膜多存在成膜质量较差,厚度不均一等问题,因此现代大规模集成电路工艺已经基本不采用旋涂方法制备薄膜,而是采用本发明提到的等离子体增强化学气相沉积(plasma enhanced chemical vapor deposition,PECVD)方法。相比较旋涂方法,利用PECVD技术制备低介电常数薄膜具有均匀性和重复性好,可大面积成膜,台阶覆盖优良。另外,薄膜成分和厚度易于控制,且使用范围广,设备简易,易于产业化,效率高且成本低。
自从2001年Grill等人首次报道PECVD技术制备出了低介电常数多孔薄膜材料以来,国际上陆续出现了相关的文献报道,如表1所示:
表1. PECVD方法制备低介电常数多孔薄膜材料
参考文献5: R. Navamathavan, C. K. Choi. Plasma enhanced chemical vapor deposition of low dielectric constant SiOC(-H) films using MTES/O2 precursor [J], Thin Solid Films, 2007, 515(12): 5040-5044.
参考文献6:Grill Alfred. Plasma enhanced chemical vapor deposited SiCOH dielectrics: from low-k to extreme low-k interconnect materials [J], Journal of Applied Physics, 2003, 93(3): 1785-1790.
参考文献7:S.-K. Kwak, K.-H. Jeong, S.-W. Rhee et al., Nanocomposite Low-k SiCOH Films by Direct PECVD Using Vinyltrimethylsilane [J]. Journal of the Electrochemical Society, 2004, 151(2): F11-F16.
如表1中所示,文献5和7中报道分别采用MTES+O2和VTMS+O2为前驱体,不同温度下利用PECVD技术沉积薄膜,最终的退火温度分别为500℃和450℃,然而如此高的退火温度条件不能满足通常的集成电路后道工艺对低介电常数材料的热稳定性要求(≤420℃)。文献6采用热处理方法去除成孔剂得到介电常数为2.05的薄膜材料,但是力学性能不理想,很难满足工艺界对薄膜材料的要求。本发明利用具有新颖性的MTES和LIMO的混合前驱体,创新性地采用交替PECVD绝缘薄膜和后等离子体处理的方法,即将绝缘层沉积步骤和致密层形成步骤交替进行,形成的薄膜具有抗吸湿性强,力学性能好,薄膜退火温度低,与集成工艺相兼容等优点。
发明内容
本发明的目的是提供一种超低介电常数绝缘薄膜的制备方法,通过该方法制备的绝缘薄膜具有理想的电学性能和力学性能,可用于极大规模集成电路互连技术领域。
为了达到上述目的,本发明提供了一种超低介电常数绝缘薄膜的制备方法,该方法包含如下具体步骤:
步骤1,利用等离子体增强化学气相沉积技术沉积薄膜:以甲基三乙氧基硅烷和柠檬烯为反应源,且甲基三乙氧基硅烷和柠檬烯均以氦气为载气被导入到化学气相沉积反应腔中,沉积形成50-100nm的绝缘层,其中,甲基三乙氧基硅烷与柠檬烯的流量比=1:1~1:2.5,该流量以克/分钟计;
步骤2,在上述腔体中采用Ar或He等离子体对绝缘层表面进行原位处理1-5分钟,形成致密的修饰层,此修饰层的作用是阻止水分子在整个绝缘层中由上而下的扩散,从而降低了上述绝缘层中孔隙对水的吸附,遏制了吸水导致介电常数的上升;
步骤3,重复上述步骤1和2,直到达到绝缘薄膜的目标厚度,得到绝缘薄膜;
步骤4,在惰性气氛中,对步骤3得到的绝缘薄膜进行高温退火,去除其中的碳氢基团(该碳氢基团包括前躯体中的碳氢基团以及柠檬烯中的碳氢基团),从而形成一种具有多孔结构的超低介电常数绝缘薄膜。
上述的方法,其中,步骤1中的沉积工艺所使用的射频频率为13.56MHz,反应腔体中初始真空为0.018-0.02托,沉积绝缘层时的衬底温度为100-400℃,功率为200-600瓦,工作压强为2-5托(1托 = 133.322Pa),导入反应腔中MTES流量为1.0-2.0克/分钟, LIMO流量为1.0-3.5克/分钟,He载气流量为500 - 5000sccm。
上述的方法,其中,在步骤2中,Ar或He等离子体表面处理时功率为300-600瓦,处理时间为1-5分钟,气压为2-8托。
上述的方法,其中,在步骤4中,退火温度为200-420℃,退火炉中的压强为0.2-0.3托,退火时间为2-6小时,退火气氛为氩气或者氮气。优选地,上述的退火工艺中,5-30分钟内由室温上升到所述退火温度。
上述的方法,其中,所述甲基三乙氧基硅烷和柠檬烯在导入反应腔体之前的汽化温度分别为50 - 60℃和60 -100℃。
本发明还提供了一种采用上述的方法制备的超低介电常数绝缘薄膜,其中,该绝缘薄膜包含:若干层绝缘层;该每层绝缘层上均设置有修饰层,在绝缘层内部具有若干孔隙;该超低介电常数绝缘薄膜介电常数为2.2-2.4,在1MV/cm时的漏电流密度为10-9-10-8A/cm2;杨氏模量为4.2-17GPa,硬度为0.5-1.3GPa。
本发明提供的超低介电常数绝缘薄膜的制备方法是分别以MTES和LIMO为反应源,在He载气的携带下导入反应腔体,采用等离子体增强化学气相沉积技术沉积形成绝缘层,然后采用氩气(Ar)或氦气(He)等离子对前述绝缘层表面进行原位处理,形成致密的修饰层,重复上述过程直至达到要求厚度的薄膜,最后将该薄膜置于高温下退火,以去除碳氢基团,从而形成超低介电常数多孔绝缘薄膜。
本发明所提供的薄膜采用具有新颖性的反应源MTES和LIMO,简单易得,使用安全,副产物对环境无污染,制备的薄膜介电常数处于2.2-2.4范围内,在满足超低介电常数的同时还具有较优异的力学特性。另外,薄膜还拥有优良的绝缘性能,在1MV/cm的外电场下,漏电流密度可以达到10-9-10-8A/cm2。因此,本发明所制备的超低介电常数绝缘薄膜能够充分满足先进集成电路对低介电常数材料的电学性能、力学性能以及绝缘性能的要求。
除此以外,本发明提供的薄膜制备方法创新性地采用交替等离子体增强化学气相沉积,形成的薄膜具有良好的抗吸湿性,力学性能较好,与集成工艺相兼容,不仅工艺简单,沉积速率快,而且成膜质量好。
附图说明
图1a-1d为本发明的超低介电常数绝缘薄膜的制备过程示意图。
具体实施方式
下面结合附图与具体实施方式对本发明作进一步详细说明。在图中,为了方便说明,放大或缩小了不同层和区域的尺寸,所示大小并不代表实际尺寸,也不反映尺寸的比例关系。
本发明采用等离子体增强化学气相沉积技术来制备超低介电常数绝缘薄膜,以氦气(He)为载气,分别将前驱体甲基三乙氧基硅烷(C7H18O3 Si,简称MTES)和成孔剂柠檬烯(C10H16,简称LIMO)带入等离子体增强化学气相沉积反应腔体中沉积形成绝缘层,等离子体增强化学气相沉积工艺所使用的射频频率为13.56MHz,反应腔体中初始真空为0.018~0.02托,衬底温度为100~400℃,沉积功率为200~ 600瓦,工作压强为2~5托,He载气流量为500~5000sccm(standard-state cubic centimeter per minute)。MTES和LIMO在导入反应腔体之前的汽化温度分别为50~60℃和60~100℃,MTES流量是1.0-2.0g克/分钟,LIMO流量是1.0-3.5克/分钟,比值为1:1-1:2.5,沉积厚度为50-100nm,形成如图1a所示的绝缘层10,该绝缘层10由Si-O-Si结构11和碳氢基团12构成。
在上述腔体中采用Ar或He等离子体对绝缘层表面进行原位处理以形成致密的修饰层20(如图1b所示),功率为300-600瓦,处理时间为1-5分钟,气压为2-8托。该修饰层20的作用是封住绝缘层10的外表面,防止绝缘层10内退火形成的孔隙吸水。
分别重复上述两个步骤从而达到目标厚度的绝缘薄膜,如图1c所示,形成了3次绝缘层-修饰层交替设置的绝缘薄膜30。
将上述目标绝缘薄膜30置于退火炉中,Ar或者N2氛围下,退火炉压强为0.2-0.3托,5-30分钟内由室温上升到退火温度,200-420℃条件下退火2-6小时,去除碳氢基团,在绝缘薄膜的绝缘层内部形成若干不规则的孔隙13(该孔隙13包括若干蠕虫状孔及若干不规则圆孔),最终获得具有多孔结构的超低介电常数绝缘薄膜,如图1d所示。
薄膜性能测量:为了测量上述薄膜的电学性能,本发明以低阻硅片(电阻率为0.001-0.02Ω·cm)为衬底,以电子束蒸发的铝在薄膜上形成直径为400-420微米的圆形金属电极以构成电容器,从而得到金属-绝缘体-半导体(简称MIS)电容结构。在室温下上述电容器基于电容-电压特性来测定电容,并通过多点测试来获得可靠的平均电容值,同时考虑电极的面积和薄膜厚度来确定介电常数。此外,通过对电流-电压的测量获得薄膜的漏电特性。通过纳米压痕仪获得薄膜的硬度和杨氏模量。
实施例1-6中,通过改变甲基三乙氧基硅烷和柠檬烯的相对流量,制备出了7种不同的薄膜样品(即,编号为1-6的样品),表2列出了在不同流量比条件下制备出的样品的电学性能,力学性能和漏电流大小。随着相对流量逐渐增大,介电常数及其力学性能都表现出先减小后增大的趋势。由表2可以看出,所得薄膜的最低介电常数为2.2,折射率为1.309,力学性能方面,硬度为0.55GPa,杨氏模量为4.23GPa,达到文献报道的多孔低介电常数薄膜力学性能的普遍水平, 另外其他样品也表现出了优良的力学性能。同时漏电流密度也较小,表现出较好的绝缘性能。因此,可以满足下一代集成电路工艺对低介电常数薄膜材料的要求。
附表2.样品的沉积速率,电学性能,力学性能和漏电流大小
尽管本发明的内容已经通过上述优选实施例作了详细介绍,但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后,对于本发明的多种修改和替代都将是显而易见的。因此,本发明的保护范围应由所附的权利要求来限定。
Claims (7)
1.一种超低介电常数绝缘薄膜的制备方法,其特征在于,该方法包含如下具体步骤:
步骤1,利用等离子体增强化学气相沉积技术沉积薄膜:以甲基三乙氧基硅烷(MTES)和柠檬烯(LIMO)为反应源,且甲基三乙氧基硅烷和柠檬烯均以氦气为载气被导入到化学气相沉积反应腔中形成绝缘层,厚度为50-100nm,其中,甲基三乙氧基硅烷与柠檬烯的流量比为1:1~1:2.5,该流量以克/分钟计;
步骤2,在上述腔体中采用Ar或He等离子体对绝缘层表面进行原位处理以形成致密的修饰层,等离子体处理时间为1-5分钟;
步骤3,重复上述步骤1和2,直到达到绝缘薄膜的目标厚度,得到绝缘薄膜;
步骤4,在惰性气氛中,对步骤3得到的绝缘薄膜进行高温退火,去除其中的碳氢基团,从而形成一种具有多孔结构的超低介电常数绝缘薄膜。
2.如权利要求1所述的方法,其特征在于,步骤1中的沉积工艺所使用的射频频率为13.56MHz,反应腔体中初始真空为0.018-0.02托,沉积绝缘层时的衬底温度为100-400℃,功率为200-600瓦,工作压强为2-5托,导入反应腔中MTES流量为1.0-2.0克/分钟, LIMO流量为1.0-3.5克/分钟,He载气流量为500 - 5000sccm。
3.如权利要求1所述的方法,其特征在于,在步骤2中,Ar或He等离子体表面处理时功率为300-600瓦,处理时间为1-5分钟,气压为2-8托。
4.如权利要求1所述的方法,其特征在于,在步骤4中,退火工艺为:退火温度为200-420℃,退火炉中的压强为0.2-0.3托,退火时间为2-6小时,退火气氛为氩气或者氮气。
5.如权利要求4所述的方法,其特征在于,上述的退火工艺中,5-30分钟内由室温上升到所述退火温度。
6.如权利要求1所述的方法,其特征在于,所述甲基三乙氧基硅烷和柠檬烯在导入反应腔体之前的汽化温度分别为50 - 60℃和60 -100℃。
7.一种采用权利要求1所述的方法制备的超低介电常数绝缘薄膜,其特征在于,该绝缘薄膜包含:若干层绝缘层(10);该每层绝缘层(10)上均设置有修饰层(20),在绝缘层(10)内部具有若干孔隙(13);该超低介电常数绝缘薄膜介电常数为2.2-2.4,在1MV/cm时的漏电流密度为10-9-10-8A/cm2;杨氏模量为4.2-17GPa,硬度为0.5-1.3GPa。
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