CN103985757A - Surrounding-gate-type nanowire transistor - Google Patents
Surrounding-gate-type nanowire transistor Download PDFInfo
- Publication number
- CN103985757A CN103985757A CN201410145600.7A CN201410145600A CN103985757A CN 103985757 A CN103985757 A CN 103985757A CN 201410145600 A CN201410145600 A CN 201410145600A CN 103985757 A CN103985757 A CN 103985757A
- Authority
- CN
- China
- Prior art keywords
- grid
- mid portion
- germanium
- encloses
- type nano
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002070 nanowire Substances 0.000 title claims abstract description 36
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 21
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 9
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 239000003795 chemical substances by application Substances 0.000 description 13
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 101100207343 Antirrhinum majus 1e20 gene Proteins 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/122—Single quantum well structures
- H01L29/125—Quantum wire structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
Abstract
The invention discloses a surrounding-gate-type nanowire transistor. The transistor comprises a cylindrical main body structure, wherein the main body structure comprises a middle portion and two end portions located on the two sides of the middle portion, the middle portion is wrapped with grid electrodes in a surrounding mode and accordingly a surrounding gate is formed, the two end portions serve as a source electrode and a drain electrode respectively, the main body structure is mainly made of silicon and germanium, and the concentration of germanium in the middle portion is larger than the concentration of germanium on the two end portions. Due to the heterojunction structure of the source electrode, the drain electrode and channels, the valence band of the middle channel portion moves upwards, and accordingly the transmitting speed and the mobility ratio of a hole can be improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to one and enclose grid type nano-wire transistor.
Background technology
Under the guidance of Moore's Law, the size of integrated circuit semiconductor apparatus is more and more less, but can not infinitely dwindle.Narrowing down to a certain degree and will reach its physics limit, serious short-channel effect and gate leakage current will there will be.This will be a challenge to the validity of Moore's Law.But people are actively finding and are alternatively putting forward high performance method with shortening device size, so industry has been put into the focus of technical exploration use high-k material and has explored in new device structure particularly the latter.Novel device architecture is by the direction and the trend that are following semiconductor device research and development.Silicon nano line transistor is a kind of new device structure, and it is one of most promising competitor under integrated circuit development course Figure 22 nm technology node.The silicon nanowire structure transistor of Preliminary report has excellent Sub-Threshold Characteristic, carrier mobility and closes step response both at home and abroad at present, can be good at suppressing short-channel effect.Than traditional body silicon planar device, the nanowire MOS FET of One Dimensional Quasi ballistic transport shows very strong minification advantage, and nano-wire transistor will show great potentiality to the set objective that realizes semiconductor route map.Because expand the area of grid encirclement raceway groove, thereby improve the ability of controlling raceway groove transoid electronics, reduce the short-channel effect of MOS device, avoided reducing of the required gate oxide thickness doing in reduction of device size simultaneously, thereby also reduced the leakage current of grid.
When MOSFET characteristic size enters after nanoscale, carrier mobility be lowered into one of the principal element for restriction device performance.Road stress application, or adopt different substrate crystal orientation, can, in the situation that not changing device geometries, strengthen significantly the performance of MOSFET.
For short ditch encloses grid type nano-wire transistor, according to the report of document " A Unified Carrier-Transport Model for the Nanoscale Surrounding-Gate MOSFET Comprising Quantum – Mechanical Effects ", its electron mobility is 120cm
2/ Vs, still far below the 1300cm of general long ditch planar MOSFET
2the electron mobility of/Vs.Under same condition, the mobility of electronics approaches 3 times of hole mobility, is respectively 40cm therefore short ditch encloses the hole mobility of grid type nano-wire transistor and general long ditch planar MOSFET
2/ Vs and 433cm
2/ Vs, the former is the latter's 1/10.Therefore this type of encloses the too small problem of grid type nano-wire transistor mobility urgently to be resolved hurrily.
Summary of the invention
The object of the invention is to, provide one to enclose grid type nano-wire transistor, to solve the too small problem of grid type nano-wire transistor mobility of enclosing.
For solving the problems of the technologies described above, the invention provides one and enclose grid type nano-wire transistor, comprising: a columned agent structure, described agent structure comprises mid portion and is positioned at two ends of mid portion both sides, be enclosed with grid around mid portion, form and enclose grid; Two ends are as source electrode and drain electrode; Wherein, the material of described agent structure comprises SiGe, and the concentration of described mid portion germanium is greater than the concentration of the germanium of described two ends.
Optionally, for the described grid type nano-wire transistor that encloses, in the SiGe of described mid portion, the concentration of germanium is 70mol%, and in the SiGe of described two ends, the concentration of germanium is 30mol%.
Optionally, for the described grid type nano-wire transistor that encloses, described mid portion is N-type doping or undopes, and described two ends are the doping of P type.
Optionally, for the described grid type nano-wire transistor that encloses, described P type is doped to and adopts BF
2adulterate, doping content is 8e19/cm
3～2e21/cm
3.
Optionally, for the described grid type nano-wire transistor that encloses, the radius of described agent structure is 10nm～50nm, and the length of mid portion is 100nm～1000nm.
Optionally, for the described grid type nano-wire transistor that encloses, the thickness of described grid is 50nm～150nm.
Optionally, for the described grid type nano-wire transistor that encloses, between described mid portion and grid, be formed with tunnel oxide, the material of described tunnel oxide is SiO
2, thickness is 5nm-20nm.
Compared with prior art, provided by the invention enclosing in grid type nano-wire transistor, improves columned agent structure, make the material of described agent structure comprise SiGe, and the concentration of described mid portion germanium is greater than the concentration of the germanium of described two ends.Compared to existing technology, be the content as germanium in the SiGe of channel part lower than centre as the content of germanium in the SiGe of two ends of source-drain electrode.Such source leak with the structure of the heterojunction of raceway groove brought intermediate channel part valence band on move, in valence band, move and can make the emission rate in hole and mobility get a promotion, and due to the employing of this SiGe of the present invention, produce transverse compressive stress, further strengthened the mobility in hole.
Brief description of the drawings
Fig. 1 is the structural representation that encloses grid type nano-wire transistor of the embodiment of the present invention;
Fig. 2 is the energy band diagram that encloses grid type nano-wire transistor of the embodiment of the present invention.
Embodiment
Below in conjunction with schematic diagram, the grid type nano-wire transistor that encloses of the present invention is described in more detail, the preferred embodiments of the present invention are wherein represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to about system or about the restriction of business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with way of example, the present invention is more specifically described with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, provides one to enclose grid type nano-wire transistor, comprising: a columned agent structure, and described agent structure comprises mid portion and is positioned at two ends of mid portion both sides, is enclosed with grid around mid portion, forms and encloses grid; Two ends are as source electrode and drain electrode; Wherein, the material of described agent structure comprises SiGe, and the concentration of described mid portion germanium is greater than the concentration of the germanium of described two ends.
Described in below enumerating, enclose the preferred embodiment of grid type nano-wire transistor, to clearly demonstrate content of the present invention, will be clear that, content of the present invention is not restricted to following examples, and other improvement by those of ordinary skill in the art's routine techniques means are also within thought range of the present invention.
Based on above-mentioned thought, the preferred embodiment that encloses grid type nano-wire transistor is provided below, please refer to Fig. 1, the structural representation of what Fig. 1 was the embodiment of the present invention enclose grid type nano-wire transistor.
As shown in Figure 1, comprise: a columned agent structure, described agent structure comprises mid portion 11 and is positioned at two ends 12 of mid portion 11 both sides, the material of described agent structure comprises SiGe (SiGe), the concentration of described mid portion 11 germanium (Ge) is greater than the concentration of the germanium of described two ends 12, preferably, and in embodiments of the present invention, in the SiGe of described mid portion 11, the concentration of germanium is 70mol%, and in the SiGe of described two ends 12, the concentration of germanium is 30mol%.Because the lattice constant of Ge is larger than Si, the use of SiGe has increased the mobility of charge carrier, produces horizontal compression simultaneously and has further strengthened hole mobility.Described mid portion 11 adulterates or undopes for N-type, and described two ends 12 are the doping of P type.Described P type is doped to and adopts BF
2adulterate, doping content is 8e19/cm
3～2e21/cm
3, concrete, can be for example 1e20/cm
3.
The cause entirely exhausting is enclosed with grid 2 around mid portion 11, forms and enclose grid, grid-control ability is strengthened, because can make carrier density increase; Two ends 12 are as source electrode and drain electrode; Wherein, the radius of described agent structure is 10nm～50nm, for example, in a preferred embodiment, radius can be 13cm, 15cm, 20cm etc., and the length of mid portion 11 is 100nm～1000nm, be that channel length is 100nm～1000nm, for example, in one embodiment, the length of mid portion 11 can be 350nm.
Between described grid 2 and mid portion 11, also comprise and be formed with tunnel oxide (not shown), the material of described tunnel oxide is SiO
2, thickness is 5nm-20nm, for example, can be 8nm.The thickness of described grid 2 is 50nm～150nm, for example, be 60nm, 75nm, 80nm etc.
The energy band diagram that encloses grid type nano-wire transistor of the present invention shows as Fig. 2, and the content that leaks Ge in the SiGe of part due to its source is 30mol%, and in intermediate channel part SiGe, the content of Ge is 70mol%.Such source leak with the structure of the heterojunction of raceway groove brought intermediate channel part top of valence band Ev on move, in valence band, move and make can be with poor (band-offset) change greatly, can make the emission rate in hole and mobility get a promotion.
In addition, deduce through emulation, with the heterogeneous SiGe nano wire pMOSFET of 13nm diameter and plane homogeneity SiGe channel device, (comparison of width 1 μ electrology characteristic m), such as electric current, the former increases by 4.5 times than the latter, and mutual conductance g
mwith gate voltage V
gthe comparison of relation, all demonstrating the former in saturation region and linear zone also all increases by 4.5 times than the latter.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (7)
1. enclose a grid type nano-wire transistor, comprising: a columned agent structure, described agent structure comprises mid portion and is positioned at two ends of mid portion both sides, is enclosed with grid around mid portion, forms and encloses grid; Two ends are as source electrode and drain electrode; Wherein, the material of described agent structure comprises SiGe, and the concentration of described mid portion germanium is greater than the concentration of the germanium of described two ends.
2. the grid type nano-wire transistor that encloses as claimed in claim 1, is characterized in that, in the SiGe of described mid portion, the concentration of germanium is 70mol%, and in the SiGe of described two ends, the concentration of germanium is 30mol%.
3. the grid type nano-wire transistor that encloses as claimed in claim 2, is characterized in that, described mid portion is that N-type is adulterated or undopes, and described two ends are the doping of P type.
4. the grid type nano-wire transistor that encloses as claimed in claim 3, is characterized in that, described P type is doped to and adopts BF
2adulterate, doping content is 8e19/cm
3～2e21/cm
3.
5. the grid type nano-wire transistor that encloses as claimed in claim 1, is characterized in that, the radius of described agent structure is 10nm～50nm, and the length of mid portion is 100nm～1000nm.
6. the grid type nano-wire transistor that encloses as claimed in claim 5, is characterized in that, the thickness of described grid is 50nm～150nm.
7. the grid type nano-wire transistor that encloses as claimed in claim 5, is characterized in that, between described mid portion and grid, be formed with tunnel oxide, the material of described tunnel oxide is SiO
2, thickness is 5nm-20nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410145600.7A CN103985757B (en) | 2014-04-08 | 2014-04-08 | Surrounding-gate-type nanowire transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410145600.7A CN103985757B (en) | 2014-04-08 | 2014-04-08 | Surrounding-gate-type nanowire transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103985757A true CN103985757A (en) | 2014-08-13 |
| CN103985757B CN103985757B (en) | 2017-05-10 |
Family
ID=51277659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410145600.7A Active CN103985757B (en) | 2014-04-08 | 2014-04-08 | Surrounding-gate-type nanowire transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103985757B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105489654A (en) * | 2015-12-01 | 2016-04-13 | 商丘师范学院 | Nanowire transistor and manufacturing method thereof |
| CN108807660A (en) * | 2017-05-02 | 2018-11-13 | 上海磁宇信息科技有限公司 | Use the ultra high density random access memory framework of vertical-type circulating type field-effect transistor |
| CN110233176A (en) * | 2018-03-05 | 2019-09-13 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1988177A (en) * | 2005-12-24 | 2007-06-27 | 三星电子株式会社 | Fin-fet having gaa structure and methods of fabricating the same |
| WO2009011450A1 (en) * | 2007-07-17 | 2009-01-22 | Sharp Kabushiki Kaisha | Core-shell-shell nanowire transistor and fabrication method thereof |
| CN101986423A (en) * | 2009-07-28 | 2011-03-16 | 台湾积体电路制造股份有限公司 | Method for forming high germanium concentration sige stressor and integrated circuit transistor structure |
| US20110062417A1 (en) * | 2009-09-16 | 2011-03-17 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| CN102148250A (en) * | 2011-01-07 | 2011-08-10 | 清华大学 | High-speed low-noise semiconductor device structure and method for forming same |
| US20110291190A1 (en) * | 2009-09-28 | 2011-12-01 | Semiconductor Manufacturing International (Shanghai) Corporation | System and method for integrated circuits with cylindrical gate structures |
-
2014
- 2014-04-08 CN CN201410145600.7A patent/CN103985757B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1988177A (en) * | 2005-12-24 | 2007-06-27 | 三星电子株式会社 | Fin-fet having gaa structure and methods of fabricating the same |
| WO2009011450A1 (en) * | 2007-07-17 | 2009-01-22 | Sharp Kabushiki Kaisha | Core-shell-shell nanowire transistor and fabrication method thereof |
| CN101986423A (en) * | 2009-07-28 | 2011-03-16 | 台湾积体电路制造股份有限公司 | Method for forming high germanium concentration sige stressor and integrated circuit transistor structure |
| US20110062417A1 (en) * | 2009-09-16 | 2011-03-17 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| US20110291190A1 (en) * | 2009-09-28 | 2011-12-01 | Semiconductor Manufacturing International (Shanghai) Corporation | System and method for integrated circuits with cylindrical gate structures |
| CN102148250A (en) * | 2011-01-07 | 2011-08-10 | 清华大学 | High-speed low-noise semiconductor device structure and method for forming same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105489654A (en) * | 2015-12-01 | 2016-04-13 | 商丘师范学院 | Nanowire transistor and manufacturing method thereof |
| CN108807660A (en) * | 2017-05-02 | 2018-11-13 | 上海磁宇信息科技有限公司 | Use the ultra high density random access memory framework of vertical-type circulating type field-effect transistor |
| CN110233176A (en) * | 2018-03-05 | 2019-09-13 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN110233176B (en) * | 2018-03-05 | 2022-07-22 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103985757B (en) | 2017-05-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Sahay et al. | Nanotube junctionless FET: proposal, design, and investigation | |
| Asthana et al. | High-speed and low-power ultradeep-submicrometer III-V heterojunctionless tunnel field-effect transistor | |
| Lu et al. | Geometry dependent tunnel FET performance-dilemma of electrostatics vs. quantum confinement | |
| Kumar et al. | Physics based analytical model for surface potential and subthreshold current of cylindrical Schottky Barrier gate all around MOSFET with high-k gate stack | |
| Nigam et al. | A new approach for design and investigation of junction-less tunnel FET using electrically doped mechanism | |
| Narula et al. | Enhanced performance of double gate junctionless field effect transistor by employing rectangular core–shell architecture | |
| Lahgere et al. | A tunnel dielectric-based junctionless transistor with reduced parasitic BJT action | |
| CN102544073A (en) | Knot-free nanowire field effect transistor | |
| CN103985757B (en) | Surrounding-gate-type nanowire transistor | |
| Kumar et al. | Parametric investigation and design of junctionless nanowire tunnel field effect transistor | |
| CN104241334A (en) | Junctionless transistor | |
| Soree et al. | Silicon nanowire pinch-off FET: basic operation and analytical model | |
| CN103247688B (en) | A kind of graphene field effect pipe of bi-material layers grid linear doping | |
| Chowdhury et al. | Silvaco TCAD based analysis of cylindrical Gate-All-Around FET having Indium Arsenide as channel and Aluminium Oxide as gate dielectrics | |
| Aslam et al. | Enhancement of the DC performance of a PNPN hetero-dielectric BOX tunnel field-effect transistor for low-power applications | |
| KR102158187B1 (en) | Hetero tunnel field effect transistor based on nanowire | |
| Singh et al. | Design and simulation analysis of silicon germanium nanowire FET for low power applications | |
| Dharavath et al. | A Two Dimensional Analytical Model of Heterostructure Double Gate with Pocket Doped Tunnel FET | |
| Tripathi et al. | High Performance Low Leakage Pocket Si x Ge 1-x Junction-Less Single-Gate Tunnel FET for 10 nm Technology | |
| CN105489654A (en) | Nanowire transistor and manufacturing method thereof | |
| CN104241138A (en) | Nanowire transistor | |
| CN104241371A (en) | Nanowire transistor | |
| Zhao et al. | Tunneling Leakage Current of Gate-All-Around Nanowire Junctionless Transistor with an Auxiliary Gate | |
| Singh et al. | Performance and comparative analysis of heterojunction structure based GAA-NWTFET for low power applications | |
| CN104269435B (en) | A kind of nodeless mesh body pipe |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |