CN103972207A - 堆叠管芯之间的螺旋形螺旋电感器 - Google Patents

堆叠管芯之间的螺旋形螺旋电感器 Download PDF

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Publication number
CN103972207A
CN103972207A CN201310162963.7A CN201310162963A CN103972207A CN 103972207 A CN103972207 A CN 103972207A CN 201310162963 A CN201310162963 A CN 201310162963A CN 103972207 A CN103972207 A CN 103972207A
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Prior art keywords
tube core
induction structure
induction
layer
integrated inductor
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CN201310162963.7A
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English (en)
Inventor
颜孝璁
罗正玮
郭晋玮
郑敏祺
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to CN201910520681.7A priority Critical patent/CN110335857A/zh
Publication of CN103972207A publication Critical patent/CN103972207A/zh
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Abstract

本发明涉及了一种提供了良好电感和Q因数的多层集成电感器。在一些实施例中，该集成电感器具有第一电感结构和第二电感结构，第一电感结构带有设置在第一集成芯片(IC)管芯上的第一螺旋图案中的第一金属层，第二电感结构带有设置在第二IC管芯上的第二螺旋图案中的第二金属层。第一IC管芯垂直堆叠在第二IC管芯之上。在第一和第二IC管芯之间垂直设置有导电的互连结构且被配置成电连接第一金属层和第二金属层。导电的互连结构在第一和第二电感结构之间提供了相对较大的距离，从而在大频率范围上提供了具有高Q因数的电感。本发明还提供了一种堆叠管芯之间的螺旋形螺旋电感器。

Description

堆叠管芯之间的螺旋形螺旋电感器
技术领域
本发明涉及半导体领域，更具体地，本发明涉及一种堆叠管芯之间的螺旋形螺旋电感器。
背景技术
电感器是配置为生成存储能量的磁场的无源电气部件。电感器用于包括电压调节器和多种RF电路的多种多样的集成电路应用。通常使用现有的集成芯片制造工艺将具有相对较小的值的电感器直接构造在集成电路上。
电感器设计者通常会关注集成电感器的电感和品质因数(Q因数)。集成电感器的电感是存储在电感器中的能量大小的标准。Q因数是存储在电感器中的能量大小与电感器中消耗的能量大小的比值(例如，理想电感器具有高Q因数)。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种多层集成电感器，包括：第一电感结构，包括设置在第一集成芯片(IC)管芯上的第一导电层；第二电感结构，包括设置在第二IC管芯上的第二导电层，所述第二IC管芯垂直堆叠在所述第一IC管芯上；以及导电互连结构，垂直设置在所述第一IC管芯和所述第二IC管芯之间且被配置成电连接所述第一导电层和所述第二导电层。
在所述多层集成电感器中，所述导电互连结构包括一个或多个微凸块或铜柱。
在所述多层集成电感器中，所述导电互连结构包括铁酸盐化合物。
在所述多层集成电感器中，进一步包括：底部填充层，设置在所述第一导电层和所述第二导电层之间且被配置成围绕所述导电互连结构。
在所述多层集成电感器中，所述第一电感结构包括绕着第一轴线卷绕第一多匝的螺旋图案，所述第一轴线垂直于所述第一IC管芯；并且所述第二电感结构包括绕着第二轴线卷绕第二多匝的螺旋图案，所述第二轴线垂直于所述第二IC管芯。
在所述多层集成电感器中，所述第一轴线和所述第二轴线以非零偏移量相分离。
在所述多层集成电感器中，进一步包括：第三电感结构，包括垂直堆叠在所述第二IC管芯上的第三IC管芯上的第三导电层；以及第二导电互连结构，垂直位于所述第二IC管芯和所述第三IC管芯之间且被配置成电连接所述第二导电层和所述第三导电层。
在所述多层集成电感器中，所述第一电感结构包括第一蜿蜒图案，所述第一蜿蜒图案沿着其长度在第一方向上卷绕、随后在与所述第一方向相反的第二方向上卷绕；并且所述第二电感结构包括第二蜿蜒图案，所述第二蜿蜒图案沿着其长度在第一方向上卷绕、随后在与所述第一方向相反的第二方向上卷绕。
在所述多层集成电感器中，所述第一导电层被设置为第一图案，所述第二导电层被设置为第二图案；并且其中，所述第一图案是所述第二图案的镜像。
在所述多层集成电感器中，所述导电互连结构在所述第一电感结构和所述第二电感结构之间提供了范围在大约20um至大约40um之间的距离。
在所述多层集成电感器中，所述第一电感结构包括形成在所述第一IC管芯上的第一铝再分配层；并且所述第二电感结构包括形成在所述第二IC管芯上的第二铝再分配层。
根据本发明的另一方面，提供了一种多层集成电感器，包括：第一电感结构，包括在第一集成芯片(IC)管芯的第一面上设置为第一螺旋图案的第一金属层；第二电感结构，包括在第二IC管芯的第一面上设置为第二螺旋图案的第二金属层，所述第二IC管芯的第一面面向第一IC管芯的第一面；以及导电互连结构，垂直设置在所述第一IC管芯和所述第二IC管芯之间且被配置成电连接所述第一金属层和所述第二金属层。
在所述多层集成电感器中，所述导电互连结构包括一个或多个微凸块或铜柱。
在所述多层集成电感器中，进一步包括：底部填充层，设置在所述第一金属层和所述第二金属层之间且被配置成围绕所述导电互连结构。
在所述多层集成电感器中，所述导电互连结构包括铁酸盐化合物。
在所述多层集成电感器中，所述导电互连结构在所述第一电感结构和所述第二电感结构之间提供了范围在大约20um至大约40um之间的距离。
根据本发明的又一方面，提供了一种形成多层集成电感器的方法，包括：在第一集成芯片(IC)管芯的第一面上形成第一电感结构；在第二IC管芯的第一面上形成第二电感结构；以及通过将所述第一电感结构和所述第二电感结构电连接的导电互连结构将所述第一IC管芯的第一面与所述第二IC管芯的第一面相连接。
在所述方法中，所述第一电感结构包括绕着第一轴线卷绕第一多匝的螺旋图案，所述第一轴线垂直于所述第一IC管芯；并且所述第二电感结构包括绕着第二轴线卷绕第二多匝的螺旋图案，所述第二轴线垂直于所述第二IC管芯。
在所述方法中，所述导电互连结构包括一个或多个微凸块或铜柱。
在所述方法中，所述导电互连结构包括铁酸盐化合物。
附图说明
图1示出了所公开的位于堆叠集成芯片(IC)管芯之间的多层集成电感器的一些实施例的截面图；
图2示出了所公开的位于堆叠IC管芯之间的多层集成电感器的一些其他实施例的截面图；
图3示出了所公开的位于堆叠IC管芯之间的螺旋电感器的一些实施例的三维视图；
图4A-图4B示出了所公开的位于邻接的可堆叠IC管芯上的电感结构的几何形状的一些实施例；
图5A-图5B示出了所公开的集成电感器的一些可选实施例；
图6A-图6B示出了包括多个串联连接的电感器的多层电感结构的一些实施例；
图7是在堆叠IC管芯之间形成多层集成电感器的方法的一些实施例的流程图。
具体实施方式
在这里参考附图来进行描述，其中，在整个说明书中类似的参考标号大体上被用来表示类似的元件，并且其中，各种结构没有按照比例绘制。在下面的说明书中，出于解释目的描述了大量具体细节以便于理解。然而，对本领域的技术人员而言较小程度地借助这些具体细节来实践在此所述的一个或更多方面是显而易见的。在其他例子中，以框图形式示出了已知的结构的器件以便于理解。
在后段工程(BEOL)金属化堆叠中，集成电感器通常形成在一个或更多金属层中。通常，将形成在不同金属层上的多个电感结构串联连接在一起，以增大整体电感。例如，多层集成电感器可以包括形成在第一金属层(例如，M1层)上的螺旋圈状图案中的第一电感结构，该第一金属层与形成在与第一金属层垂直分离的第二金属层(例如，M2层)上的螺旋圈状图案中的第二电感结构串联连接。螺旋圈状图案将由流经第一金属层和第二金属层的电流所引起的磁通量集中在一起，以将能量存储在多层电感器内。
然而，集成芯片(IC)部件的缩小尺寸将多层集成电感器的制造复杂化。例如，在发展的技术节点中，BEOL金属化堆叠中的金属层之间的垂直距离较小使得多层集成电感器的电感结构之间距离较小。距离较小使得集成电感器具有低共振频率和高寄生电容(例如，由于电容与电极间距成反比)。高寄生电容存储能量使得多层集成电感器的品质因数(Q因数)偏离总能量。另外，使用电感结构的较低金属层(具有较小宽度和较高电阻)导致产生了减小集成电感器的电感的较高电阻。
因此，本发明涉及了提供良好电感和品质因数的多层集成电感器及相关制造方法。在一些实施例中，集成电感器包括第一电感结构和第二电感结构，第一电感结构包括设置在第一集成芯片(IC)管芯上的第一金属层，第二电感结构包括设置在第二IC管芯上的第二金属层。第一IC管芯垂直堆叠在第二IC管芯上。导电互连结构垂直位于第一和第二IC管芯之间且被配置成电连接第一金属层和第二金属层。导电互连结构被配置成在第一和第二电感结构之间提供相对较大的距离，这在较大频率范围上提供了高Q因数。
图1示出了所公开的位于堆叠集成芯片(IC)管芯之间的多层集成电感器100的一些实施例的截面图。
多层集成电感器100包括堆叠在第一IC管芯102上的第二集成芯片(IC)管芯104。在一些实施例中，一个或更多第一和第二IC管芯102和104可以包括硅衬底(例如，具有多个集成芯片器件)。在其他实施例中，第一或更多第一和第二IC管芯102和104可以包括被配置提供结构稳定性，改善散热、改善互连等的中介层衬底(例如，玻璃或硅中介层衬底)。
第一IC管芯102包括第一电感结构110，该第一电感结构包括设置在第一衬底112的第一面上方的第一导电层。在一些实施例中，第一电感结构110被设置在介电层108之上，该介电层包括一种或更多种位于半导体衬底100上方的介电材料(例如，氧化物)。在一些实施例中，第一导电层包括设置在一个或更多介电层内部的金属互连层(例如，铜金属互连层)，该介电层设置在第一衬底112的第一面之上。在其他实施例中，第一导电层可以包括形成在BEOL金属化堆叠之上的再分配层(例如，铝再分配层)或背面金属。在一些实施例中，第一电感结构110可以包括具有导电材料第一螺旋电感器，该导电材料形成了绕着固定中心点卷绕n匝的曲线的螺旋图案。在其他实施例中，第一电感结构110可以包括形成非螺旋图案的导电材料。
第二IC管芯104包括第二电感结构118，该第二电感结构包括设置在第二衬底120的第一面上方的第二导电层。在一些实施例中，第二电感结构118设置在介电层116之上，该介电层包括一种或更多种位于半导体衬底114之上的介电材料。在一些实施例中，第二导电层包括设置在一个或更多介电层内的金属互连层，该介电层被设置在第二衬底120的第一面上。在其他实施例中，第二导电层可以包括形成在BEOL金属化堆叠之上的再分配层或背面金属。在一些实施例中，第二电感结构118可以包括具有导电材料的第二螺旋电感器，该导电材料形成了绕着固定中心点卷绕n匝的曲线的螺旋图案。在其他实施例中，第二导电结构118可以包括形成非螺旋图案的导电材料。
导电互连结构122垂直位于第一IC管芯102和第二IC管芯104之间。导电互连结构122被配置成电连接第一电感结构110和第二电感结构118。在一些实施例中，导电互连结构122包括一个或更多微凸块(例如，钨微凸块)或铜柱。
在一些实施例中，导电互连结构122包括多个微凸块或铜柱，它们被包括在设置在第一IC管芯102和第二IC管芯104之间的底部填充层124内。底部填充层124被配置成防止第一IC管芯102和第二IC管芯104之间的热失配。在多个实施例中，底部填充层124可以包括可塑的底部填充，该底部填充包括例如，合成树脂或环氧树脂。底部填充层124还可以在第一IC管芯102和第二IC管芯104之间提供额外的粘合且保护导电互连结构122不受到腐蚀性污染(例如，湿气)的侵害。
通过连接第一和第二电感结构110和118，通过导电互连结构122可以在第一和第二电感结构110和118之间实现较大距离。第一和第二电感结构110和118之间的大的距离减小了寄生电容，由此改善了多层集成电感器100的Q因数。另外，第一和第二电感结构110和118可以由具有大厚度的金属层形成。金属层的较大厚度减小了电感结构110和118的电阻，从而改善了多层集成电感器100的电感。
应该理解，所公开的多层集成电感器结构可以实施在2.5维集成芯片(2.5D IC)或3维集成芯片(3D IC)之间。例如，图2示出了包括位于2.5DIC和3DIC结构中的堆叠的IC之间的多层集成电感器的半导体模块200的一些额外的实施例的截面图。
半导体模块200包括通过一个或更多焊球204与第一层间衬底206相连接的封装件衬底202(例如，印刷电路板、有机板等)。第一层间衬底206包括一个或更多硅通孔(TSV)208，这些硅通孔提供了穿过第一层间衬底206延伸的垂直的电连接。在一些实施例中，一个或更多焊球204可以包括倒装芯片C4焊料凸块。
在一些实施例中，半导体模块200可以包括形成在2.5D IC结构210内的多层集成电感器。在这种实施例中，一个或更多TSV208与第一再分配层212相连接，包括设置在第一层间衬底206之上的第一电感结构。第一再分配层212被配置成在一个或更多TSV208和一个或更多微凸块214(例如，位于底部填充层218内)之间提供电连接。在一些实施例中，第一再分配层212可以包括铝再分配层(ALRDL)。在一些实施例中，第一再分配层212可以包括再分配层(RDL)和一个或更多金属间层的组合。一个或更多微凸块214连接第一再分配层212和第二再分配层216，包括设置在上面的IC管芯222之上的第二电感结构。在一些实施例中，第二再分配层216与一个或更多金属互连层相连接，该金属互连层形成在一个或更多设置在上面的IC管芯222上的介电层220之内。
与倒装芯片C4焊球相比，一个或更多微凸块214提供了更小的凸块尺寸(例如，10um-70um)和更近的间距(例如，10um-80um)。更小的凸块尺寸在第一再分配层212上的第一电感结构和第二再分配层216的第二电感结构之间提供了大约10um-70um的垂直距离。
在一些可选的实施例中，半导体模块200可以包括形成在3DIC结构224内部的多层集成电感器。在这种实施例中，一个或更多TSV208与第一再分配层226相连接，包括设置在第一层间衬底206上面的第一电感结构。第一再分配层226被配置成在一个或更多TSV208和一个或更多微凸块228(例如，位于底部填充层232内)之间提供电连接。一个或更多微凸块228将第一再分配层226和第二再分配层230相连接，包括设置在第二层间衬底236上的第二电感结构。在一些实施例中，第二再分配层230与一个或更多金属互连层相连接，该金属互连层形成在设置在第二层间衬底236上的一个或更多介电层234之内。
在一些实施例中，3D IC结构224可以包括多个垂直连接的电感器。例如，在一些实施例中，第二再分配层230与一个或更多穿过第二层间衬底236延伸的TSV相连接。在这种实施例中，第一或更多TSV238与第三再分配层242(例如，通过形成在一个或更多介电层240内部的一个或更多金属互连层)相连接，包括设置在第二层间衬底236上方的第三电感结构。第三再分配层242被配置成在一个或更多TSV238和一个或更多金属，一个或更多微凸块244(例如，位于底部填充层248内部)之间提供电连接。一个或更多微凸块244将第三再分配层242与第四再分配层246相连接，包括设置在上面的IC管芯252之上的第四电感结构。在一些实施例中，第四再分配层246与一个或更多金属互连层相连接，该金属互连层形成在一个或更多设置在上面的IC管芯252之上的介电层250之内。
图3示出了所公开的位于堆叠管芯之间的多层螺旋电感器300的一些实施例的三维视图。
多层螺旋电感器300包括第一电感结构302和第二电感结构304。第一电感结构302包括具有导电材料的第一螺旋电感器，该导电材料形成了绕着固定中心点卷绕n匝的曲线的螺旋图案。第二电感结构304包括具有导电材料的第二螺旋电感器，该导电材料形成了以绕着固定中心点卷绕n匝的螺旋图案。在一些实施例中，第一电感结构302是第二电感结构304的镜像，从而使得第一和第二电感结构关于对称轴线308对称。
导电互连结构306被设置在第一电感结构302和第二电感结构304之间。在一些实施例中，导电互连结构306包括具有高磁导率(例如，具有50以上的相对磁导率)的磁性材料。例如，在一些实施例中，导电互连结构306可以包括铁酸盐化合物，该铁酸盐化合物包括有铁。
将理解，所公开的多层电感器可以包括具有大范围几何形状的电感结构。图4A-图4B示出了位于相邻接的可堆叠的IC管芯上的一些实施例电感结构。将理解，图4A-图4B所示出的几何形状并不是限制性的实例且所公开的电感结构可以具有其他几何形状。
图4A示出了位于第一IC管芯上的第一电感结构400的俯视图和位于第二IC管芯上的第二电感结构402的俯视图。第一电感结构400包括具有蜿蜒图案的导电材料，该导电材料沿着其长度在第一方向上卷绕且然后在与第一方向相反的第二方向上卷绕。第二电感结构402包括具有蜿蜒图案的导电材料，第二电感结构是第一电感结构400沿着对称轴线406的镜像。第一和第二电感结构402和404的几何形状提供了阳性互感。换言之，第一电感结构400导致经过第一电感结构400的电流出现变化从而在第二电感结构402中引起电动势(emf)，该电动势是之间的互感，反之亦然。
图4A还示出了俯视图404，该图示出了第一和第二电感结构400和402的重叠。第一和第二电感结构400和402通过408处的导电互连结构122沿着对称轴线406相互串联连接。
图4B示出了位于第一IC管芯上的第一电感结构410的俯视图和位于第二IC管芯上的第二电感结构412的俯视图。第一电感结构410包括以顺时针方向的旋转图案向内卷绕的导电材料。第二导电结构412包括以逆时针方向的旋转图案向内卷绕的导电材料。
图4B还示出了俯视图414，该图示出了第一和第二电感结构410和412的重叠。如俯视图414中所示的那样，第一和第二电感结构410和412通过416处的导电互连结构串联连接从而形成两个端口的电感器，该电感器在418处具有第一上端口418且在420处具有第二下端口。
图5A-图5B示出了公开的多层集成电感器的一些可选的实施例。
图5A示出了多层集成电感器500的三维视图。多层集成电感器500包括形成在第一IC管芯上的第一电感结构502和形成在第二IC管芯上的第二电感结构506。第一和第二电感结构502和506通过导电互连结构510串联连接。第一电感结构502包括绕着第一轴线504卷绕多匝的导电材料，该第一轴线垂直于第一IC管芯。第二电感结构506包括绕着第二轴线508卷绕多匝的导电材料，该第二轴线垂直于第二IC管芯。第二轴线508以非零偏移d偏离第一轴线504，从而使得第一和第二电感结构相互偏离。
图5B示出了多层集成电感器500的截面图512。如截面图512所示，第一轴线504和第二轴线508之间的偏移导致第一电感结构502的边缘以偏移D偏离第二电感结构506的边缘。在一些实施例中，第一电感结构502可以具有不同于第二电感结构506的尺寸。例如，第一电感结构502可以包括以第一半径r1远离第一轴线504进行卷绕的导电材料，该第一半径大于第二半径r2，第二电感结构506以第二半径远离第二轴线508进行卷绕。第一和第二电感结构的不同的半径r1和r2导致轴线中的偏移d不同与第一和第二电感结构502和508的边缘之间的偏移D。
将理解，所公开的电感器可以包括位于堆叠的管芯配置的相应的IC管芯上的多个电感结构。例如，第一IC管芯可以包括串联连接的一个或更多电感结构，而堆叠在第一IC管芯上的第二IC管芯可以包括一个或更多个与第一IC管芯上的电感结构串联连接的电感结构。
图6A是包括四个公开的串联连接的电感结构的多层电感器600的一些实施例的三维视图。
多层电感器600包括位于第一IC管芯(未示出)上的第一电感结构602和第二电感结构604。多层电感器600另外包括位于第二IC管芯(未示出)上的第三电感结构606和第四电感结构608，第二IC管芯垂直放置在第一IC管芯上面。第三和第四电感结构606和608通过在第三和第四电感结构606和608之间横向地延伸的导线相互连接。第一和第三导电结构602和60通过导电互连结构610垂直相连接。第二和第四电感结构604和608通过导电互连结构612垂直地相连接。
图6B示出了图表614，该图表示出了多层电感器600的电感和Q因数。
沿着第一y轴线，图表614示出了作为频率(x轴线)的函数的电感(y-轴线)。形成在相同的管芯上的电感器(即，传统的集成电感器)的电感被示为趋势线616。如所公开的电感器那样的形成在不同的管芯上的电感器的电感被示为趋势线618。传统的电感器提供的电感被限制在大约2.5GHz的共振频率上。所公开的电感器提供了在6GHz以上的共振频率上的电感。
沿着第二y轴线，图表614示出了作为频率(x轴线)的函数的Q因数(第二y轴线)。形成在相同的管芯上的电感器(即，传统的集成电感器)的Q因数被示为趋势线620。如所公开的电感器那样的形成在不同的管芯上的电感器的电感被示为趋势线622。传统的电感器提供的Q因数被限制在大约2.5GHz的共振频率上。所公开的电感器提供了在6GHz以上的共振频率上的电感。
图7是在堆叠的集成芯片(IC)管芯之间形成多层电感器的方法700的一些实施例的流程图。
虽然下面以一系列的动作和事件示出和描述了在此所提供的方法700，但将理解：这些动作或事件的所示顺序并不被解释成限制性的。例如，一些动作可以不同的顺序发生和/或与除了在此所示出和/或描述的那些所不同的动作或事件同时发生。另外，不是所有的示出的动作都应实施此处的说明书的一个或更多方面或实施例。另外，在此所述的一个或更多动作可以在一个或更多不同的动作和/或阶段中进行。
在动作702中，在第一集成芯片(IC)管芯的第一面上形成第一电感结构。在一些实施例中，第一电感结构包括螺旋结构，该螺旋结构包括设置第一IC管芯上的再分配层。
在动作704中，在第二IC管芯的第一面上形成第二电感结构。在一些实施例中，第二电感结构包括螺旋结构，该螺旋结构包括设置在第二IC管芯上的再分配层。
在动作706中，第一IC管芯通过一个或更多导电互连结构与第二IC管芯相连接，该导电互连结构电连接第一和第二电感结构。第一和第二IC管芯以第一IC管芯的第一面面向第二管芯的第一面的方式相互连接，从而使得一个或更多导电互连结构分开第一和第二电感结构。在一些实施例中，第一IC管芯的第一面与第二IC管芯的第一面面对面。第一和第二IC管芯随后通过一个或更多使用热压接合而形成的微凸块相互接触。
将理解，虽然在整个文件中参考示例性的结构(例如，图6-图15所示出的那些结构)来论述在此所述的方法的多个方面，但那些方法并不局限于所展示的相应的结构。反之，这些方法(和结构)被认为是相互独立的且能够独立成立并且在不参考附图中所述的具体方面的情况下仍可被实践。另外，此处所描述的层可以任意适合的方式形成，诸如，旋涂、溅射、生长和/或沉积技术等。
同样，本领域的技术人员可以在阅读和/或理解说明书和附图的基础上得出等效的变化和/或更改。在此所公开的内容包括所有这种更改和变化并且大体上不局限于此。另外，虽然已经借助多个实施中的仅仅一个公开了具体的特征或方面，但正如所期望的那样，这种特征或方面可以与其它实施的一个或更多其它特征和/或方面相结合。另外，对于此处所使用的措辞“包括”、“具有”、“带有”和/或它们的变型的范围而言，这些措辞均是包含意味的，类似于“包括”。同时，“示例性的”仅仅指的是一个实例，而不是最佳的。还应理解：出于简单和易于理解的目的，在此所述的部件、层和/或元件均以具体的尺寸和/或相互方位示出，但实际的尺寸和/或方位可能基本上不同于此处所述的那样。
因此，本发明涉及了一种提供了良好电感和Q因数的多层集成电感器以及相关的形成方法。
在一些实施例中，本发明涉及了一种多层集成电感器。该多层集成电感器包括第一电感结构和第二电感结构，第一电感结构包括设置在第一集成芯片(IC)管芯上的第一导电层，第二电感结构包括设置在垂直堆叠在第一IC管芯上的第二IC管芯之上的第二导电层。在第一IC管芯和第二IC管芯之间垂直设置有导电的互连结构且被配置成电连接第一导电层和第二导电层。
在其他实施例中，本发明涉及了一种多层集成电感器，包括第一电感结构和第二电感结构，第一电感结构包括设置在第一集成芯片(IC)管芯的第一面上的第一螺旋图案中的第一金属层，第二电感结构包括设置在第二IC管芯的第一面上的第二螺旋图案中的第二金属层，第二IC管芯的第一面面向第一IC管芯的第一面。在第一和第二IC管芯之间垂直设置有导电的互连结构且被配置成电连接第一金属层和第二金属层。
在其他实施例中，本发明涉及了一种形成多层集成电感器的方法。该方法包括在第一集成芯片(IC)管芯的第一面上形成第一电感结构。该方法进一步包括在第二IC管芯的第一面上形成第二电感结构。该方法另外包括通过电连接第一电感结构和第二电感结构的导电的互连结构将第一IC管芯的第一面与第二IC管芯的第一面相连接。

Claims (10)

1.一种多层集成电感器，包括：
第一电感结构，包括设置在第一集成芯片(IC)管芯上的第一导电层；
第二电感结构，包括设置在第二IC管芯上的第二导电层，所述第二IC管芯垂直堆叠在所述第一IC管芯上；以及
导电互连结构，垂直设置在所述第一IC管芯和所述第二IC管芯之间且被配置成电连接所述第一导电层和所述第二导电层。
2.根据权利要求1所述的多层集成电感器，其中，所述导电互连结构包括一个或多个微凸块或铜柱。
3.根据权利要求1所述的多层集成电感器，其中，所述导电互连结构包括铁酸盐化合物。
4.根据权利要求1所述的多层集成电感器，进一步包括：
底部填充层，设置在所述第一导电层和所述第二导电层之间且被配置成围绕所述导电互连结构。
5.根据权利要求1所述的多层集成电感器，其中，
所述第一电感结构包括绕着第一轴线卷绕第一多匝的螺旋图案，所述第一轴线垂直于所述第一IC管芯；并且
所述第二电感结构包括绕着第二轴线卷绕第二多匝的螺旋图案，所述第二轴线垂直于所述第二IC管芯。
6.根据权利要求5所述的多层集成电感器，其中，所述第一轴线和所述第二轴线以非零偏移量相分离。
7.根据权利要求1所述的多层集成电感器，进一步包括：
第三电感结构，包括垂直堆叠在所述第二IC管芯上的第三IC管芯上的第三导电层；以及
第二导电互连结构，垂直位于所述第二IC管芯和所述第三IC管芯之间且被配置成电连接所述第二导电层和所述第三导电层。
8.根据权利要求1所述的多层集成电感器，其中，
所述第一电感结构包括第一蜿蜒图案，所述第一蜿蜒图案沿着其长度在第一方向上卷绕、随后在与所述第一方向相反的第二方向上卷绕；并且
所述第二电感结构包括第二蜿蜒图案，所述第二蜿蜒图案沿着其长度在第一方向上卷绕、随后在与所述第一方向相反的第二方向上卷绕。
9.一种多层集成电感器，包括：
第一电感结构，包括在第一集成芯片(IC)管芯的第一面上设置为第一螺旋图案的第一金属层；
第二电感结构，包括在第二IC管芯的第一面上设置为第二螺旋图案的第二金属层，所述第二IC管芯的第一面面向第一IC管芯的第一面；以及
导电互连结构，垂直设置在所述第一IC管芯和所述第二IC管芯之间且被配置成电连接所述第一金属层和所述第二金属层。
10.一种形成多层集成电感器的方法，包括：
在第一集成芯片(IC)管芯的第一面上形成第一电感结构；
在第二IC管芯的第一面上形成第二电感结构；以及
通过将所述第一电感结构和所述第二电感结构电连接的导电互连结构将所述第一IC管芯的第一面与所述第二IC管芯的第一面相连接。
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