CN103970701B - The IP core of real time data synchronization collection based on field programmable gate array - Google Patents
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Abstract
The IP core of the collection of the real time data synchronization based on field programmable gate array of the present invention, belongs to the technical field of Internet of Things application.Structure has basic IP kernel module, peripheral hardware IP kernel module and sensor customized IP core module.Sensor customized IP core module includes temperature and air pressure sensor customized IP core, infrared temperature-test sensor customized IP core and temperature measuring sensor customized IP core etc..These IP kernels are all based on Avalon interface specifications, and CPU is communicated by Avalon buses with each IP kernel, is finally completed the data acquisition to sensor.The present invention can effectively overcome the poor efficiency, low rate and the defect for being unable to real-time synchronization of traditional sensors data acquisition, can connect different types of sensor interface；Under same clock, data are handled parallel, the effect of high speed acquisition is reached；Modules can be operated independently from, and realize the real-time collection of data；Being capable of efficent use of resources.
Description
Technical field
The invention belongs to the technical field of Internet of Things application, it is related to the data acquisition of polytype sensing system, specifically
It is related to the sensor data acquisition based on FPGA (field programmable gate array), the system can be widely used in industrial monitoring, agricultural
Monitoring, city management, prevent and reduce natural disasters, the field such as digital medical.
Background technology
At present, sensor penetrates into the multiple fields of national life already, and the interface mode of sensor has on the market now
It is a variety of, including one-wire interface pattern, IIC interface modes, SPI interface pattern etc., and the collection of sensing data is namely pressed
The access to sensor is realized according to corresponding interface mode.Essence is not accomplished in the collection of the sensing data in some current fields also
True synchronization, but some fields need to carry out environmental data the collection of stringent synchronization, such as digital medical, industrial monitoring
Different environmental variances is directed to Deng, these fields, it is necessary at the time of one specific such as temperature, humidity, light intensity, magnetic field
The collection of environmental data is carried out, and requires that the collection of each environmental variance larger time error can not occur, it is necessary to ensure
Real time synchronization.At present at home and abroad, the mode of collection sensing data typically has following several：Using arm processors, numeral
Signal processor or field programmable gate array are FPGA to make the processor of system.
In traditional sensor data acquisition system, the collection of sensing data is by CPU (such as single-chip microcomputer or microprocessor
Device) controlled by software simulated timing diagrams mode, virtually increase CPU pressure, inefficient, some CPU of work
It is integrated with some interface modes, such as ARM, but these interface modes, than relatively limited, once the quantity of sensor is very big, this is just
The scope that cpu i/f can be carried is exceeded.And in traditional sensor data acquisition system, because being to use serial place
Reason mode, so real time synchronization difficult to realize, also cannot carry out the collection and application of sensing data in specific occasion.
But this exactly FPGA strong point, FPGA on programming device based on developing, and it both solves customization electricity
The deficiency on road, overcomes the defect of original programming device again.The integrated level of field programmable gate array logic is high, and its device is close
Degree can complete the function of combinational logic circuit and the sequential of simulation and its complexity, it is adaptable to high end digital up to tens million of doors
The design of logic circuit, can so improve the efficiency of system acquisition data, and can realize the collection of high-speed data, additionally it is possible to prop up
Hold the data acquisition of multichannel.
The data of collection sensor are realized with FPGA, it most locates at a high speed and parallel significant advantage is that can realize
Reason.The system controlled by software its arithmetic speed certainly can not be comparable with the system of pure hardware, because software is order
The mode of execute instruction has carried out the control of paired systems, and the system of pure hardware is described with Digital Logic language, and counts
Word logical language is run in a parallel fashion, so the speed of pure hardware is obviously more faster than the system speed based on software.
FPGA uses the framework based on IP (Intellectual Property intellectual properties) core, and this mode can make each
Peripheral hardware IP kernel is operated independently from, and can accomplish synchronous purpose.Therefore more realized using the method for IP kernel at a high speed and same in real time
Step, and the use of fpga chip is more reasonable.So the present invention just be the sensor data acquisition based on FPGA.
The content of the invention
The purpose of the present invention is exactly to propose a kind of real time data synchronization collection IP kernel based on FPGA, overcomes traditional sensing
Poor efficiency, low rate and the defect for being unable to real-time synchronization of device data acquisition, realize the parallel place to sensor data acquisition
Reason, and reach that relatively high picking rate requires and realized the real-time synchronization characteristic of sensor data acquisition.What it was realized
Mechanism is as shown in Figure 1.
The present invention is the specification based on Avalon buses, designs corresponding IP kernel, and constitute NIOS II processors system
Framework, the hardware scheme of the design unite as shown in Fig. 2 hardware configuration is divided into three parts, basic IP is illustrated in figure 3
Core module (that is, essential intellectual property rights core module), Fig. 4 is peripheral hardware IP kernel module (that is, peripheral hardware intellectual property core module), and Fig. 5 is
Sensor customized IP core module (that is, the self-defined intellectual property core module of sensor).
Basic IP kernel module：The part is that soft appraise and decide of NIOS II has been made including CPU, SDRAM, FLASH, including SYSID
IP kernel, forms most basic processor system.These IP kernels are provided with the clock frequency of system, interrupt address and storage
Location.
Peripheral hardware IP kernel module：The part is that soft appraise and decide of NIOS II has made timer core, universal input/output core, memory
Core, serial ports controller core etc..These IP kernels provide basic timing for system, storage, the function of input and output.
Sensor customized IP core module：Different sensors module accordingly connects by Digital Logic language customization for the part
The IP kernel of mouth, including temperature and air pressure sensor ms5607, infrared temperature-test sensor mlx90615 and temperature measuring sensor
ds18b20.The design of the part uses Digital Logic language, and all obeys Avalon buses.
The design of the design is exactly the IP kernel module by formulating three parts above, based on Avalon architecture for exchanging,
Different sensor customized IP cores is integrated into a processor system, independently of one another operation, reaches the parallel, mesh of high speed
's.
In order to realize the above object the sensor customized IP core that the present invention is customized uses following technical scheme：Use number
Word logical language writes the customized IP core of sensor, that is, generates the logic hardware of sensor acquisition module, makes independent
Soft core, and finally realize parallel high-speed handle.
The design of temperature and air pressure sensor ms5607 in the present invention is as follows, and Fig. 6 is temperature, air pressure sensor chip
Ms5607 interface protocol, Fig. 7 is the interface sequence of the chip initiation, and Fig. 8 show the chip and reads memory command
Interface sequence, Fig. 9 is the interface sequence of data conversion step, and Figure 10 is reads the interface sequence of conversion value, and shown in Figure 11 is
Using Digital Logic vorbal model interface sequence and the state machine of interface sequence agreement is realized, Figure 12 is that the state machine of initialization shows
It is intended to, Figure 13 is temperature, the state machine diagram of baroceptor ms5607 data conversions, Figure 14 is that ms5607 reads conversion value
State machine diagram.
The design of infrared temperature-test sensor mlx90615 in the present invention is as follows, and Figure 15 is infrared measurement of temperature chip mlx90615
Interface protocol, Figure 16 is the sequential of the interface, and shown in Figure 17 is the state machine that Digital Logic language realizes the sequential.
The design of temperature measuring sensor ds18b20 in the present invention is as follows, and Figure 18 is ds18b20 temperature sensor chips
Interface protocol, Figure 19 is the initialization interface sequential of the chip, and Figure 20 show the interface sequence that the chip writes bit, figure
18 show the interface sequence for reading bit, and shown in Figure 21 is the state machine that Digital Logic language realizes the sequential.
The sensor customized IP core of the design by using Digital Logic vorbal model interface sequence, adoption status machine
Method realizes the agreement of interface sequence, in the state machine implementation process of each sensor customized IP core, all employs shape
The nested mechanism of state machine.
By basic IP kernel module described above, peripheral hardware IP kernel module, sensor customized IP core module is all integrated into one
In individual system, that is, the soft cores of NIOS II are generated, as shown in figure 22.Pass through synchronization mechanism proposed by the present invention, each IP kernel module
Can independent operating.
Summary, concrete technical scheme of the invention is as follows.
The IP core that real time data synchronization of the one kind based on field programmable gate array (FPGA) is gathered
(Intellectual Property Core), structure has basic IP kernel module, including including CPU, SDRAM, FLASH, SYSID
IP kernel；Peripheral hardware IP kernel module, including timer core, general purpose I/O core, memory core, serial ports controller core；Characterized in that,
Structure also has sensor customized IP core module；Described sensor customized IP core module, is passed by temperature and air pressure
Sensor customized IP core, infrared temperature-test sensor customized IP core and temperature measuring sensor customized IP core are constituted, each sensing
Device customized IP core the corresponding interface IP kernel of different sensors modules, integrated different sensors by Digital Logic language customization
It is outer to be located at a system, parallel operation；
Basic IP kernel module, peripheral hardware IP kernel module and sensor customized IP core module are all based on Avalon interface specifications
, be the port using NIOS II processors as master port, remaining port is that from port, these include universal asynchronous receive from port
Send out transmitter (UART) port, timer port, parallel input/output (PIO) port, flash memory (Flash) port, sensor side
Mouth, synchronous DRAM (SDRAM) port；CPU passes through Avalon buses and basic IP kernel module, peripheral hardware IP kernel module
Communicated with sensor customized IP core module, be finally completed the data acquisition to sensor.
Described temperature and air pressure sensor customized IP core, using ms5607 chips；Described infrared temperature-test sensor is certainly
IP kernel is defined, using mlx90615 chips；Described temperature measuring sensor customized IP core, using ds18b20 chips.
Described temperature and air pressure sensor customized IP core, sets interface protocol, and the interface sequence of initialization reads storage
The interface sequence of device order, the interface sequence of data conversion step, the interface sequence of reading conversion value, digital logic states machine,
The state machine of initialization, the state machine of data conversion reads the state machine of conversion value.
Described infrared temperature-test sensor customized IP core, sets interface protocol, interface sequence, digital logic states machine.
Described temperature measuring sensor customized IP core, sets interface protocol, and initialization interface sequential writes bit
Interface sequence, reads the interface sequence of bit, reads the digital logic states machine of bit.
The present invention realizes that the technical scheme of the method for the real-time collection of sensing data is as follows.
A kind of method for the real-time collection for realizing sensing data, based on basic IP kernel module, peripheral hardware IP kernel module and biography
Sensor customized IP core module, the real-time collection of sensing data is realized using following following four step：(1) sensor is made by oneself
Adopted IP kernel, in same clock along starting, starts to gather sensor number according to field programmable gate array (FPGA) concurrency
According to；(2) sensor customized IP core module gathers sensing data respectively according to the interface protocol of respective sensor, by collection
Data are beamed back to be preserved in CPU buffer；(3) CPU records any two sensing in sensor customized IP core module
Device passes data back CPU time, once there is the situation for passing time irreversibility back, then wherein the time required to shorter sensor
Automatic time delay, the arrival until waiting another sensor echo back data can be carried out according to respective interface protocol；(4) CPU pairs
Data are handled, and are once again set up the clock of collection, and start the collection of sensing data simultaneously.Pass through this four steps
Suddenly, synchronization process of the CPU to data is finally realized, the synchronous acquisition of data is realized.
Using the system of IP kernel of the present invention, can effectively overcome the poor efficiency of traditional sensors data acquisition, low rate and
The defect of real-time synchronization is unable to, a large amount of different types of sensor interfaces can be connected；Can be parallel right under same clock
Data are handled, and reach the effect of high speed acquisition；Modules can be operated independently from, under parallel synchronous mechanism, with regard to energy
Realize the real-time collection of data, and modules can realize the energy-conservation of sensor according to the speed degree of data acquisition；By
It is high in FPGA integrated level, so being capable of efficent use of resources using the system of IP kernel of the present invention.
Brief description of the drawings
Fig. 1 is the real-time synchronization sequential logic schematic diagram of the design.
Fig. 2 is the schematic diagram for the hardware plan that the design is used.
Fig. 3 is basic IP kernel module diagram.
Fig. 4 is peripheral hardware IP kernel module diagram.
Fig. 5 is sensor customized IP core module diagram.
Fig. 6 is temperature and air pressure sensor ms5607 interface protocol schematic diagram.
Fig. 7 is the interface sequence schematic diagram of temperature and air pressure sensor ms5607 initialization.
Fig. 8 is the interface sequence schematic diagram that temperature and air pressure sensor ms5607 reads memory command.
Fig. 9 is the interface sequence schematic diagram of temperature and air pressure sensor ms5607 data conversion steps.
Figure 10 is the interface sequence schematic diagram that temperature and air pressure sensor ms5607 reads conversion value.
Figure 11 is temperature and air pressure sensor ms5607 digital logic states machine schematic diagram.
Figure 12 is the state machine diagram of temperature and air pressure sensor ms5607 initialization.
Figure 13 is the state machine diagram of temperature and air pressure sensor ms5607 data conversions.
Figure 14 is the state machine diagram that temperature and air pressure sensor ms5607 reads conversion value.
Figure 15 is infrared measurement of temperature chip mlx90615 interface protocol schematic diagram.
Figure 16 is infrared measurement of temperature chip mlx90615 interface sequence schematic diagram.
Figure 17 is infrared measurement of temperature chip mlx90615 digital logic states machine schematic diagram.
Figure 18 is the interface protocol schematic diagram of temperature measuring sensor ds18b20 chips.
Figure 19 is temperature measuring sensor ds18b20 chip initiation interface sequence schematic diagrames.
Figure 20 is the interface sequence schematic diagram that temperature measuring sensor ds18b20 chips write bit.
Figure 21 is the interface sequence schematic diagram that temperature measuring sensor ds18b20 chips read bit.
Figure 22 is the digital logic states machine schematic diagram that temperature measuring sensor ds18b20 chips read bit.
Figure 23 is all peripheral hardware IP kernel modules of NIOS II processor systems
Embodiment
The real-time synchronization sequential logic of the system of embodiment 1
Reference picture 1, the figure shows the real-time synchronization sequential logic schematic diagram of system.It is visible in figure to have three kinds of signals,
Wherein CLK is the clock signal of system, and input0 is the collection signal that sensor 1 is inputted to CPU, input1 be sensor 2 to
The collection signal of CPU inputs.Present invention utilizes FPGA parallel feature, arbitrarily sensed in sensor customized IP core module
Device 1 and sensor 2 are independent IP kernels, meet AVALON buses, and two IP kernels can enter when a clock leading edge arrives simultaneously
Row data acquisition.
T0 is the time needed for the gathered data of sensor 1, and T1 is the time needed for the gathered data of sensor 2, and t0 is sensing
The data of collection are sent to the transmission time that CPU carries out data processing by device 1, and t1 is that the data of collection are sent to by sensor 2
CPU carries out the transmission time of data processing, and Δ t is in order that the data that sensor 1 is gathered with sensor 2 are passed CPU back and carried out together
The time difference of processing is walked, and two sensors are carried out the collection of signal, data transmitted after having gathered by the present invention in synchronization
Cpu cache device is given to wait data processing, when two sensors pass data back CPU time of occurrences nonsynchronous situation, that
Shorter sensor can carry out automatic time delay according to respective interface protocol the time required to wherein, and set gather again same
Clock is walked, the purpose of CPU synchronization process data is finally realized, what is 1. and 2. represented is the time that CPU synchronizes processing data
Point and again the clock edge of gathered data.
The data of CPU processing come from each sensor, and the data of each sensor are carried out on same clock edge, i.e.,
What CPU was received is synchronization so sensing data, so the present invention realizes the real-time same of sensor data acquisition
Step property.The timing diagram is the simple situation for introducing two kinds of sensors, because FPGA interface resource is more, so can load
Kind of sensor enriches, but can realize real time synchronization.Embodiment 2NIOS II processor system frameworks
Reference picture 2, the figure shows the hardware scheme that the design is used.Hardware structure is divided into three by the design
Part, including basic IP kernel module, peripheral hardware IP kernel module, sensor customized IP core module.NIOS II processor systems are bases
In the premise of Avalon bus switch frameworks, the port of NIOS II processor is master port, and the port of remaining peripheral hardware is from end
Mouthful, the system includes the self-defined controller core of three sensor assemblies, timer core, general purpose I/O core, memory from peripheral hardware
Core, serial ports controller core etc..CPU is communicated by Avalon buses with each peripheral hardware, is adopted the data that complete to sensor
Collection.
Reference picture 3, the figure shows be basic IP kernel module.Basic IP kernel module include NIOS II processor cores,
Sdram controller core, FLASH controller core etc..
Reference picture 4, the figure shows be peripheral hardware IP kernel module.Peripheral hardware IP kernel module includes universal input/output core, storage
Device core, serial ports controller core etc..
Reference picture 5, the figure shows be sensor customized IP core module.Sensor customized IP core module is each biography
The controller core of sensor, the present invention includes 1. temperature and air pressure sensor ms5607 customized IP cores, 2. infrared temperature-test sensor
Mlx90615 customized IP cores and 3. temperature measuring sensor ds18b20 customized IP cores.
The temperature and air pressure sensor ms5607 customized IP cores of embodiment 3
Reference picture 6, the figure shows be temperature, baroceptor ms5607 interface protocol.According to ms5607 chip
Handbook, it is known that carrying out data acquisition to the sensor needs using seven steps, the first six step is as shown in fig. 6, have
Respective corresponding command byte.The reading sequencing of data is first to read 8 values of consult volume (C0~C7), then read D1's
Value, finally reads D2 value.
Reference picture 7, the figure shows be temperature, baroceptor ms5607 initialization interface sequence.Can by timing diagram
To find out, CSB drags down enable bus；Judge SDI value in the rising edge of clock, SDI value is the required life for completing step
The value of byte is made, SDI values now are 0x1e, are reset command；After order input process, SDO keeps high level state, one
Denier completes the input of order, and SDO is dragged down and waited the step of 2.8ms confirms execution to be reset, while SCLK also keeps dragging down
State；After after 2.8ms, SDO is drawn high, and SCLK keeps ortho states, after certain time, CSB release buses.PS signals are model selection
Signal, when it is low level, expression uses SPI mode, is otherwise IIC patterns, hardware PS is grounded all the time in the design
, so ignoring PS signal in timing simulation.
Reference picture 8, the figure shows be temperature, baroceptor ms5607 read memory command interface sequence.This
In figure, SDI inputs are values that command byte is 0xa6, i.e. Ad2, Ad1, Ad0 is followed successively by 0,1,1, that is, that read is C4
Value.Digital independent from C0 to C7 is required for completing the when program process of upper figure, when each parameter is read, first input life
Byte is made, then obtains 16bit data.CSB signals are kept in the reading process of command byte input and data is carried out all the time
Low level, enables spi bus, and release bus is drawn high if 8 parameters read and finished.SDO is when byte command is inputted
High level state is kept, low level state is kept when reading 16bit data.
Reference picture 9, the figure shows be temperature, baroceptor ms5607 data conversion steps interface sequence.The figure
For the timing diagram of D1 switch process, the command byte of SDI inputs is 0x48, and command byte input finishes rear SCLK and keeps low level
8.22ms；CSB keeps in the order input for completing SDI and low level in 8.22ms stand-by period, it is ensured that enable SPI total
Line, once motion terminates just to draw high release bus；SDO keeps high level in input state, once SDI inputs are finished, then draws
Low hold 8.22ms；PS remains low level.The sequential of D2 switch process is similar with D1 switch process, and difference is
The command byte of SDI inputs is different, and the order of D2 switch process is 0x58.
Reference picture 10, the figure shows be temperature, baroceptor ms5607 read conversion value interface sequence.SDI is first
Input Read ADC command byte：0x00, the state value of input is read in the rising edge of clock, and now SDO remains high
Level state；Afterwards, SDI keeps low level, and SDO starts to export 24bit data；CSB signals during execution all the time
Low level state is kept, once terminate to draw high.
Reference picture 11, the figure shows be temperature, baroceptor ms5607 digital logic states machine.With
During Verilog vorbal model moulds ms5607 agreement, according to ms5607 use flow, its state machine is segmented into the 8 of the figure
Individual state.
Reference picture 12, the figure shows be temperature, baroceptor ms5607 initialization state machine.Simulation initialization step
Rapid sequential divide into three states, first write 8bit command byte：0x1e, then waits 2.8ms delay, once delay
Explanation initialization step success is finished, is one by the mark position of initialization step, to show whether judgment step completes.Reference
Figure 13, the figure shows be temperature, baroceptor ms5607 data conversions state machine.
Reference picture 13, the figure shows be temperature, baroceptor ms5607 data conversions state machine.Simulate D1 steps
Sequential need to undergo three states, first write the command byte 0x48 of D1 switch process, it is to be written to be successfully carried out delay
8.22ms delay state, successfully means that D1 switch process is finished once being delayed, and is one by the mark position of D1 switch process.
The simulation of D2 switch process is similar with D1 switch process, and difference is that the command byte write is 0x58.
Reference picture 14, the figure shows be temperature, baroceptor ms5607 read conversion value state machine.Read conversion
Value step is divided into five states, and first writing commands byte 0x00 is then successively read the high, medium and low 8bit of 24bit data number
According to finally complement mark position 1 is terminated.
The infrared measurement of temperature chip mlx90615 customized IP cores of embodiment 4
Reference picture 15, the figure shows be infrared measurement of temperature chip mlx90615 interface protocol.Mlx90615 uses SMBus
There being agreement during pattern reads and the agreement write, that is, the flow read and write, as shown in the drawing to be respectively SMBus reading agreement and write association
View.Wherein each link is represented respectively means S：Start, SlaveAddress:From address, Wr：Write (bit are 0), A：
Response, Sr：Restarting, Rd：Read (bit are 1), Data Byte Low：The low byte of data, Data Byte High：Number
According to high byte, PEC：Examine position, P in school：Stop.
Reference picture 16, the figure shows be infrared measurement of temperature chip mlx90615 interface sequence.When can be seen that by the figure
When clock signal (SCL) keeps high level, data wire (SDA) from high to low, represents the startup of bus；SCL keeps high level, SDA
Keep high level or low level constant, it is meant that just to transmit data, if necessary to the level value of change data, then need
SCL keeps changing polarity during low level；SCL keeps high level, and SDA represents that bus stops transmission from low to high, now；SDA is every
During the data of one byte of reading or write-in, the ACK that can transmit or receive a bit between SCL low period believes
Number.In the present invention, because calculating the value of temperature using data in reading ram register, only used in agreement
Reading mode.By the figure it is known that the flow for reading memory substantially, first starts bus, transfer address often receives one
Individual byte sends response or sends a byte and is followed by being responded, and restarts, and sends address, sends response, and segmentation receives 2
The data of individual byte, send response, stop bus.According to the command instruction of previously described read/write address and memory, only
There is a mlx90615, use the address i.e. 5Bh that dispatches from the factory, plus read-write flag bit behind 7 bit addresses, finally synthesize
B7h is reads from address in 8 bits, and B6h is to write from address；Command instruction is 0x27, and expression is that RAM is operated.
Reference picture 17, the figure shows be infrared measurement of temperature chip mlx90615 digital logic states machine.More than
Agreement and corresponding sequential, just corresponding waveform can be exported with Digital Logic vorbal model device sequential.In emulation bus sequential
When, Digital Logic language is needed to use state machine, and 12 states as shown in Figure 5 are segmented into according to above-mentioned sequential.
Each state of mlx90615 state machines is each protocol steps of correspondence and sequential, utilizes the realization pair of this state machine
Mlx90615 Digital Logic simulation, and be loaded into according to Avalon bus specifications in NIOS II soft-core processor systems.
The temperature measuring sensor ds18b20 customized IP cores of embodiment 5
Reference picture 18, the figure shows be temperature measuring sensor ds18b20 chips interface protocol.According to ds18b20
Chip handbook, it is known that carrying out data acquisition to the sensor needs using five steps, as shown in figure 18, each step
There is each corresponding command byte, a piece of ds18b20 photographs have only been used in the design, so in ROM operations, saving
The link of search has been gone, ROM is directly skipped.
Reference picture 19, the figure shows be temperature measuring sensor ds18b20 chip initiation interface sequences.Initialization step
Suddenly main frame needs to initiate reset pulse of the duration between 480us to 960us first, then wait 15 to 60us when
Between, secondly slave needs the low level pulse that response arrives 240us for one 60, last bus release.
Reference picture 20, the figure shows be temperature measuring sensor ds18b20 chips write bit interface sequence.When writing
Enter be bit 0 when, bus firstly the need of keep low level 60us, then draw high more than 1us time；And write-in is bit
When 1, bus first keeps the time that low level is more than 1us, then keeps low level 60us time.
Reference picture 21, the figure shows be temperature measuring sensor ds18b20 chips read bit interface sequence.Work as reading
Take be bit 0 when, bus first keeps low level for a period of time, then draw high holding 60us；What it is when reading is bit 1
When, bus first drags down several microseconds, then keeps more than high level 60us.
Reference picture 22, the figure shows be temperature measuring sensor ds18b20 chips read bit digital logic states
Machine.According to ds18b20 interface protocol, agreement is divided into 14 states as shown in figure 22 when the design is simulated with Verilog.
The NIOS II processor systems of the system of embodiment 6
Reference picture 23, the figure shows be by basic IP kernel module, peripheral hardware IP kernel module, sensor customized IP core module
All it is added in the system in SOPC Builder instruments, generates the complete soft cores of NIOS II, is exactly that system owns shown in the figure
Peripheral hardware.
Claims (3)
1. a kind of IP core of the real time data synchronization collection based on field programmable gate array, structure has basic IP kernel mould
IP kernel including block, including CPU, SDRAM, FLASH, SYSID；Peripheral hardware IP kernel module, including timer core, general purpose I/O core are deposited
Reservoir core, serial ports controller core；Characterized in that,
Structure also has sensor customized IP core module；Described sensor customized IP core module, by temperature and air pressure sensor
Customized IP core, infrared temperature-test sensor customized IP core and temperature measuring sensor customized IP core are constituted；Described temperature
Baroceptor customized IP core, sets interface protocol, and the interface sequence of initialization reads the interface sequence of memory command,
The interface sequence of data conversion step, reads the interface sequence of conversion value, digital logic states machine, the state machine of initialization, number
According to the state machine of conversion, the state machine of conversion value is read；Described infrared temperature-test sensor customized IP core, sets interface to assist
View, interface sequence, digital logic states machine；Described temperature measuring sensor customized IP core, sets interface protocol, initialization
Interface sequence, writes the interface sequence of bit, reads the interface sequence of bit, reads the digital logic states machine of bit；It is each to pass
Sensor customized IP core the corresponding interface IP kernel of different sensors modules by Digital Logic language customization, integrated different sensings
Located at a system, parallel operation outside device；Each sensor is according to the concurrency of field programmable gate array, same
Clock starts to gather sensing data, realizes the synchronous acquisition of data along starting, and is carried out according to each sensor interface agreement automatic
Delay, realizes that sensing data synchronously arrives at receiving terminal；
Basic IP kernel module, peripheral hardware IP kernel module and sensor customized IP core module are all based on Avalon interface specifications,
Be the port using NIOS II processors as master port, remaining port is that from port, these include universal asynchronous receiving-transmitting biography from port
Defeated device port, timer port, parallel input/output port, flash memory port, sensor port, synchronous DRAM
Port；CPU is led to by Avalon buses and basic IP kernel module, peripheral hardware IP kernel module and sensor customized IP core module
Letter, is finally completed the data acquisition to sensor.
2. the IP core of the real time data synchronization collection according to claim 1 based on field programmable gate array,
Characterized in that, described temperature and air pressure sensor customized IP core, using ms5607 chips；Described infrared temperature-test sensor
Customized IP core, using mlx90615 chips；Described temperature measuring sensor customized IP core, using ds18b20 chips.
Passed 3. a kind of IP core of the collection of the real time data synchronization based on field programmable gate array of claim 1 is realized
The method of the real-time collection of sensor data, the real-time collection of sensing data is realized using following four step：(1) sensor from
Concurrency of the IP kernel according to field programmable gate array is defined, in same clock along starting, starts to gather sensing data；
(2) sensor customized IP core module gathers sensing data respectively according to the interface protocol of respective sensor, by the number of collection
According to being preserved in the buffer for beaming back CPU；(3) CPU records any two sensor in sensor customized IP core module
Data are passed back to CPU time, once there is the situation for passing time irreversibility back, then the wherein shorter sensor meeting of required time
Automatic time delay, the arrival until waiting another sensor echo back data are carried out according to respective interface protocol；(4) CPU logarithms
According to being handled, and the clock of collection is once again set up, and starts the collection of sensing data simultaneously.
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| CN107291651A (en) * | 2017-07-05 | 2017-10-24 | 山东超越数控电子有限公司 | A kind of parallel bus automatic compensating method based on FPGA |
| CN110965983A (en) * | 2018-09-27 | 2020-04-07 | 中国石油化工股份有限公司 | Underground electromagnetic flaw detector |
| CN111506461A (en) * | 2019-01-14 | 2020-08-07 | 新岸线(北京)科技集团有限公司 | Bus-based back pressure module for testing and implementation method thereof |
| EP3753804A1 (en) * | 2019-06-17 | 2020-12-23 | Mitsubishi Heavy Industries, Ltd. | Modular surveillance system for an infrastructure and/or a vehicle |
| CN110908942B (en) * | 2019-11-28 | 2021-09-07 | 武汉华之洋科技有限公司 | FPGA-based IP core and method for freely converting multiple encoder protocols |
| CN110907693B (en) * | 2019-12-10 | 2022-02-01 | 航天新长征大道科技有限公司 | Compact peripheral interconnection bus board card |
| JP7468618B2 (en) * | 2020-03-19 | 2024-04-16 | 日本電気株式会社 | Billing information processing device, billing information processing system, billing information processing method, and billing information processing program |
| CN112765080A (en) * | 2021-01-22 | 2021-05-07 | 联想(北京)有限公司 | Information processing method and equipment |
| CN114137922A (en) * | 2021-11-28 | 2022-03-04 | 浙江中控技术股份有限公司 | Data processing method and device for industrial control system and storage medium |
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