CN112765080A - Information processing method and equipment - Google Patents
Information processing method and equipment Download PDFInfo
- Publication number
- CN112765080A CN112765080A CN202110086865.4A CN202110086865A CN112765080A CN 112765080 A CN112765080 A CN 112765080A CN 202110086865 A CN202110086865 A CN 202110086865A CN 112765080 A CN112765080 A CN 112765080A
- Authority
- CN
- China
- Prior art keywords
- operation mode
- parameter information
- functional module
- core
- feeding back
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention discloses an information processing method and equipment, which are applied to a device to be tested configured with a functional module and comprise the following steps: based on a first instruction, periodically switching the operation mode of an IP core in the functional module; if the IP core is in a first operation mode, feeding back first parameter information representing the state of the functional module; and if the IP core is in a second operation mode, feeding back second parameter information representing the state of the device to be tested. Therefore, the first operation mode and the second operation mode are set for the IP core of the functional module and are periodically switched according to the first instruction, and the detected states are fed back in different operation modes.
Description
Technical Field
The present invention relates to the field of server technologies, and in particular, to an information processing method and device.
Background
At present, a power management module on a server side acquires state information of peripheral equipment of an accelerator card by adding an IIC IP core resource for each peripheral equipment on an FPGA chip, and the method has the defect of increasing operation resources.
Disclosure of Invention
The embodiment of the invention provides an information processing method and equipment, which have the technical effect that the peripheral state of an FPGA chip can still be acquired under the condition that IP core resources are not increased.
One aspect of the present invention provides an information processing method applied to a device under test configured with a functional module, the method including: based on a first instruction, periodically switching the operation mode of an IP core in the functional module; if the IP core is in a first operation mode, feeding back first parameter information representing the state of the functional module; and if the IP core is in a second operation mode, feeding back second parameter information representing the state of the device to be tested.
In an embodiment, the periodically switching the operation mode of the IP core in the functional module includes: the operation mode is initially the first operation mode; and switching the operation mode to the second operation mode every preset time, and after feeding back the second parameter information, switching the operation mode to the first operation mode again.
In an embodiment, if the IP core is in the first operation mode, the method further includes: monitoring the first parameter information in real time, and storing the first parameter information into an information base; correspondingly, the feeding back the first parameter information includes: and extracting first parameter information in the information base and feeding back the first parameter information.
In an embodiment, the feeding back the first parameter information includes: and receiving and responding to a second instruction to feed back the first parameter information.
In one embodiment, the second parameter information includes a temperature parameter and a voltage parameter.
Another aspect of the present invention provides an information processing apparatus including a device under test configured with a functional module, a first device, and a second device; the first device is connected to the functional module in a communication manner and used for sending a first instruction to the functional module so as to periodically switch the operation mode of an IP core in the functional module; the first device is further configured to feed back first parameter information representing a state of the functional module when the IP core is in a first operating mode; and the second device is used for feeding back second parameter information representing the state of the device to be tested when the IP core is in a second operation mode.
In an embodiment, the first device is specifically configured to: and sending a first instruction to the functional module at intervals of a preset time length to instruct the IP core to switch the operation mode to the second operation mode, and after the first device feeds back the second parameter information, switching the operation mode to the first operation mode.
In an embodiment, the first device is specifically configured to: monitoring the first parameter information in real time, and storing the first parameter information into a register; correspondingly, when feeding back the first parameter information, the first device is specifically configured to: and extracting first parameter information in the register and feeding back the first parameter information.
In an implementation manner, when feeding back the first parameter information, the first device is specifically configured to: and receiving and responding to a second instruction sent by a third device to acquire the first parameter information and feed back the first parameter information to the third device.
In an implementation manner, the first device is a micro control unit MCU, the second device includes a temperature sensor and a current sensor, the third device is a power management device BMC, and the functional module is an FPGA chip.
In the embodiment of the invention, the first operation mode and the second operation mode are set for the IP core of the functional module, and the operation mode feedback is periodically switched.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
FIG. 1 is a schematic diagram of an implementation flow of an information processing method according to an embodiment of the present invention;
fig. 2 is a schematic flow chart illustrating an implementation process of each operation mode in an information processing method according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an information processing apparatus according to an embodiment of the present invention;
fig. 4 is a detailed feedback flowchart of an information processing method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an aspect of the present invention provides an information processing method applied to a device under test configured with a functional module, where the method includes:
102, if the IP core is in a first operation mode, feeding back first parameter information representing the state of the functional module;
and 103, if the IP core is in the second operation mode, feeding back second parameter information representing the state of the device to be tested.
In this embodiment, the functional module is a hardware such as an FPGA (Field Programmable Gate Array) chip, a CPLD (Complex Programmable Logic Device) chip and the like that can configure an IP core, and the FPGA chip is preferred in this embodiment. The device to be tested includes an accelerator card, a video card, a sound card, and the like, and in this embodiment, the device to be tested is preferably the accelerator card.
Referring to fig. 2 and fig. 3, in step 101, the first command may be a periodic clock signal or a pulse signal, and may be sent by internal hardware (such as a micro control unit MCU) mounted on the device under test, or may be sent by an external device (such as a central processing unit CPU) connected to the device under test. The triggering mode of the first instruction is mainly triggered according to a local clock or an external clock, and comprises a high level signal and a low level signal. The function module can configure a first operation mode and a second operation mode in advance through a software program, and after the function module obtains a first instruction, the operation mode of the IP core is switched through a preset software program according to a clock high-low level signal.
In steps 102 and 103, the operation mode includes a first operation mode and a second operation mode, and when the application is performed, the first operation mode may correspond to a high level of the clock signal, and the second operation mode corresponds to a low level of the clock signal, when the clock signal is at the high level, the operation mode of the IP core is switched to the first operation mode, and when the clock signal is at the low level, the operation mode of the IP core is switched to the second operation mode. Of course, the reverse is also possible, i.e. the first operation mode corresponds to a low level of the clock signal and the second operation mode corresponds to a high level of the clock signal.
And when the operation mode of the IP core is in the first operation mode, acquiring and feeding back first parameter information representing the state of the functional module. Specifically, the first parameter information includes parameters such as temperature and voltage inside the functional module, and the parameters inside the functional module cannot be directly obtained by using peripheral devices (such as a temperature sensor and a voltage sensor), so when the IP core is in the first operation mode, the feedback mode of the first parameter information may be that the processor (such as the MCU) queries the device to be tested according to a preset access address of the device to be tested and obtains the first parameter information, and then the first parameter information is fed back by writing the first parameter information into the configured register.
And when the operation mode of the IP core is in a second operation mode, obtaining and feeding back second parameter information representing the state of the device to be tested. Specifically, the second parameter information includes parameters of the device to be tested, such as temperature, voltage, and current, and the parameters of the device to be tested may be directly measured by external devices, such as a temperature sensor, a current sensor, and an EEPROM register, which are connected to the I2C interface of the functional module, so that when the IP core is in the second operation mode, the feedback mode of the second parameter information may query each external device through the preset access address of each external device, acquire the state information monitored by each external device, and then feed back the acquired state information.
The feedback object is determined according to the requirement, for example, the power management module BMC at the server side needs to acquire and manage the state of the device to be tested, such as the accelerator card, and then the first parameter information and the second parameter information are fed back to the power management module.
Therefore, the first operation mode and the second operation mode are set for the IP core of the functional module and are periodically switched according to the first instruction, and the detected states are fed back in different operation modes.
In one embodiment, the periodically switching the operation mode of the IP core in the functional module includes:
the operation mode is initially a first operation mode;
and switching the operation mode to a second operation mode every preset time length, and after feeding back second parameter information, switching the operation mode to the first operation mode again.
In this embodiment, because the parameter inside the functional module has a large influence on the whole functional module, the operation mode is initially the first operation mode to monitor the state inside the functional module for a long time, that is, the time length in the first operation mode is long in a period of a preset time length. In this embodiment, the preset duration is preferably the period duration of the clock signal, and if the first operation mode corresponds to the high level of the clock signal, the duration of the clock signal at the high level is longer, and the duration of the clock signal at the low level is shorter. When the operation mode is in the first operation mode, if the clock signal has high and low potential changes, the functional module responds to the potential changes to switch the operation mode from the first operation mode to the second operation mode, and after the functional module feeds back the second parameter information, the operation mode is switched to the first operation mode again in a short time due to the short duration of the low level.
Further, when the operation mode is switched to the second operation mode, the processor may actively read status information monitored by each peripheral device, and send the status information to the power management module BMC through an SMBUS bus (i.e., a low-speed data channel in the figure) of the PCIE interface on the device to be tested, and certainly, the status information may also be sent to the power management module BMC through a high-speed data channel on the PCIE interface.
In summary, referring to fig. 3 and fig. 4, taking the functional module as the FPGA as an example, the general implementation process of the above steps is as follows:
firstly, an IP core of the FPGA is set to be in a first operation mode so as to obtain parameters inside the FPGA, and meanwhile, an access address of the device to be tested is preset through software so that the micro control unit can inquire the device to be tested according to the access address of the device to be tested.
Secondly, the micro control unit periodically sends a clock signal to the FPGA, assuming that a high level corresponds to the first operation mode and a low level corresponds to the second operation mode. If the clock signal is at a high level, the current operation mode is the first operation mode, and when the device to be tested receives a data reading request sent by a power management module BMC on the server side, the control unit queries the device to be tested according to the access address of the device to be tested, acquires the parameters in the FPGA, and feeds the parameters back to the power management module BMC in a register writing mode. And when the clock signal is at a low level, the current operation mode is switched to a second operation mode, the access address of each peripheral device (such as a temperature sensor, a current sensor and the like) is preset through software, the server side or the micro control unit inquires each peripheral device through the access address of the peripheral device and acquires each peripheral state, and the acquired peripheral state is actively sent to the power management module BMC through the SMBUS.
Due to the fact that the time length of the clock signal in the low level is short, after the clock signal is sent in the second operation mode, the clock signal is switched to the first operation mode shortly, and the clock signal continues to wait for the reading request of the power management module BMC in the first operation mode.
In an implementation manner, if the IP core is in the first operation mode, the method further includes:
monitoring first parameter information in real time, and storing the first parameter information into an information base;
correspondingly, the first parameter information is fed back, and the method comprises the following steps:
and extracting first parameter information in the information base and feeding back the first parameter information.
In this embodiment, if the IP core is in the first operating mode, the first parameter information inside the functional module is stored in the information base in real time, and the access request of the power management module BMC is received in real time, and after receiving the second instruction sent by the power management module BMC to obtain the first parameter information, the microcontroller or the processor reads and feeds back the latest first parameter information in the information base.
Another aspect of an embodiment of the present invention provides an information processing apparatus, including a device under test configured with a functional module, a first device, and a second device;
the first device is in communication connection with the functional module and is used for sending a first instruction to the functional module so as to periodically switch the operation mode of the IP core in the functional module;
the first device is also used for feeding back first parameter information representing the state of the functional module when the IP core is in a first operation mode;
the second device is used for feeding back second parameter information representing the state of the device to be tested when the IP core is in the second operation mode.
Referring to fig. 2, in this embodiment, the functional module may be an FPGA (Field Programmable Gate Array), a CPLD (Complex Programmable Logic Device), and the like, and preferably, the functional module is an FPGA chip. The device to be tested comprises an accelerator card, a display card, a sound card and the like, and preferably, the device to be tested is the accelerator card. The first device can be a micro control unit MCU or a central processing unit CPU, and preferably the first device is the micro control unit MCU. The second device includes a temperature sensor, a current sensor, an EEPROM register, and the like.
When the system is used, the micro control unit MCU sends a first instruction to the FPGA chip, the first instruction can be a periodic clock signal or a pulse signal so as to periodically switch the operation modes of the IP core in the functional module, the operation modes comprise a first operation mode and a second operation mode, when the system is applied, the first operation mode can be made to correspond to the high level of the clock signal, the second operation mode corresponds to the low level of the clock signal, when the clock signal is at the high level, the operation mode of the IP core is switched to the first operation mode, and when the clock signal is at the low level, the operation mode of the IP core is switched to the second operation mode. Specifically, the triggering mode of the first instruction is mainly triggered according to a local clock or an external clock, and the triggering mode includes a high level signal and a low level signal. The function module can configure a first operation mode and a second operation mode in advance through a software program, and after the function module obtains a first instruction, the operation mode of the IP core is switched through a preset software program according to a clock high-low level signal.
The first parameter information comprises parameters such as temperature and voltage in the functional module, and the parameters in the functional module cannot be directly acquired by using peripheral equipment (such as a temperature sensor and a voltage sensor), so that when the IP core is in a first operation mode, the device to be detected is inquired and first parameter information is acquired by the micro control unit MCU according to a preset access address of the device to be detected, and then the first parameter information is written into a configured register and fed back to a third device; the second parameter information includes parameters of the device to be tested, such as temperature, voltage, current and the like, and the parameters of the device to be tested can be directly measured by the second devices, such as the temperature sensor, the current sensor, the EEPROM and the like, which are connected with the I2C interface of the functional module, so that when the IP core is in the second operation mode, each peripheral device is queried through the second device through the preset access address of each peripheral device, the state information monitored by each peripheral device is acquired, and second parameter information of the voltage, the current and the like is acquired and fed back to the third device. The third device is preferably a power management module BMC on the server side according to the requirement, and the power management module BMC needs to acquire and manage the state of the device to be tested, such as the accelerator card.
Therefore, the first operation mode and the second operation mode are set for the IP core of the functional module and are periodically switched according to the first instruction, and the detected states are fed back in different operation modes.
In an embodiment, the first device is specifically configured to:
and sending a first instruction to the functional module every preset time length to instruct the IP core to switch the operation mode to the second operation mode, and after the first device feeds back the second parameter information, switching the operation mode to the first operation mode.
In this embodiment, because the influence of the internal parameters of the FPGA chip on the entire FPGA chip is large, the operation mode is initially the first operation mode to monitor the internal state of the FPGA chip in real time, that is, the time length in the first operation mode is long in a period of a preset time length. In this embodiment, the preset duration is preferably the period duration of the clock signal, and if the first operation mode corresponds to the high level of the clock signal, the duration of the clock signal at the high level is longer, and the duration of the clock signal at the low level is shorter. When the operation mode is in the first operation mode, if the clock signal has high and low potential changes, the functional module responds to the potential changes to switch the operation mode from the first operation mode to the second operation mode, and after the functional module feeds back the second parameter information, the operation mode switches the operation mode to the first operation mode again because the time length of the clock signal at the low level is short.
Further, when the operation mode is switched to the second operation mode, the processor may actively read status information monitored by each peripheral device, and send the status information to the power management module BMC through an SMBUS bus (i.e., a low-speed data channel in the figure) of the PCIE interface on the device to be tested, and certainly, the status information may also be sent to the power management module BMC through a high-speed data channel on the PCIE interface.
In an embodiment, the first device is specifically configured to:
monitoring first parameter information in real time, and storing the first parameter information into a register;
correspondingly, when feeding back the first parameter information, the first device is specifically configured to:
and extracting the first parameter information in the register and feeding back the first parameter information.
In this embodiment, if the IP core is in the first operating mode, the first parameter information inside the FPGA chip is stored in the register in real time, and the access request of the power management module BMC is received in real time, and after receiving the second instruction sent by the power management module BMC to obtain the first parameter information, the MCU reads and feeds back the latest first parameter information in the register.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. An information processing method is applied to a device under test configured with a functional module, and comprises the following steps:
based on a first instruction, periodically switching the operation mode of an IP core in the functional module;
if the IP core is in a first operation mode, feeding back first parameter information representing the state of the functional module;
and if the IP core is in a second operation mode, feeding back second parameter information representing the state of the device to be tested.
2. The method of claim 1, the periodically switching the operating mode of the IP cores in the functional module, comprising:
the operation mode is initially the first operation mode;
and switching the operation mode to the second operation mode every preset time, and after feeding back the second parameter information, switching the operation mode to the first operation mode again.
3. The method of claim 1, if the IP core is in a first mode of operation, the method further comprising:
monitoring the first parameter information in real time, and storing the first parameter information into an information base;
correspondingly, the feeding back the first parameter information includes:
and extracting first parameter information in the information base and feeding back the first parameter information.
4. The method of claim 1 or 3, the feeding back first parameter information, comprising:
and receiving and responding to a second instruction to feed back the first parameter information.
5. The method of claim 1, the second parameter information comprising a temperature parameter and a voltage parameter.
6. An information processing apparatus includes a device under test configured with a functional module, a first device, and a second device;
the first device is connected to the functional module in a communication manner and used for sending a first instruction to the functional module so as to periodically switch the operation mode of an IP core in the functional module;
the first device is further configured to feed back first parameter information representing a state of the functional module when the IP core is in a first operating mode;
and the second device is used for feeding back second parameter information representing the state of the device to be tested when the IP core is in a second operation mode.
7. The apparatus of claim 6, the first device to be specifically configured to:
and sending a first instruction to the functional module at intervals of a preset time length to instruct the IP core to switch the operation mode to the second operation mode, and after the first device feeds back the second parameter information, switching the operation mode to the first operation mode.
8. The apparatus of claim 6, the first device to be specifically configured to:
monitoring the first parameter information in real time, and storing the first parameter information into a register;
correspondingly, when feeding back the first parameter information, the first device is specifically configured to:
and extracting first parameter information in the register and feeding back the first parameter information.
9. The apparatus according to claim 6 or 8, wherein the first device, when feeding back the first parameter information, is specifically configured to:
and receiving and responding to a second instruction sent by a third device to acquire the first parameter information and feed back the first parameter information to the third device.
10. The device of claim 9, wherein the first device is a Micro Control Unit (MCU), the second device comprises a temperature sensor and a current sensor, the third device is a power management device (BMC), and the functional module is an FPGA chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110086865.4A CN112765080A (en) | 2021-01-22 | 2021-01-22 | Information processing method and equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110086865.4A CN112765080A (en) | 2021-01-22 | 2021-01-22 | Information processing method and equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112765080A true CN112765080A (en) | 2021-05-07 |
Family
ID=75703649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110086865.4A Pending CN112765080A (en) | 2021-01-22 | 2021-01-22 | Information processing method and equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112765080A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113783762A (en) * | 2021-09-30 | 2021-12-10 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission method, system, storage medium and equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080136641A1 (en) * | 2006-12-06 | 2008-06-12 | Algotronix, Ltd. | Thermal Active Tag for Electronic Designs and Intellectual Property Cores |
| CN103970701A (en) * | 2014-05-28 | 2014-08-06 | 吉林大学 | Field-programmable gate array based real-time synchronous data acquisition intellectual property core |
| CN105760053A (en) * | 2016-02-18 | 2016-07-13 | 联想(北京)有限公司 | Information processing method and electronic equipment |
| CN107506279A (en) * | 2017-08-18 | 2017-12-22 | 江苏微锐超算科技有限公司 | The Properties Control method and device of FPGA device |
| CN207115097U (en) * | 2017-07-19 | 2018-03-16 | 郑州云海信息技术有限公司 | A kind of FPGA isomeries accelerator card |
-
2021
- 2021-01-22 CN CN202110086865.4A patent/CN112765080A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080136641A1 (en) * | 2006-12-06 | 2008-06-12 | Algotronix, Ltd. | Thermal Active Tag for Electronic Designs and Intellectual Property Cores |
| CN103970701A (en) * | 2014-05-28 | 2014-08-06 | 吉林大学 | Field-programmable gate array based real-time synchronous data acquisition intellectual property core |
| CN105760053A (en) * | 2016-02-18 | 2016-07-13 | 联想(北京)有限公司 | Information processing method and electronic equipment |
| CN207115097U (en) * | 2017-07-19 | 2018-03-16 | 郑州云海信息技术有限公司 | A kind of FPGA isomeries accelerator card |
| CN107506279A (en) * | 2017-08-18 | 2017-12-22 | 江苏微锐超算科技有限公司 | The Properties Control method and device of FPGA device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113783762A (en) * | 2021-09-30 | 2021-12-10 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission method, system, storage medium and equipment |
| CN113783762B (en) * | 2021-09-30 | 2023-04-07 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission method, system, storage medium and equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW201227341A (en) | Remote management systems and methods for servers, and computer program products thereof | |
| CN111966189B (en) | Flexibly configured multi-computing-node server mainboard structure and program | |
| US11422960B2 (en) | Interrupt monitoring systems and methods for failure detection for a semiconductor device | |
| CN111198795A (en) | Method and device for acquiring memory temperature by substrate controller | |
| US20060150023A1 (en) | Debugging apparatus | |
| JP2002024201A (en) | Semiconductor integrated circuit | |
| CN115543746A (en) | Graphics processor monitoring method, system and device and electronic equipment | |
| CN112765080A (en) | Information processing method and equipment | |
| CN117707884A (en) | Method, system, equipment and medium for monitoring power management chip | |
| US20230367508A1 (en) | Complex programmable logic device and communication method | |
| CN115543759A (en) | Log lookup method and device for operating system, electronic device and storage medium | |
| CN107066421B (en) | Oscilloscope and collected data reporting method thereof | |
| CN115994057A (en) | Chip bus detection method and device, electronic equipment and storage medium | |
| CN112100023B (en) | Board card information acquisition method and device for heterogeneous acceleration platform | |
| CN108880916B (en) | IIC bus-based fault positioning method and system | |
| CN112953788A (en) | Network state detection method and device, BMC and storage medium | |
| CN112154419A (en) | Performance monitoring device and method, system on chip, movable platform and camera | |
| CN113010336A (en) | Application processor crash field debugging method and application processor | |
| CN111367885A (en) | Database management system, database management method, storage medium, and electronic device | |
| CN116577551B (en) | SSD power consumption testing method and system and electronic equipment | |
| CN118012661B (en) | Test alarm monitoring device, method and test machine | |
| CN113466566B (en) | Trigger type signal acquisition method and device | |
| CN113282441B (en) | Hardware running state data acquisition method and hardware detection equipment | |
| CN118152201A (en) | Method and device for testing operation performance of hardware equipment | |
| CN113052996A (en) | Data recording apparatus and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |