CN103956382A - 一种沟槽功率器件结构及其制造方法 - Google Patents

一种沟槽功率器件结构及其制造方法 Download PDF

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CN103956382A
CN103956382A CN201410165169.2A CN201410165169A CN103956382A CN 103956382 A CN103956382 A CN 103956382A CN 201410165169 A CN201410165169 A CN 201410165169A CN 103956382 A CN103956382 A CN 103956382A
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power device
reticle
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孙效中
沈志伟
吴江
郑迎新
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CHANGZHOU WANGTONG SEMICONDUCTOR TECHNOLOGY Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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Abstract

本发明公开了一种沟槽功率器件结构及其制造方法，其中沟槽功率器件结构，包括有源区和终端两部分结构，有源区最***一圈沟槽开始直到器件边缘，沟槽设于第一层光刻版上，第二层光刻版上设有LOCOS区域，第二层光刻版上设有接触孔，第四层光刻版上设有源极与栅极；本发明采取沟槽隔离与LOCOS相结合。本发明基于各种终端结构的优点，使得本发明的工艺简单，成本低廉，占用面积非常少且具有很宽的电压适应范围等优点。

Description

一种沟槽功率器件结构及其制造方法
技术领域
本发明涉及半导体器件及其制造方法技术领域，尤其是一种沟槽功率器件结构及其制造方法。
背景技术
目前，金属氧化物半导体场效应管(MOSFET)，绝缘栅双极晶体管(IGBT)，沟槽金属势垒肖特基二极管(TMBS)以及超势垒二极管(SBD)等是几种最为重要的功率器件。在工业电子，家电业以及消费电子诸领域都有它们的用武之地。开关电源电路，整流电路以及驱动电路中都离不开它们的身影。功率器件要求正向大电流，反向大电压。自从功率器件发明起，提高其反向耐压能力就成为一个重要课题。
功率器件的耐压能力由两部分组成：一是有源区耐压，二是终端耐压，其中任何一方耐压不够，就没办法满足要求。有源区的耐压问题相对比较简单，只要选择合适的材料与工艺就能实现。而终端耐压则不然，它不仅与材料和工艺有关，还和器件的终端结构有关，所以需要做特殊处理。如图1为不做任何改进的终端结构，由于等势面弯曲，电场汇集，抬高局部电场，致使耐压降低。于是便出现了很多新结构以提高终端耐压能力，比如：LOCOS结构，分压环结构，场板结构及沟槽隔离结构等等。以上所提及的改进结构，其基本思路无外乎增大等势面曲率半径，以达到降低表面电场或结电场的作用。
如今，人们采取以上所述的终端结构或其中几个的组合结构，设计出许多符合要求的功率器件。但总体来讲，每个终端结构都有其优点，又有其不足。比如分压环结构的优点是工艺相对简单，而缺点是占用面积大及受环境影响较大，需要覆盖保护层；如图2所示的为沟槽隔离结构利用电场终止于沟槽侧壁的原理以达到提高耐压的目的，此方法在100V以下器件是可行的，因为电压较低，耗尽层不会绕过沟槽底部而往外延伸，但随着电压的加大，耗尽层也跟着往下扩展，就会有绕过沟槽的风险，为了解决这个风险，只有加深沟槽，这样同时会带来沟槽底部容易过早击穿问题，如此便形成了沟槽底部击穿与P-N结击穿无法同时满足的问题，所以沟槽隔离只可以适用与低于100V产品。
发明内容
本发明专利的发明目的在于：避免现有技术的不足，提供一种沟槽功率器件结构及其制造方法。
为实现上述目的，本发明采取的技术方案为：包括有源区和终端两部分结构，其中，有源区最***一圈沟槽开始直到器件边缘，沟槽设于第一层光刻版上，第二层光刻版上设有LOCOS区域，第二层光刻版上设有接触孔，第四层光刻版上设有源极与栅极。
进一步，所述的采取沟槽隔离与LOCOS相结合。
进一步，所述的第四层光刻版为金属层。
本发明还提供一种沟槽功率器件结构的制造方法，其步骤如下：
步骤一，选择合适的材料利用第一层光刻版形成沟槽，淀积或热过程生长一层氮化硅；
步骤二，利用第二层光刻版开出LOCOS区域，去除LOCOS区域的氮化硅，用化学或物理过程长热氧化层；
步骤三，再把未打开区域的氮化硅去除，长栅氧，淀积多晶硅，多晶硅回刻到原材料硅表面，体区注入与推进，源区注入与推进；
步骤四，淀积隔离层，利用第三光刻版开孔，孔刻蚀；
步骤五，淀积金属，利用第四层光刻版形成源极与栅极。
综上所述，由于采用了上述技术方案，本发明的有益效果是：
1、基于各种终端结构的优点，使得本发明的工艺简单，成本低廉，占用面积非常少且具有很宽的电压适应范围等优点。
2、相同条件下，采取沟槽隔离与LOCOS相结合的结构比传统结构的漏电低至少一个数量级。
3、耐压能力更强，相同条件下，传统技术在34V击穿，而采取沟槽隔离与LOCOS相结合后到40V击穿。
4、终端尺寸小，10um的终端就能实现30V耐压，而传统技术要实现同等性能，尺寸至少为40um，所以采取沟槽隔离与LOCOS相结合的技术仅占仅占传统的1/4，甚至可以做到更小。
附图说明
图1是做任何改进的终端结构；
图2是沟槽隔离只可以适用于低于100V的产品结构；
图3是采取沟槽隔离与LOCOS相结合的计算结果图；
图4是分压环技术终端击穿计算曲线；
图5是MOSFET单管俯视图；
图6是第一层光刻版，有源区与终端沟槽形成图；
图7是第二层光刻版，LOCOS结构形成图；
图8是去除氮化硅，仅剩***的氧化层图；
图9是沟槽内形成栅氧与栅多晶；
图10是源区与体区形成图；
图11是源、栅接触孔形成图；
图12是图五B-B切向剖面图。
图中标记：1-源极金属层，2-栅极金属层，3-隔离层氧化物，4-多晶，5-接触孔，6-栅氧，7-沟槽一，8-沟槽二，9-场氧，10-。
具体实施方式
下面结合附图，对本发明专利作详细的说明。
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
如图5、图12所示，本发明沟槽功率器件包括有源区和终端两部分(以一种功率器件MOSFET为例)，其中，有源区最***一圈沟槽开始直到器件边缘，沟槽设于第一层光刻版上，第二层光刻版上设有LOCOS区域，第二层光刻版上设有接触孔，第四层光刻版上设有源极与栅极。
进一步，所述的采取沟槽隔离与LOCOS相结合。
进一步，所述的第四层光刻版为金属层。
本发明还提供一种沟槽功率器件结构的制造方法，其步骤如下：
步骤一，选择合适的材料利用第一层光刻版形成沟槽，淀积或热过程生长一层氮化硅；
步骤二，利用第二层光刻版开出LOCOS区域，去除LOCOS区域的氮化硅，用化学或物理过程长热氧化层；
步骤三，再把未打开区域的氮化硅去除，长栅氧，淀积多晶硅，多晶硅回刻到原材料硅表面，体区注入与推进，源区注入与推进；
步骤四，淀积隔离层，利用第三光刻版开孔，孔刻蚀；
步骤五，淀积金属，利用第四层光刻版形成源极与栅极。
方案一，图5为MOSFET或IGBT的单管俯视图，图中有一个切面，B-B。，B-B的完整剖面如图12示。下面重点分析B-B的形成过程，从图6到图11分别详述如下。
图6：N型基片，晶向<100>，淀积或热过程生长2000A-20000A的氧化层作为硬掩膜，第一层光刻，形成沟槽图形，硬掩膜湿法或干法刻蚀到基片表面，沟槽干法刻蚀，底部圆滑刻蚀，湿法或干法完全去除硬掩膜。
图7：通过淀积或热过程生长200A-20000A的氮化硅，第二层光刻，把从隔离沟槽内侧到器件边缘的氮化硅全部去除，热过程生长2000A-20000A的氧化层。
图8：通过湿法或干法全部刻蚀掉有源区的氮化硅。
图9：热过程长50A-3000A的栅氧，淀积多晶硅，多晶硅回刻到与沟槽表面水平位置。
图10：体区注入与推进，源区注入与推进。
图11：淀积或热过程生长2000A-20000A的氧化层作为隔离层，通过第三层光刻形成接触孔区域，湿法或干法刻蚀隔离层到基片表面，干法刻蚀基片0.3um-1um。
图12：蒸发或溅射1um-5um金属层作为电极层，第四层光刻版定义栅、源极区域，通过湿法或干法把金属层刻开。最终形成如图12所示的结构。
其中上述在沟槽刻蚀时，利用沟槽刻蚀的负载效应，根据沟槽尺寸大小不同，有意使***的沟槽刻蚀得深些，有源区中沟槽刻蚀得浅些，这样***的沟槽能更好的阻断电场，有源区沟槽形成满足要求的MOSFET基本单元。从电场终止沟槽往外算起，由于沟槽内生长了一层很厚的氧化层，后续的体注入，源注入都不会穿过，致使体、源注入的区域终止于截至沟槽的内侧，如此一来电场只存在于截至沟槽的内侧，而不会往外延伸，再加上P-N是垂直于沟槽侧壁的，也就不存在电场汇集等现象了，达到有效提高耐压能力的目的。从截至沟槽往外算起，沟槽底部都长有厚氧化层，可以有效抗压，氧化层的厚度可以根据抗压的大小而调整厚度。原则上讲，这种***结构可以把电压做到无穷大，而占用器件的面积又非常小。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (5)

1.一种沟槽功率器件结构，包括有源区和终端两部分结构，其特征在于，有源区最***一圈沟槽开始直到器件边缘，沟槽设于第一层光刻版上，第二层光刻版上设有LOCOS区域，第二层光刻版上设有接触孔，第四层光刻版上设有源极与栅极。
2.根据权利要求1所述沟槽功率器件结构，其特征在于：采取沟槽隔离与LOCOS相结合。
3.根据权利要求1所述沟槽功率器件结构，其特征在于：第四层光刻版为金属层。
4.根据权利要求1所述沟槽功率器件结构的制造方法，其特征在于：步骤一，选择合适的材料利用第一层光刻版形成沟槽，淀积或热过程生长一层氮化硅；步骤二，利用第二层光刻版开出LOCOS区域，去除LOCOS区域的氮化硅，用化学或物理过程长热氧化层；步骤三，再把未打开区域的氮化硅去除，长栅氧，淀积多晶硅，多晶硅回刻到原材料硅表面，体区注入与推进，源区注入与推进；步骤四，淀积隔离层，利用第三光刻版开孔，孔刻蚀；步骤五，淀积金属，利用第四层光刻版形成源极与栅极。
5.根据权利要求4所述沟槽功率器件结构的制造方法，其特征在于：在沟槽刻蚀时，利用沟槽刻蚀的负载效应，根据沟槽尺寸大小不同，有意使***的沟槽刻蚀得深些，有源区中沟槽刻蚀得浅些。
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