CN103944660A - Clock synchronization device and method - Google Patents
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- CN103944660A CN103944660A CN201310019630.9A CN201310019630A CN103944660A CN 103944660 A CN103944660 A CN 103944660A CN 201310019630 A CN201310019630 A CN 201310019630A CN 103944660 A CN103944660 A CN 103944660A
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Abstract
The invention provides a clock synchronization device and method. The method is applied to the clock synchronization device which comprises a clock source radio frequency front end device and radio frequency front end devices to be synchronized. The method includes the step of system initialization, the step of exchanging clock values between the clock source radio frequency front end device and the radio frequency front end devices to be synchronized, the step of processing data and generating a correction value through the radio frequency front end devices to be synchronized and the step of correcting the local clocks through the radio frequency front end devices to be synchronized according to the correction value. According to the clock synchronization device and method, the clock signal of the clock source radio frequency front end device is used for correcting the clock signals of the radio frequency front end devices to be synchronized, so that time synchronization between the radio frequency front end devices is achieved with low cost and high precision.
Description
Technical field
The present invention relates to the Time synchronization technique in a kind of software radio, particularly relate to a kind of clock synchronization device and method.
Background technology
Along with the variation of people's demand and the development of the communication technology, there is various radio communication standards and corresponding communication equipment, in order to meet the intercommunication problem of equipment, shorten the construction cycle, reduce development cost, people have proposed the concept of software radio.The core concept of software radio is that one of structure has open, standardized, modular general hardware platform, and various communication functions are realized on this hardware platform by software.Because hardware platform can constantly be upgraded along with the development of device, the mode that simultaneously can change software by increasing realizes new communication function, and the concept of software radio is subject to extensive concern.The concept of virtual radio is that the people such as V.Bose in 1999 propose, and its target is to replace dedicated devices to complete the digital signal processing in radio communication with the computing capability of all-purpose computer.Compared with software radio based on Special Purpose Programmable device architectures, virtual radio electric system has that development cost is low, the cycle is short, upgrading is quick, the feature of flexible configuration, can support the wireless network of existing various modes, can also design and support following network schemer by expansion.It is the software radio of " software implementation " more.
In virtual radio electric system, require each composition module time synchronized.At present mainly adopt and in system, set clock source, realize synchronously by the mode of tranmitting data register synch command, but because there is propagation delay time, treat that the lock in time that lock unit receives is not accurate enough, and for example, based on bus (high-speed PCI E bus) though propagation delay time neither a determined value between two fixing nodes, visible this synchronous method precision is not high enough.
Also there is at present a kind of high-precision Time Synchronizing, but this scheme need to arrange the synchronizer such as GPS receiver, for treating that to each of system lock unit passes through special circuit and sends lock in time, make eachly to treat that lock unit can receive accurate lock in time; Changing scheme can also all arrange GPS receiver in treating lock unit each, treat that lock unit completes exact time synchronization by GPS receiver, but cost is higher.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of clock synchronization device and method, for solving prior art clock source and treating between synchronizer the problems such as the not high enough and cost of synchronization accuracy is higher.
For achieving the above object and other relevant objects, the invention provides a kind of clock synchronization device, comprising: clock source radio frequency front-end device, it comprises: the first clock source, provides system reference clock signal pulse; The first clock register, the system reference clock signal pulse providing according to described clock source produces local reference clock; Time data generator, the low level of the described local reference clock of lasting acquisition current time, and according to default frequency generation time data; Time data bag sending module, continues to collect described time data, and the time data of collection is sent to target device reaching Preset Time interval; Packet receives feedback module, in order to receive to time request data package, and send feedback data packet to target device after default time interval; And treat synchronous radio frequency front-end device, it comprises: second clock source, provides local adjustable clock signal pulse; Second clock register, the local adjustable clock signal pulse providing according to described second clock source produces local clock value; Data packet transceive module, in order in the time receiving the time data that described time data bag sending module sends, send to time request data package to described clock source radio-frequency front-end equipment, and the moment of transmission is recorded as to the first local clock value, and receive the feedback data packet that described packet reception feedback module feeds back, and the moment of reception is recorded as to the second local clock value; Measure generator time calibration, read the time data of described data packet transceive module reception and first, second local clock value of record, calculate clock frequency correcting value and local clock correcting value and calibrate described second clock source and second clock register.
Preferably, measuring generator described time calibration comprises: collecting unit, continue to read the time data of described data packet transceive module reception and first, second local clock value of record, and according to Preset Time interval, the repeatedly time data reading is packaged into time data collection, and repeatedly first, second local clock value of record is packaged into the first local clock value collection and the second local clock value collection; Clock frequency correction amount calculating unit, calculate differing from and obtaining the first difference collection of described the first local clock value collection and described time data collection, the average that captures multiple differences of described the first difference converges minimum and calculate the plurality of difference is the first average, the first average of statistics preset times is stored as the first average collection, calculate the difference of current the first average and the first average collection, and carry out filtering and process acquisition clock frequency correcting value; Local clock correction amount calculating unit, calculate differing from and obtaining the second difference collection of described the second local clock value collection and described the first local clock value collection, the average that captures multiple differences of described the second difference converges minimum and calculate the plurality of difference is the second average, described the second average is carried out to filtering and process acquisition filter value, calculate 1/2nd of described filter value and obtain described local clock correcting value; And correcting unit, calibrate described second clock source and second clock register according to the described clock frequency correcting value and the local clock correcting value that calculate.
The present invention also provides a kind of clock synchronizing method, be applied to and include clock source radio frequency front-end device and treat in the clock synchronization device of synchronous radio frequency front-end device, comprise the following steps: system initialization, the raw time interval of the transmission time interval of the bit wide of Preset Time data, the frequency of system reference clock signal pulse, time data and time adjustment volume production; Described clock source radio frequency front-end device continues the low level of local reference clock of acquisition current time, and according to default frequency generation time data, and treats synchronous radio frequency front-end device described in the time data of collection is sent to reaching Preset Time interval; Described send in the time receiving the time data of transmission until synchronous radio frequency front-end device to time request data package to described clock source radio-frequency front-end equipment, and the moment of transmission is recorded as to the first local clock value; Described clock source radio frequency front-end device receive to time request data package, and after default time interval, send feedback data packet to described in treat synchronous radio frequency front-end device; The described feedback data packet for the treatment of synchronous radio frequency front-end device reception feedback, and the moment of reception is recorded as to the second local clock value; And described in treat that synchronous radio frequency front-end device reads first, second local clock value of time data and record, calculate the local clock for the treatment of synchronous radio frequency front-end device described in the calibration of clock frequency correcting value and local clock correcting value.
Preferably, the described method that calculates clock frequency correcting value and local clock correcting value comprises the following steps: first, second local clock value that continues to read time data and record, and according to Preset Time interval, the repeatedly time data reading is packaged into time data collection, and repeatedly first, second local clock value of record is packaged into the first local clock value collection and the second local clock value collection; Calculate differing from and obtaining the first difference collection of described the first local clock value collection and described time data collection, the average that captures multiple differences of described the first difference converges minimum and calculate the plurality of difference is the first average, the first average of statistics preset times is stored as the first average collection, calculate the difference of current the first average and the first average collection, and carry out filtering and process acquisition clock frequency correcting value; Simultaneously, calculate differing from and obtaining the second difference collection of described the second local clock value collection and described the first local clock value collection, the average that captures multiple differences of described the second difference converges minimum and calculate the plurality of difference is the second average, described the second average is carried out to filtering and process acquisition filter value, calculate 1/2nd of described filter value and obtain described local clock correcting value; And according to the local clock for the treatment of synchronous radio frequency front-end device described in the described clock frequency correcting value calculating and the calibration of local clock correcting value.
As mentioned above, clock synchronization device of the present invention and method, used the clock signal calibration of clock source radio-frequency front-end equipment to treat the clock signal of synchronous radio-frequency front-end equipment, can low cost, and the high-precision time synchronized realizing between radio-frequency front-end equipment.Brief description of the drawings
Fig. 1 is shown as the composition frame chart of clock synchronization device of the present invention.
Fig. 2 is shown as the theory diagram of clock synchronization device of the present invention.
Fig. 3 is shown as the theory diagram of measuring generator in clock synchronization device of the present invention time calibration.
Fig. 4 is shown as the flow chart of clock synchronizing method of the present invention.
Fig. 5 be shown as clock synchronizing method of the present invention in the flow chart of concrete calibration.
Element numbers explanation
1 clock source radio frequency front-end device
11 first clock sources
12 first clock registers
13 time data generators
14 time data bag sending modules
15 packets receive feedback module
16 first bus ports
2 treat synchronous radio frequency front-end device
21 second clock sources
22 second clock registers
23 data packet transceive modules
Measure generator 24 time calibrations
241 collecting units
242 clock frequency correction amount calculating unit
243 local clock correction amount calculating unit
244 correcting units
25 second bus ports
S1 ~ S6 step
S61 ~ S63 step
Embodiment
Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
It should be noted that, the diagram providing in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy and only show with assembly relevant in the present invention in graphic but not component count, shape and size drafting while implementing according to reality, when its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
Embodiment mono-
Refer to Fig. 1 and Fig. 2, Fig. 1 is shown as the composition frame chart of clock synchronization device of the present invention, Fig. 2 is shown as the theory diagram of clock synchronization device of the present invention, as shown in the figure, the invention provides a kind of clock synchronization device, comprise: clock source radio frequency front-end device 1, and at least onely treat synchronous radio frequency front-end device 2.In actual embodiment, described clock source radio frequency front-end device 1 by bus with described in radio frequency front-end device 2 to be synchronizeed connect, particularly, described clock source radio frequency front-end device 1 also comprises the first bus port 16, describedly treat that synchronous radio frequency front-end device 2 also comprises the second bus end 25, described the first bus port 16 is connected to described the second bus port 25 by bus, and described bus 3 is for example PCIE bus, Hyper Transport bus or Intel QuickPath Interconnect bus.In the present embodiment, described clock source radio frequency front-end device 1 by high-speed PCI E bus 3 with described in radio frequency front-end device 2 to be synchronizeed connect.
It should be noted that, set forth for convenience principle of the present invention and effect, in embodiment described later, treat that taking a clock source radio frequency front-end device and one synchronous radio frequency front-end device describes as example temporarily.
Described clock source radio frequency front-end device 1 comprises: the first clock source 11, the first clock registers 12, and time data generator 13, time data bag sending module 14, and packet receives feedback module 15.
Described the first clock source 11 provides system reference clock signal pulse; In the present embodiment, the system reference clock signal pulse that for example frequency is 100MHz.
The system reference clock signal pulse that described the first clock register 12 provides according to described clock source produces local reference clock; In the present embodiment, the system reference clock signal pulse that the first clock register 12 provides according to described clock source produces the local reference clock of 64bits.
Described time data generator 13 continues the low level of the described local reference clock of acquisition current time, and according to default frequency generation time data; In the present embodiment, described time data generator 13 continues the low level of the described local reference clock of acquisition current time, and every 10 to 10000 local pulse reference clocks produce a time data, for example, described time data generator 13 produces the time data t0 that length is 32bits, time data generator 13 by the time interval of specifying be for example every 100 clock pulse once, intercept the low 32bits of reference clock position, current time this locality as time data t0.
Described time data bag sending module 14 continues to collect described time data, and the time data of collection is sent to target device reaching Preset Time interval; In the present embodiment, described time data bag sending module continues to collect described time data, and every 10 to 10000 the local pulse reference clocks of time data of collecting are sent once to target device, and described target device is for treating synchronous radio frequency front-end device 2.For example, described in described time data bag sending module 14 is sent to time data t0 by high-speed PCI E bus 3, treat synchronous radio frequency front-end device 2, the transmission time interval of described time data t0 is that every 100 local pulse reference clocks send once.
Described packet receive feedback module 15 in order to receive to time request data package, and send feedback data packet to target device after default time interval; In the present embodiment, described packet receive feedback module 15 receive to time request data package after 10 to 10000 local pulse reference clocks often send feedback data packet to described in treat synchronous radio frequency front-end device 2.For example, described packet receive feedback module 15 receive to time request data package after every 100 local pulse reference clocks send feedback data packet to described in treat synchronous radio frequency front-end device 2.
Describedly treat synchronous radio frequency front-end device 2, it comprises: second clock source 21, and second clock register 22, data packet transceive module 23, and measure generator 24 time calibration.
Described second clock source 21 provides local adjustable clock signal pulse; In the present embodiment, the local adjustable clock signal pulse that described second clock source 21 provides, be for example 100MHz clock signal, wherein the frequency of clock signal pulse can be adjusted according to clock frequency correcting value T1, and the initial frequency errors in described second clock source 21 is generally less than 50ppm.
The local adjustable clock signal pulse that described second clock register 22 provides according to described second clock source 21 produces local clock value; In the present embodiment, the local adjustable clock signal pulse that described second clock register 22 provides according to described second clock source 21 produces 64bits local clock value.
Described data packet transceive module 23 in order in the time receiving the time data that described time data bag sending module 14 sends, send to time request data package to described clock source radio-frequency front-end equipment, and the moment of transmission is recorded as to the first local clock value, and receive the feedback data packet that described packet reception feedback module 15 feeds back, and the moment of reception is recorded as to the second local clock value; In the present embodiment, the first local clock value is designated as t1, and the second local clock value is designated as t2.Described data packet transceive module 23 is by high-speed PCI E bus 3 time of reception data t0, receive after time information data t0, send immediately to time request data package to clock source radio-frequency front-end equipment, and record the first local clock value t1 of delivery time, but also receiving the second local clock value of the feedback data packet of clock source radio-frequency front-end equipment feedback, record is designated as t2.
Measure generator 24 described time calibration and read time data that described data packet transceive module 23 receives and first, second local clock value of record, calculate clock frequency correcting value and local clock correcting value and calibrate described second clock source 21 and second clock register 22.Refer to Fig. 3, be shown as the theory diagram of measuring generator in clock synchronization device of the present invention time calibration, as shown in the figure, in the present embodiment, measuring generator 24 described time calibration comprises: collecting unit 241, clock frequency correction amount calculating unit 242, local clock correction amount calculating unit 243, and correcting unit 244.
Described collecting unit 241 continues to read time data that described data packet transceive module 23 receives and first, second local clock value of record, and according to Preset Time interval, the repeatedly time data reading is packaged into time data collection, and repeatedly first, second local clock value of record is packaged into the first local clock value collection and the second local clock value collection, described collecting unit 241 continues to read first of time data that described data packet transceive module 23 receives and record, the second local clock value, and according to Preset Time interval, 10 to 10000 time datas that read are packaged into time data collection, and by 10 to 10000 times first of record, the second local clock value is packaged into the first local clock value collection and the second local clock value collection, for example, described collecting unit 241 continues to read time data t0 that described data packet transceive module 23 receives and the first local clock value t1 of record, the second local clock value t2, and according to Preset Time interval, 100 time datas that read are packaged into time data collection [t0], and by 100 the first local clock value t1 of record, the second local clock value t2 is packaged into the first local clock value collection [t1] and the second local clock value collection [t2].
Described clock frequency correction amount calculating unit 242 is calculated differing from of described the first local clock value collection and described time data collection and is obtained the first difference collection, the average that captures multiple differences of described the first difference converges minimum and calculate the plurality of difference is the first average, the first average of statistics preset times is stored as the first average collection, calculate the difference of current the first average and the first average collection, and carry out filtering and process acquisition clock frequency correcting value.In the present embodiment, described clock frequency correction amount calculating unit 242 is calculated differing from of described the first local clock value collection and described time data collection and is obtained the first difference collection, capturing multiple differences of described the first difference converges minimum and calculating the plurality of difference is the first difference subset, and the average of calculating this first difference subset is the first average, first average of adding up 1 to 10000 time is stored as the first average collection, calculate the difference of current the first average and the first average collection, and carry out filtering and process acquisition clock frequency correcting value.
For example, described clock frequency correction amount calculating unit 242 is calculated differing from of described the first local clock value collection [t1] and described time data collection [t0] and is obtained the first difference collection ([t1]-[t0]), capturing 16 differences minimum in described the first difference collection ([t1]-[t0]) and calculating these 16 differences is the first difference subset, and to calculate this be that the average of the first difference subset of 16 differences is the first average X, the the first average X that adds up 10 times is stored as the first average collection Z, the difference of calculating current the first average X and the first average collection Z is designated as W, i.e. (X-Z)/10000=W, and carry out filtering and process acquisition clock frequency correcting value.More specifically, in an embodiment, select first order IIR low pass filter, filter coefficient gets 0.01, and W is carried out to filtering, and filtering is output as U, finally exports U as clock frequency correcting value T1.So, be not limited to this, in practice, can choose different parameters according to the synchronous stage, for example starting stage, treat that the frequency difference between synchronous radio-frequency front-end equipment and clock source radio-frequency front-end equipment is very large, at this moment can choose less R, K, L, larger filter coefficient; After frequency is basicly stable, for synchronous precision, can select larger R, K, L, and less filter coefficient.
Described local clock correction amount calculating unit 243 is calculated differing from of described the second local clock value collection and described the first local clock value collection and is obtained the second difference collection, the average that captures multiple differences of described the second difference converges minimum and calculate the plurality of difference is the second average, described the second average is carried out to filtering and process acquisition filter value, calculate 1/2nd of described filter value and obtain described local clock correcting value.
In the present embodiment, described local clock correction amount calculating unit 243 is calculated differing from of described the second local clock value collection and described the first local clock value collection and is obtained the second difference collection, the multiple differences that capture described the second difference converges minimum are the second difference subset, and the average of calculating this second difference subset is the second average, described the second average is carried out to filtering and process acquisition filter value, calculate 1/2nd of described filter value and obtain described local clock correcting value.
For example, described local clock correction amount calculating unit 243 is calculated differing from of described the second local clock value collection [t2] and described the first local clock value collection [t1] and is obtained the second difference collection ([t2]-[t1]), capturing 16 differences minimum in described the second difference collection ([t2]-[t1]) is the second difference subset, and to calculate this be that the average of 16 differences of the second difference subset is the second average Y, described the second average Y is carried out to filtering and process acquisition filter value V, calculate 1/2nd of described filter value V, be V/2, obtain described local clock correcting value T2.More specifically, in an embodiment, select first order IIR low pass filter, filter coefficient gets 0.01, and described the second average Y is carried out to filtering processing, calculates 1/2nd of described filter value V, i.e. V/2 obtains described local clock correcting value T2.So, be not limited to this, in practice, can choose different parameters according to the synchronous stage, for example starting stage, treat that the frequency difference between synchronous radio-frequency front-end equipment and clock source radio-frequency front-end equipment is very large, at this moment can choose less R, K, L, larger filter coefficient; After frequency is basicly stable, for synchronous precision, can select larger R, K, L, and less filter coefficient.
Described correcting unit 244 is calibrated described second clock source 21 and second clock register 22 according to the described clock frequency correcting value and the local clock correcting value that calculate.Particularly, the described clock frequency correcting value T1 and the local clock correcting value T2 that calculate calibrate described second clock source 21 and second clock register 22, to treat the local clock of synchronous radio frequency front-end device 2 described in calibrating.
Embodiment bis-
Refer to Fig. 4, be shown as the flow chart of clock synchronizing method of the present invention, as shown in the figure, the invention provides a kind of clock synchronizing method, be applied to and include clock source radio frequency front-end device 1 and treat in the clock synchronization device of synchronous radio frequency front-end device 2, in actual embodiment, described clock source radio frequency front-end device 1 by bus 3 with described in radio frequency front-end device 2 to be synchronizeed connect, particularly, described clock source radio frequency front-end device 1 also comprises the first bus port 16, describedly treat that synchronous radio frequency front-end device 2 also comprises the second bus port 25, described the first bus port 16 is connected to described the second bus port 25 by bus, described bus is for example PCIE bus, Hyper Transport bus, or Intel QuickPath Interconnect bus.In the present embodiment, described clock source radio frequency front-end device 1 by high-speed PCI E bus 3 with described in radio frequency front-end device 2 to be synchronizeed connect.
Described clock synchronizing method comprises the following steps:
S1: system initialization, the raw time interval of the transmission time interval of the bit wide of Preset Time data, the frequency of system reference clock signal pulse, time data and time adjustment volume production; In the present embodiment, in system initialization, fixed time data bit width is 32bits; System reference clock signal pulse frequency is 100MHz; The transmission time interval of time data is that every 100 pulse reference clocks send once; The life of time adjustment volume production is spaced apart 100 time information datas of every reception and produces once.
S2: described clock source radio frequency front-end device 1 continues the low level of the local reference clock of acquisition current time, and according to default frequency generation time data, and described in being sent to, the time data of collection treats synchronous radio frequency front-end device 2 reaching Preset Time interval; In the present embodiment, described clock source radio frequency front-end device 1 continues the low level of the local reference clock of acquisition current time, and every 10 to 10000 local pulse reference clocks produce a time data, and by every the time data of collection 10 to 10000 local pulse reference clocks send once to described in treat synchronous radio frequency front-end device.For example, described clock source radio frequency front-end device 1 continues the low level of the local reference clock of acquisition current time, and every 100 local pulse reference clocks produce a time data, and by every the time data of collection 100 local pulse reference clocks send once to described in treat synchronous radio frequency front-end device 2.
For example, described clock source radio frequency front-end device 1 produces the time data t0 that length is 32bits, time data generator 13 by the time interval of specifying be for example every 100 clock pulse once, intercept the low 32bits of reference clock position, current time this locality as time data t0.Described clock source radio frequency front-end device 1 is treated synchronous radio frequency front-end device 2 described in time data t0 being sent to by high-speed PCI E bus 3, and the transmission time interval of described time data t0 is that every 100 local pulse reference clocks send once.
S3: described in send in the time receiving the time data of transmission until synchronous radio frequency front-end device 2 to time request data package to described clock source radio-frequency front-end equipment, and the moment of transmission is recorded as to the first local clock value; In the present embodiment, the first local clock value is designated as t1, describedly treat that synchronous radio frequency front-end device 2 is by high-speed PCI E bus 3 time of reception data t0, receive after time information data t0, send immediately to time request data package to clock source radio-frequency front-end equipment, and record the first local clock value t1 of delivery time.
S4: described clock source radio frequency front-end device 1 receive to time request data package, and after default time interval, send feedback data packet to described in treat synchronous radio frequency front-end device 2; For example, described clock source radio frequency front-end device 1 receive to time request data package after every 100 local pulse reference clocks send feedback data packet to described in treat synchronous radio frequency front-end device 2.
S5: described in treat that synchronous radio frequency front-end device 2 receives the feedback data packet of feedback, and the moment of reception is recorded as to the second local clock value; In the present embodiment, the second local clock value is designated as t2.Describedly treat that synchronous radio frequency front-end device 2 receives the feedback data packet of feedback by high-speed PCI E bus 3, and the second local clock value that record receives the feedback data packet of clock source radio-frequency front-end equipment feedback is designated as t2.
S6: described in treat that synchronous radio frequency front-end device 2 reads first, second local clock value of time data and record, calculate the local clock for the treatment of synchronous radio frequency front-end device 2 described in the calibration of clock frequency correcting value and local clock correcting value.
Refer to Fig. 5, be shown as clock synchronizing method of the present invention in the flow chart of concrete calibration, as shown in the figure, in the present embodiment, the described method that calculates clock frequency correcting value and local clock correcting value comprises the following steps:
S61: first, second local clock value that continues to read time data and record, and according to Preset Time interval, the repeatedly time data reading is packaged into time data collection, and repeatedly first, second local clock value of record is packaged into the first local clock value collection and the second local clock value collection; In the present embodiment, described resuming studies got first, second local clock value of time data and record, and according to Preset Time interval, 10 to 10000 time datas that read are packaged into time data collection, and 10 to 10000 first, second local clock values of record are packaged into the first local clock value collection and the second local clock value collection.For example, described the first local clock value t1 that continues to read time data t0 and record, the second local clock value t2, and according to Preset Time interval, 100 time datas that read are packaged into time data collection [t0], and 100 the first local clock value t1, the second local clock value t2 of record are packaged into the first local clock value collection [t1] and the second local clock value collection [t2].
S62: calculate differing from and obtaining the first difference collection of described the first local clock value collection and described time data collection, the average that captures multiple differences of described the first difference converges minimum and calculate the plurality of difference is the first average, the first average of statistics preset times is stored as the first average collection, calculate the difference of current the first average and the first average collection, and carry out filtering and process acquisition clock frequency correcting value.In the present embodiment, the differing from and obtain the first difference collection of described the first local clock value collection of described calculating and described time data collection, the multiple differences that capture described the first difference converges minimum are the first difference subset, and to calculate this be that the average of the first difference subset is the first average, first average of adding up 1 to 10000 time is stored as the first average collection, calculate the difference of current the first average and the first average collection, and carry out filtering and process acquisition clock frequency correcting value.
Particularly, in step S62, calculate differing from and obtaining the first difference collection ([t1]-[t0]) of described the first local clock value collection [t1] and described time data collection [t0], capturing 16 differences minimum in described the first difference collection ([t1]-[t0]) is the first difference subset, and to calculate this be that the average of 16 differences of the first difference subset is the first average X, the the first average X that adds up 10 times is stored as the first average collection Z, the difference of calculating current the first average X and the first average collection Z is designated as W, i.e. (X-Z)/10000=W, and carry out filtering and process acquisition clock frequency correcting value.More specifically, in an embodiment, select first order IIR low pass filter, filter coefficient gets 0.01, and W is carried out to filtering, and filtering is output as U, finally exports U as clock frequency correcting value T1.So, be not limited to this, in practice, can choose different parameters according to the synchronous stage, for example starting stage, treat that the frequency difference between synchronous radio-frequency front-end equipment and clock source radio-frequency front-end equipment is very large, at this moment can choose less R, K, L, larger filter coefficient; After frequency is basicly stable, for synchronous precision, can select larger R, K, L, and less filter coefficient.
Simultaneously, calculate differing from and obtaining the second difference collection of described the second local clock value collection and described the first local clock value collection, the average that captures multiple differences of described the second difference converges minimum and calculate the plurality of difference is the second average, described the second average is carried out to filtering and process acquisition filter value, calculate 1/2nd of described filter value and obtain described local clock correcting value.In the present embodiment, the differing from and obtain the second difference collection of described the second local clock value collection of described calculating and described the first local clock value collection, capture multiple differences of described the second difference converges minimum for being the second difference subset, and the average of calculating this second difference subset is the second average, described the second average is carried out to filtering and process acquisition filter value, calculate 1/2nd of described filter value and obtain described local clock correcting value.
Particularly, in step S62, calculate differing from and obtaining the second difference collection ([t2]-[t1]) of described the second local clock value collection [t2] and described the first local clock value collection [t1], capturing 16 differences minimum in described the second difference collection ([t2]-[t1]) is the second difference subset, and to calculate this be that the average of 16 differences of the second difference subset is the second average Y, described the second average Y is carried out to filtering and process acquisition filter value V, calculate 1/2nd of described filter value V, be V/2, obtain described local clock correcting value T2.More specifically, in an embodiment, select first order IIR low pass filter, filter coefficient gets 0.01, and described the second average Y is carried out to filtering processing, calculates 1/2nd of described filter value V, i.e. V/2 obtains described local clock correcting value T2.So, be not limited to this, in practice, can choose different parameters according to the synchronous stage, for example starting stage, treat that the frequency difference between synchronous radio-frequency front-end equipment and clock source radio-frequency front-end equipment is very large, at this moment can choose less R, K, L, larger filter coefficient; After frequency is basicly stable, for synchronous precision, can select larger R, K, L, and less filter coefficient.
S63: according to the local clock for the treatment of synchronous radio frequency front-end device 2 described in the described clock frequency correcting value calculating and the calibration of local clock correcting value.Particularly, described in the described clock frequency correcting value T1 calculating and local clock correcting value T2 calibration, treat the local clock of synchronous radio frequency front-end device 2.
In sum, clock synchronization device of the present invention and method, used the clock signal calibration of clock source radio-frequency front-end equipment to treat the clock signal of synchronous radio-frequency front-end equipment, can low cost, and the high-precision time synchronized realizing between radio-frequency front-end equipment.So the present invention has effectively overcome various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and conventionally know that the knowledgeable, not departing from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.
Claims (12)
1. a clock synchronization device, is characterized in that, comprising:
Clock source radio frequency front-end device, it comprises:
The first clock source, provides system reference clock signal pulse;
The first clock register, the system reference clock signal pulse providing according to described clock source produces local reference clock;
Time data generator, the low level of the described local reference clock of lasting acquisition current time, and according to default frequency generation time data;
Time data bag sending module, continues to collect described time data, and the time data of collection is sent to target device reaching Preset Time interval;
Packet receives feedback module, in order to receive to time request data package, and send feedback data packet to target device after default time interval; And
Treat synchronous radio frequency front-end device, it comprises:
Second clock source, provides local adjustable clock signal pulse;
Second clock register, the local adjustable clock signal pulse providing according to described second clock source produces local clock value;
Data packet transceive module, in order in the time receiving the time data that described time data bag sending module sends, send to time request data package to described clock source radio-frequency front-end equipment, and the moment of transmission is recorded as to the first local clock value, and receive the feedback data packet that described packet reception feedback module feeds back, and the moment of reception is recorded as to the second local clock value;
Measure generator time calibration, read the time data of described data packet transceive module reception and first, second local clock value of record, calculate clock frequency correcting value and local clock correcting value and calibrate described second clock source and second clock register.
2. clock synchronization device according to claim 1, it is characterized in that: described clock source radio frequency front-end device also comprises the first bus port, describedly treat that synchronous radio frequency front-end device also comprises the second bus port, described the first bus port is connected to described the second bus port by bus.
3. clock synchronization device according to claim 2, is characterized in that: described bus is PCIE bus, Hyper Transport bus or Intel QuickPath Interconnect bus.
4. clock synchronization device according to claim 1, is characterized in that: measure generator described time calibration and comprise:
Collecting unit, continue to read the time data of described data packet transceive module reception and first, second local clock value of record, and according to Preset Time interval, the repeatedly time data reading is packaged into time data collection, and repeatedly first, second local clock value of record is packaged into the first local clock value collection and the second local clock value collection;
Clock frequency correction amount calculating unit, calculate differing from and obtaining the first difference collection of described the first local clock value collection and described time data collection, the average that captures multiple differences of described the first difference converges minimum and calculate the plurality of difference is the first average, the first average of statistics preset times is stored as the first average collection, calculate the difference of current the first average and the first average collection, and carry out filtering and process acquisition clock frequency correcting value;
Local clock correction amount calculating unit, calculate differing from and obtaining the second difference collection of described the second local clock value collection and described the first local clock value collection, the average that captures multiple differences of described the second difference converges minimum and calculate the plurality of difference is the second average, described the second average is carried out to filtering and process acquisition filter value, calculate 1/2nd of described filter value and obtain described local clock correcting value;
Correcting unit, calibrates described second clock source and second clock register according to the described clock frequency correcting value and the local clock correcting value that calculate.
5. clock synchronization device according to claim 4, it is characterized in that: described clock frequency correction amount calculating unit is calculated differing from of described the first local clock value collection and described time data collection and obtained the first difference collection, capturing multiple differences of described the first difference converges minimum and calculating the plurality of difference is the first difference subset, and the average of calculating this first difference subset is the first average, statistics the first average is repeatedly stored as the first average collection, calculate the difference of current the first average and the first average collection, and carry out filtering and process acquisition clock frequency correcting value.
6. clock synchronization device according to claim 4, it is characterized in that: described local clock correction amount calculating unit is calculated differing from of described the second local clock value collection and described the first local clock value collection and obtained the second difference collection, the multiple differences that capture described the second difference converges minimum are the second difference subset, and the average of calculating this second difference subset is the second average, described the second average is carried out to filtering and process acquisition filter value, calculate 1/2nd of described filter value and obtain described local clock correcting value.
7. a clock synchronizing method, is applied to include clock source radio frequency front-end device and treat and, in the clock synchronization device of synchronous radio frequency front-end device, it is characterized in that, comprises the following steps:
System initialization, the raw time interval of the transmission time interval of the bit wide of Preset Time data, the frequency of system reference clock signal pulse, time data and time adjustment volume production;
Described clock source radio frequency front-end device continues the low level of local reference clock of acquisition current time, and according to default frequency generation time data, and treats synchronous radio frequency front-end device described in the time data of collection is sent to reaching Preset Time interval;
Described send in the time receiving the time data of transmission until synchronous radio frequency front-end device to time request data package to described clock source radio-frequency front-end equipment, and the moment of transmission is recorded as to the first local clock value;
Described clock source radio frequency front-end device receive to time request data package, and after default time interval, send feedback data packet to described in treat synchronous radio frequency front-end device;
The described feedback data packet for the treatment of synchronous radio frequency front-end device reception feedback, and the moment of reception is recorded as to the second local clock value; And
Describedly treat that synchronous radio frequency front-end device reads first, second local clock value of time data and record, calculate the local clock for the treatment of synchronous radio frequency front-end device described in clock frequency correcting value and the calibration of local clock correcting value.
8. clock synchronizing method according to claim 7, is characterized in that: described clock source radio frequency front-end device by bus with described in radio frequency front-end device to be synchronizeed connect.
9. clock synchronizing method according to claim 8, is characterized in that: described bus is PCIE bus, HyperTransport bus or Intel QuickPath Interconnect bus.
10. clock synchronizing method according to claim 7, is characterized in that: the described method that calculates clock frequency correcting value and local clock correcting value comprises the following steps:
Continue to read first, second local clock value of time data and record, and according to Preset Time interval, the repeatedly time data reading is packaged into time data collection, and repeatedly first, second local clock value of record is packaged into the first local clock value collection and the second local clock value collection;
Calculate differing from and obtaining the first difference collection of described the first local clock value collection and described time data collection, the average that captures multiple differences of described the first difference converges minimum and calculate the plurality of difference is the first average, the first average of statistics preset times is stored as the first average collection, calculate the difference of current the first average and the first average collection, and carry out filtering and process acquisition clock frequency correcting value; Simultaneously, calculate differing from and obtaining the second difference collection of described the second local clock value collection and described the first local clock value collection, the average that captures multiple differences of described the second difference converges minimum and calculate the plurality of difference is the second average, described the second average is carried out to filtering and process acquisition filter value, calculate 1/2nd of described filter value and obtain described local clock correcting value; And
According to the local clock for the treatment of synchronous radio frequency front-end device described in the described clock frequency correcting value calculating and the calibration of local clock correcting value.
11. clock synchronizing methods according to claim 10, it is characterized in that: the differing from and obtain the first difference collection of described the first local clock value collection of described calculating and described time data collection, the multiple differences that capture described the first difference converges minimum are the first difference subset, and to calculate this be that the average of the first difference subset is the first average, statistics the first average is repeatedly stored as the first average collection, calculate the difference of current the first average and the first average collection, and carry out filtering and process acquisition clock frequency correcting value.
12. clock synchronizing methods according to claim 10, it is characterized in that: the differing from and obtain the second difference collection of described the second local clock value collection of described calculating and described the first local clock value collection, the multiple differences that capture described the second difference converges minimum are the second difference subset, and the average of calculating this second difference subset is the second average, described the second average is carried out to filtering and process acquisition filter value, calculate 1/2nd of described filter value and obtain described local clock correcting value.
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