CN103943085B - The driving method that a kind of gate driver circuit, display unit and subregion show - Google Patents
The driving method that a kind of gate driver circuit, display unit and subregion show Download PDFInfo
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- CN103943085B CN103943085B CN201410130951.0A CN201410130951A CN103943085B CN 103943085 B CN103943085 B CN 103943085B CN 201410130951 A CN201410130951 A CN 201410130951A CN 103943085 B CN103943085 B CN 103943085B
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Abstract
The driving method that the embodiment of the present invention provides a kind of gate driver circuit, display unit and subregion to show, in order to reduce the power consumption of existing display unit this display unit in the time that user only needs the content of the some viewing areas demonstration that will see display unit. Wherein, each shifting deposit unit in gate driver circuit can be in the time that the first control signal received in the first control signal termination of self be high level, the gate line that self is connected and low level signal termination are logical, thereby after the gate line that makes to connect at this shifting deposit unit, the gate line of scanning can not be strobed again.
Description
Technical field
The present invention relates to Display Technique field, relate in particular to a kind of gate driver circuit, display unit and subregionThe driving method that territory shows.
Background technology
TFT-LCD (ThinFilmTransistor-LiquidCrystalDisplay, TFT liquidCrystal display) general principle that realizes a frame picture disply is to drive successively from top to bottom by grid (gate)Square wave to every one-row pixels input certain width carries out gating, then drives each by source electrode (source)The signal output from top to bottom successively that row pixel is required. At present, the display floater of a kind of like this structure of manufacture is logicalBe often by gate driver circuit and source electrode drive circuit by COF (ChipOnFilm covers brilliant film) orCOG (ChipOnGlass, chip is directly fixed on glass) technique is produced on glass substrate, but works asWhen resolution ratio is higher, the output of grid driving and source drive is all more, and the length of drive circuit also will increase,This will be unfavorable for binding (Bonding) technique of module drive circuit.
In order to overcome above problem, the manufacture of existing display floater often adopts GOA (GateDriveonArray)The design of circuit, than traditional COF or COG technique, this has not only saved cost, and canAccomplish the design for aesthetic of panel both sides symmetry, the Bonding region of simultaneously also having saved gate driver circuit withAnd peripheral wiring space, thereby realize the design of the narrow frame of display unit, improve the production capacity of display unitAnd yield.
But display unit is in the time adopting above-mentioned display floater, shows and all will drive on display floater each timeEach pixel all shows, this in some cases, as user only needs to see the some of display unitViewing area show content (for example user only need to see display unit show time) time, increasedThe power consumption of display unit.
Summary of the invention
The driving side that the embodiment of the present invention provides a kind of gate driver circuit, display unit and subregion to showMethod, only needs to see some viewing areas of display unit user in order to reduce existing display unitShow content time this display unit power consumption.
Based on the problems referred to above, a kind of gate driver circuit that the embodiment of the present invention provides, comprises that N displacement postDeposit receipt unit;
The forward selection signal end of p shifting deposit unit receives p-j shifting deposit unit outputSignal, p=j+1 ... .N, first shifting deposit unit is to each displacement in j shifting deposit unitThe forward of deposit unit is selected the signal end mutually different original trigger signal of received bit respectively;
The reverse selection signal end of r shifting deposit unit receives r+j shifting deposit unit outputSignal, r=1,2 ... N-j, N-j+1 shifting deposit unit is to each in N shifting deposit unitThe reverse selection signal end of the shifting deposit unit mutually different gating end signal of received bit respectively;
The clock signal terminal of k shifting deposit unit receives mod ((k-1)/(2*j))+1 clock signal,K=1,2 ..., N; J is positive integer;
The control signal termination of each shifting deposit unit is received the first control signal, each shifting deposit unitForward scan signal end receives the first level signal, and the reverse scan signal end of each shifting deposit unit receivesSecond electrical level signal, the low level signal termination of each shifting deposit unit is received low level signal;
When the first level signal is high level signal, second electrical level signal is low level signal; The first level letterWhile number being low level signal, second electrical level signal is high level signal;
Each shifting deposit unit is low electricity for the first control signal of receiving in the first control signal terminationFlat and just/while oppositely selecting signal that signal end receives to be high level, by just/reverse scan signal terminationThe high level signal of receiving charges to this transistor to the transistorized grid of driving grid line in selfStable unlatching; After the stable unlatching of this transistor, by the clock signal output receiving by clock signal terminal;The first control signal of receiving in the first control signal termination is that low level and anti-/ forward select signal end to receiveTo signal while being high level, with anti-/ low level signal that forward scan signal end receives to driving in selfThe transistorized grid of gate line is discharged to this transistor and closes; And receive in the first control signal terminationTo the first control signal while being high level, the gate line that self is connected leads to low level signal termination.
A kind of display unit that the embodiment of the present invention provides, comprises that the grid that the embodiment of the present invention provides drives electricityRoad.
The driving method that subregion that the embodiment of the present invention provides shows, is applied to that the embodiment of the present invention providesGate driver circuit, comprising:
Determine the gate line that the pixel in the region that needs to show in display floater connects;
Control described gate driver circuit and carry out present frame scanning, the last j bar grid in definite gate lineWhen each gate line gating in polar curve finishes, control each shift LD list in described gate driver circuitThe first control signal that the control signal termination of unit is received is high level, until described gate driver circuit startsWhile carrying out next frame scanning, control the control signal of each shifting deposit unit in described gate driver circuitThe first control signal that termination is received is low level.
The driving method that subregion that the embodiment of the present invention provides shows, is applied to that the embodiment of the present invention providesGate driver circuit, comprising:
Determine the gate line that the pixel in the region that needs to show in display floater connects;
Determine described gate driver circuit forward scan, for the initial j bar grid in definite gate lineIn each shifting deposit unit in the described gate driver circuit that each gate line in line connects oneShifting deposit unit, controls the forward of this shifting deposit unit and selects signal end to receive original trigger signal; PinThe described grid that each gate line except initial j bar gate line in definite gate line connected drivesA shifting deposit unit in each shifting deposit unit in moving circuit, controls this shifting deposit unitForward selects signal end to receive the signal of this shifting deposit unit j shifting deposit unit output before;Each displacement in the described gate driver circuit connecting for each gate line in definite gate line is postedA shifting deposit unit in deposit receipt unit, connects second at the reverse selection signal end of this shifting deposit unitSelect when circuit, after the reverse selection signal end of controlling this shifting deposit unit receives this shifting deposit unitThe signal of j shifting deposit unit output, connect at the reverse selection signal end of this shifting deposit unitWhen second switch circuit, control the second switch circuit of the reverse selection signal end connection of this shifting deposit unitClosed;
Determine described gate driver circuit reverse scan, for the initial j bar grid in definite gate lineIn each shifting deposit unit in the described gate driver circuit that each gate line in line connects oneShifting deposit unit, the reverse selection signal end of controlling this shifting deposit unit receives gating end signal; PinThe described grid that each gate line except initial j bar gate line in definite gate line connected drivesA shifting deposit unit in each shifting deposit unit in moving circuit, controls this shifting deposit unitOppositely select signal end to receive the signal of this shifting deposit unit j shifting deposit unit output afterwards;Each displacement in the described gate driver circuit connecting for each gate line in definite gate line is postedA shifting deposit unit in deposit receipt unit, selects signal end to connect first at the forward of this shifting deposit unitSelect when circuit, the forward of controlling this shifting deposit unit is selected before signal end receives this shifting deposit unitThe signal of j shifting deposit unit output, select signal end to connect at the forward of this shifting deposit unitWhen the first on-off circuit, the forward of controlling this shifting deposit unit is selected the first on-off circuit of signal end connectionClosed;
Control described gate driver circuit and carry out present frame scanning, the last j bar grid in definite gate lineWhen each gate line gating in polar curve finishes, control each shift LD list in described gate driver circuitThe first control signal that the control signal termination of unit is received is high level, until described gate driver circuit startsWhile carrying out next frame scanning, control the control signal of each shifting deposit unit in described gate driver circuitThe first control signal that termination is received is low level.
The beneficial effect of the embodiment of the present invention comprises:
The driving method that gate driver circuit, display unit and the subregion that the embodiment of the present invention provides shows,Because the each shifting deposit unit in gate driver circuit is received in the first control signal termination of selfWhen the first control signal is high level, gate line and the low level signal termination that self can be connected are logical, therebyAfter the gate line that makes to connect at this shifting deposit unit, the gate line of scanning can not be strobed again, namelySay, the display unit that adopts this gate driver circuit only pixel in control section viewing area shows,This,, in the time that user only needs the content of the some viewing areas demonstration that will see display unit, can reduce aobviousThe power consumption of showing device.
Brief description of the drawings
One of structural representation of the gate driver circuit that Fig. 1 a provides for the embodiment of the present invention;
Two of the structural representation of the gate driver circuit that Fig. 1 b provides for the embodiment of the present invention;
Three of the structural representation of the gate driver circuit that Fig. 2 a provides for the embodiment of the present invention;
Four of the structural representation of the gate driver circuit that Fig. 2 b provides for the embodiment of the present invention;
The driving method that the subregion that Fig. 3 provides for the embodiment of the present invention shows is applied to Fig. 1 a or Fig. 1 bFlow chart when shown gate driver circuit;
The driving method that the subregion that Fig. 4 provides for the embodiment of the present invention shows is applied to Fig. 2 a or Fig. 2 bFlow chart when shown gate driver circuit.
Detailed description of the invention
The driving method that gate driver circuit, display unit and the subregion that the embodiment of the present invention provides shows,Because the each shifting deposit unit in gate driver circuit is received in the first control signal termination of selfWhen the first control signal is high level, gate line and the low level signal termination that self can be connected are logical, therebyAfter the gate line that makes to connect at this shifting deposit unit, the gate line of scanning can not be strobed again, and this makesWhen user only needs the content of the some viewing areas demonstration that will see display unit, can reduce display unitPower consumption.
Below in conjunction with Figure of description, a kind of gate driver circuit, demonstration dress that the embodiment of the present invention is providedThe detailed description of the invention of putting the driving method showing with subregion describes.
A kind of gate driver circuit that the embodiment of the present invention provides, comprises N shifting deposit unit;
The forward selection signal end of p shifting deposit unit receives p-j shifting deposit unit outputSignal, p=j+1 ... .N, first shifting deposit unit is to each displacement in j shifting deposit unitThe forward of deposit unit is selected the signal end mutually different original trigger signal of received bit respectively;
The reverse selection signal end of r shifting deposit unit receives r+j shifting deposit unit outputSignal, r=1,2 ... N-j, N-j+1 shifting deposit unit is to each in N shifting deposit unitThe reverse selection signal end of the shifting deposit unit mutually obstructed gating end signal of received bit respectively;
The clock signal terminal of k shifting deposit unit receive mod ((k-1)/h)+1 clock signal,K=1,2 ..., N; H is more than or equal to 2*j, and j is positive integer; Wherein, ((k-1)/h) (k-1) got in expression to modThe remainder of/h;
For example, j=2, h=2*j=4, in the time of k=1, mod ((k-1)/h)+1=1, therefore, post by first displacementThe clock signal terminal of deposit receipt unit receives the 1st clock signal; In the time of k=2, mod ((k-1)/h)+1=2, therefore,The clock signal terminal of second shifting deposit unit receives the 2nd clock signal; In the time of k=3,((k-1)/h)+1=3, therefore, the clock signal terminal of the 3rd shifting deposit unit receives the 3rd clock letter to modNumber; In the time of k=4, and mod ((k-1)/h)+1=4, therefore, the clock signal terminal of the 4th shifting deposit unitReceive the 4th clock signal; In the time of k=5, and mod ((k-1)/h)+1=1, therefore, the 5th shift LD listThe clock signal terminal of unit receives the 1st clock signal; In the time of k=6, mod ((k-1)/h)+1=2, therefore, theThe clock signal terminal of six shifting deposit units receives the 2nd clock signal, etc.
The control signal termination of each shifting deposit unit is received the first control signal, each shifting deposit unitForward scan signal end receives the first level signal, and the reverse scan signal end of each shifting deposit unit receivesSecond electrical level signal, the low level signal termination of each shifting deposit unit is received low level signal;
The first level signal is high level signal, and when second electrical level signal is low level signal, described grid drivesMoving circuit forward scan; The first level signal is low level signal, when second electrical level signal is high level signal,Described gate driver circuit reverse scan;
In the time of described gate driver circuit forward scan, each shifting deposit unit, for believing in the first controlThe first control signal that number termination is received is that low level and forward select signal that signal end receives (Beginning triggering signal, or the signal of this shifting deposit unit j shifting deposit unit output before)During for high level, the crystalline substance of the high level signal receiving with forward scan signal end to driving grid line in selfThe grid of body pipe charges to the stable unlatching of this transistor; After the stable unlatching of this transistor, will pass through timeThe clock signal output that clock signal end receives; The first control signal of receiving in the first control signal termination isLow level and oppositely to select the signal that signal end receives (be gating end signal, or this displacement is postedThe signal that j shifting deposit unit after deposit receipt unit exported) while being high level, use reverse scan signalThe low level signal that termination is received is discharged to this crystalline substance to the transistorized grid of driving grid line in selfBody pipe is closed; And the first control signal of receiving in the first control signal termination is while being high level, by selfThe gate line connecting and low level signal termination are logical;
In the time of described gate driver circuit reverse scan, each shifting deposit unit, for believing in the first controlThe first control signal that number termination is received is low level and signal (the i.e. choosing of oppositely selecting signal end to receiveLogical end signal, or the signal of this shifting deposit unit j shifting deposit unit output afterwards)During for high level, the crystalline substance of the high level signal receiving with reverse scan signal end to driving grid line in selfThe grid of body pipe charges to the stable unlatching of this transistor; After the stable unlatching of this transistor, will pass through timeThe clock signal output that clock signal end receives; The first control signal of receiving in the first control signal termination isThe signal that low level and forward select signal end to receive (be original trigger signal, or this displacement is postedThe signal that j shifting deposit unit before deposit receipt unit exported) while being high level, use forward scan signalThe low level signal that termination is received is discharged to this crystalline substance to the transistorized grid of driving grid line in selfBody pipe is closed; And the first control signal of receiving in the first control signal termination is while being high level, by selfThe gate line connecting and low level signal termination are logical.
Work as j=1, when h=2, the structure of the gate driver circuit that the embodiment of the present invention provides as shown in Figure 1a.In the gate driver circuit shown in Fig. 1 a, in the time that m is odd number, m shifting deposit unit SRmClock signal terminal CLKIN receive the first clock signal clk 1, in the time that m is even number, m displacementThe clock signal terminal CLKIN of deposit unit SRm receives second clock signal CLK2, wherein, and first o'clockClock signal CLK1 and the complementation of second clock signal, when the first clock signal is high level, second clock letterNumber be low level, when the first clock signal is low level, second clock signal is high level.
In the gate driver circuit shown in Fig. 1 a, the forward of first shifting deposit unit SR1 is selected letterNumber end CHOFIN receives original trigger signal STV, except first shifting deposit unit SR1 respectivelyThe forward of individual shifting deposit unit selects signal end CHOFIN to receive the defeated of its previous shifting deposit unitGo out to hold the signal of OUTPUT output; The reverse selection signal termination of N shifting deposit unit SRNReceive gating end signal CF, each shifting deposit unit except N shifting deposit unit SRNReverse selection signal end CHOBIN to receive the output OUTPUT of a shifting deposit unit thereafter defeatedThe signal going out; The control signal end GCIN of each shifting deposit unit receives the first control signal GC1, everyThe forward scan signal VFIN termination of individual shifting deposit unit is received the first level signal V1, each shift LDThe reverse scan signal end VBIN of unit receives second electrical level signal V2, each shifting deposit unit lowLevel signal end VGLIN receives low level signal VGL.
Work as j=2, when h=4, the structure of the gate driver circuit that the embodiment of the present invention provides as shown in Figure 1 b,In the gate driver circuit shown in Fig. 1 a, the clock signal terminal CLKIN of k shifting deposit unit SRkReceive mod ((k-1)/4)+1 clock signal, wherein, when the first clock signal clk 1 is high level, theThree clock signal clks 3 are low level, when the 3rd clock signal clk 3 is high level, and the first clock signalCLK1 is low level; When second clock signal CLK2 is high level, the 4th clock signal clk 4 is lowLevel, when the 4th clock signal clk 4 is high level, second clock signal CLK2 is low level.
In the gate driver circuit shown in Fig. 1 b, the forward of first shifting deposit unit SR1 is selected letterNumber end CHOFIN receive the first original trigger signal STV1, the forward of second shifting deposit unit SR2Select signal end CHOFIN to receive the second original trigger signal STV2, wherein, the first original trigger signalSTV1 is two mutually different pulse signals of position with the second original trigger signal STV2, except first displacementThe forward choosing of each shifting deposit unit beyond deposit unit SR1 and second shifting deposit unit SR2Select the output OUTPUT output that signal end CHOFIN receives second shifting deposit unit before itSignal; The reverse selection signal end of N shifting deposit unit SRN receives the first gating end signalCF1, the reverse selection signal end of N-1 shifting deposit unit SRN receives the second gating end signalCF2, each except N shifting deposit unit SRN and N-1 shifting deposit unit SRN-1The reverse selection signal end CHOBIN of individual shifting deposit unit receives its second shifting deposit unit afterwardsThe signal of output OUTPUT output; The control signal end GCIN of each shifting deposit unit receivesThe first control signal GC1, the forward scan signal VFIN termination of each shifting deposit unit is received the first levelSignal V1, the reverse scan signal end VBIN of each shifting deposit unit receives second electrical level signal V2,The low level signal end VGLIN of each shifting deposit unit receives low level signal VGL.
Certainly, j also can get other value, for example, j=4, now, gate driver circuit will receive 8 notSame clock signal, 4 original trigger signal that position is mutually different, 4 gating end signals that position is mutually different,And receive the first control signal, the first level signal, second electrical level signal and low level signal.
Preferably, in the gate driver circuit that the embodiment of the present invention provides, also comprise the first selection circuit, secondSelect circuit, the first on-off circuit and second switch circuit;
The forward of p shifting deposit unit selects signal end to select circuit to receive p-j by one firstThe signal of individual shifting deposit unit output, this first selects circuit also to receive that ((p-1)/j)+1 is moved with modThe identical signal of signal that the forward of position deposit unit selects signal end to receive;
This first selection circuit, selects signal end receiving for controlling the forward of p shifting deposit unitThe signal of p-j shifting deposit unit output, and receive and mod ((p-1)/j)+1 shifting deposit unitForward select to switch between signal that the signal that receives of signal end is identical;
First shifting deposit unit is to the forward of each shifting deposit unit in j shifting deposit unitSelect signal end to receive an original trigger signal by a first different on-off circuit respectively;
Each the first on-off circuit, selects signal for the forward of controlling the shifting deposit unit being connected with selfWhether end receives original trigger signal;
The reverse selection signal end of r shifting deposit unit selects circuit to receive r+j by one secondThe signal of individual shifting deposit unit output, this second selection circuit also receives ((r-1)/j) individual displacement with N-modThe identical signal of signal that the reverse selection signal end of deposit unit receives;
This second selection circuit, is receiving for the reverse selection signal end of controlling r shifting deposit unitThe signal of r+j shifting deposit unit output, and receive and N-mod ((r-1)/j) individual shifting deposit unitThe identical signal of the signal that receives of reverse selection signal end between switch;
N-j+1 shifting deposit unit is to each shifting deposit unit in N shifting deposit unitOppositely select signal end to receive a gating end signal by a different second switch circuit respectively;
Each second switch circuit, for controlling the reverse selection signal of the shifting deposit unit being connected with selfWhether end receives gating end signal.
Select circuit, first when comprising the first selection circuit, second in the gate driver circuit shown in Fig. 1 aWhen on-off circuit and second switch circuit, its structure as shown in Figure 2 a. In Fig. 2 a with the first selection circuitSW1, second selects circuit SW2 to be the gate-controlled switch of single-pole double throw, the first on-off circuit SW3 and theThe gate-controlled switch that two on-off circuit SW4 are single-pole single-throw(SPST is that example describes, and certainly, first selects electricityRoad and second selects circuit also can adopt other forms, is receiving two kinds of different signals as long as can realizeBetween switch, the first on-off circuit and second switch circuit also can adopt other forms, as long as canRealize and receiving signal and do not receiving switching between signal. Therefore, post by controlling with first displacementThe second selection circuit SW2 that the reverse selection signal end CHOBIN of the SR1 of deposit receipt unit is connected, can controlThe reverse selection signal end CHOBIN of first shifting deposit unit SR1 is receiving second shift LDThe signal of the output OUTPUT output of cell S R2, and switch between reception gating end signal CF;By controlling and the forward selection signal end CHOFIN of N shifting deposit unit SRN is connected firstSelect circuit SW1, can control the forward of N shifting deposit unit SRN and select signal end CHOFINThe signal of exporting at the output OUTPUT that receives N-1 shifting deposit unit SRN-1, and receiveBetween original trigger signal STV, switch. Select by controlling with the forward of first shifting deposit unit SR1Select the first on-off circuit SW3 that signal end CHOFIN is connected, can control first shifting deposit unitThe forward of SR1 selects signal end CHOFIN whether to receive original trigger signal STV; By controlling and NThe connected second switch circuit SW4 of reverse selection signal end CHOBIN of individual shifting deposit unit SRN,Whether the reverse selection signal end CHOBIN that can control N shifting deposit unit SRN receives gatingEnd signal CF.
Select circuit, first when comprising the first selection circuit, second in the gate driver circuit shown in Fig. 1 bWhen on-off circuit and second switch circuit, its structure as shown in Figure 2 b. In Fig. 2 b with the first selection circuitSW1, second selects circuit SW2 to be the gate-controlled switch of single-pole double throw, the first on-off circuit SW3 and theThe gate-controlled switch that two on-off circuit SW4 are single-pole single-throw(SPST is that example describes, and certainly, first selects electricityRoad and second selects circuit also can adopt other forms, is receiving two kinds of different signals as long as can realizeBetween switch, the first on-off circuit and second switch circuit also can adopt other forms, as long as canRealize and receiving signal and do not receiving switching between signal. In Fig. 2 b, N is odd number. Therefore,By control be connected with the reverse selection signal end CHOBIN of first shifting deposit unit SR1 secondSelect circuit SW2, can control the reverse selection signal end CHOBIN of first shifting deposit unit SR1The signal of exporting at the output OUTPUT that receives the 3rd shifting deposit unit SR3, and receive firstBetween gating end signal CF1, switch; Reverse choosing by control with second shifting deposit unit SR2Select the second selection circuit SW2 that signal end CHOBIN is connected, can control second shifting deposit unitThe reverse selection signal end CHOBIN of SR2 is receiving the output of the 4th shifting deposit unit SR3The signal of OUTPUT output, and switch between reception the second gating end signal CF2; By control withThe first selection circuit that the forward of N shifting deposit unit SRN selects signal end CHOFIN to be connectedSW1, can control the forward of N shifting deposit unit SRN and select signal end CHOFIN receivingThe signal of the output OUTPUT output of N-2 shifting deposit unit SRN-2, and receive at the beginning of firstBetween beginning triggering signal STV1, switch. Select by controlling with the forward of first shifting deposit unit SR1The first on-off circuit SW3 that signal end CHOFIN is connected, can control first shifting deposit unit SR1Forward select signal end CHOFIN whether to receive the first original trigger signal STV1; By controlling and theThe first on-off circuit SW3 that the forward of two shifting deposit unit SR2 selects signal end CHOFIN to be connected,Can control the forward of second shifting deposit unit SR2 selects signal end CHOFIN whether to receive secondOriginal trigger signal STV2; Believe by controlling with the reverse selection of N-1 shifting deposit unit SRN-1Number end CHOBIN connected second switch circuit SW4, can control N-1 shifting deposit unitWhether the reverse selection signal end CHOBIN of SRN-1 receives the second gating end signal CF2; By controlThe second switch electricity that system is connected with the reverse selection signal end CHOBIN of N shifting deposit unit SRNWhether road SW4, can control the reverse selection signal end CHOBIN of N shifting deposit unit SRNReceive the first gating end signal CF1.
The structure of the shifting deposit unit in the gate driver circuit that the embodiment of the present invention provides is not limit, as long as energyEnough realize the pieces of data line on the display floater in gating display unit successively.
The embodiment of the present invention also provides a kind of display unit, comprises that the grid that the embodiment of the present invention provides drives electricityRoad.
The driving method that subregion that the embodiment of the present invention provides shows, is applied to that the embodiment of the present invention providesGate driver circuit, as shown in Figure 3, comprising:
S301, determine the gate line that the pixel in the region that needs in display floater to show connects;
S302, control described gate driver circuit and carry out present frame scanning, last in definite gate lineWhen each gate line gating in j bar gate line finishes, control each displacement in described gate driver circuitThe first control signal that the control signal termination of deposit unit is received is high level, controls described grid and drivesThe gate line that each shifting deposit unit in circuit connects receives low level signal, until described grid drivesCircuit starts to carry out next frame when scanning, controls each shifting deposit unit in described gate driver circuitThe first control signal that control signal termination is received is low level, controls each in described gate driver circuitThe gate line that individual shifting deposit unit connects no longer receives low level signal.
Taking the structure of the gate driver circuit shown in Fig. 1 a as example (j=1), first determine in display floater and needThe gate line that pixel in the region showing connects is h article of gate line to the N-h article grid in display floaterPolar curve, h is less than N/2. In the time of gate driver circuit forward scan shown in Fig. 1 a, h article of gate line extremelyThe last item gate line in N-h article of gate line is N-h article of gate line, the grid shown in control chart 1aThe present frame scanning that utmost point drive circuit carries out, in the time that N-h article of gate line gating finishes, controls display floaterIn each gate line receive low level signal, until under the gate driver circuit shown in Fig. 1 a starts to carry outWhen one frame scan, the grid that each shifting deposit unit in the gate driver circuit shown in control chart 1a connectsPolar curve no longer receives low level signal. Therefore, in the time of forward scan, when the pixel in the region that needs show connectsWhen the gate line connecing is h article of gate line to the N-h article of gate line in display floater, gate driver circuitThe gate line of actual scanning is Article 1 gate line to the N-h bar gate line in display floater. When grid drivesWhen moving circuit reverse scan, the last item gate line in h article of gate line to the N-h article gate line is theH bar gate line, the present frame scanning that the gate driver circuit shown in control chart 1a carries out, at h article of gridWhen the logical end of line selection, each the gate line of controlling in display floater receives low level signal, until Fig. 1 a instituteWhen the gate driver circuit showing starts to carry out next frame scanning, in the gate driver circuit shown in control chart 1aThe gate line that connects of each shifting deposit unit no longer receive low level signal. Therefore, in the time of reverse scan,The gate line connecting when the pixel in the region that needs show is h article of gate line to the N-h in display floaterWhen bar gate line, the gate line of gate driver circuit actual scanning be h article of gate line in display floater extremelyN article of gate line.
Taking the structure of the gate driver circuit shown in Fig. 2 a as example (j=2), first determine in display floater and needThe gate line that pixel in the region showing connects is h article of gate line to the N-h article grid in display floaterPolar curve, h is less than N/2. In the time of gate driver circuit forward scan shown in Fig. 2 a, h article of gate line extremelyLast j article of gate line in N-h article of gate line is N-h-1 article of gate line and N-h article of gate line,The present frame scanning that gate driver circuit shown in control chart 2a carries out, at N-h-1 article of gate line gatingWhen end and N-h article of gate line gating finish, each the gate line of controlling in display floater receives low levelSignal, until the gate driver circuit shown in Fig. 2 a starts to carry out next frame when scanning, shown in control chart 2aGate driver circuit in the gate line that connects of each shifting deposit unit no longer receive low level signal. CauseThis, in the time of forward scan, the gate line connecting when the pixel in the region that needs show is the in display floaterWhen h article of gate line to the N-h bar gate line, the gate line of gate driver circuit actual scanning is display floaterIn Article 1 gate line to the N-h bar gate line. In the time of gate driver circuit reverse scan, h article of gridLast j article of gate line in polar curve to the N-h article gate line is h article of gate line and h+1 article of gate line,The present frame scanning that gate driver circuit shown in control chart 2a carries out, finishes at h article of gate line gatingAnd when h+1 article of gate line gating finishes, each the gate line of controlling in display floater receives low level signal,Until the gate driver circuit shown in Fig. 2 a starts to carry out next frame when scanning, the grid shown in control chart 2aThe gate line that each shifting deposit unit in drive circuit connects no longer receives low level signal. Therefore, existWhen reverse scan, the gate line connecting when the pixel in the region that needs show is h article of grid in display floaterWhen polar curve to the N-h bar gate line, the gate line of gate driver circuit actual scanning is in display floaterH article of gate line to the N bar gate line.
Preferably, a displacement in each shifting deposit unit connecting for described definite gate line is postedDeposit receipt unit, in the time that described definite gate line need to be by gating successively, this shifting deposit unit receive timeThe Cycle Length of clock signal, equals whole gate lines in described display floater need to be by gating successively time,The t of the Cycle Length of the clock signal that this shifting deposit unit receives doubly;
Wherein, the number that t equals the gate line in described display floater is divided by scanning described definite gridThe number of gate line when line in the described display floater of actual scanning.
For example, the gate line connecting when the pixel of determining in the region that needs to show in display floater is display surfaceWhen h article of gate line to the N-h article of gate line in plate, at h article of gate line to the N-h article grid of scanningWhen polar curve, if gate driver circuit forward scan, the so grid in the described display floater of actual scanningThe number of line is N-h bar, now t=N/ (N-h), Article 1 gate line to the N-h bar in display floaterThe Cycle Length T1=of the clock signal that the shifting deposit unit that each gate line in gate line connects receivesN*T2/ (N-h), T2 is whole gate lines in display floater while needing successively gating, each in display floaterThe Cycle Length of the clock signal that the shifting deposit unit that bar gate line connects receives; If grid drives electricityRoad reverse scan, the number of the gate line in the described display floater of actual scanning is N-h+1 bar so, thatT=N/ (N-h+1), T1=N*T2/ (N-h+1).
Preferably, for a gate line in described definite gate line, need at described definite gate lineWill be by gating successively time, the duration that this gate line is strobed, equals the whole grid in described display floaterWhen polar curve need to be by gating successively, the t of the duration that this gate line is strobed doubly.
For example, the gate line connecting when the pixel of determining in the region that needs to show in display floater is display surfaceWhen h article of gate line to the N-h article of gate line in plate, at h article of gate line to the N-h article grid of scanningWhen polar curve, if gate driver circuit forward scan, the so grid in the described display floater of actual scanningThe number of line is N-h bar, now t=N/ (N-h), Article 1 gate line to the N-h bar in display floaterThe duration Ton1=N*Ton2/ (N-h) that each gate line in gate line is strobed, Ton2 is in display floaterWhole gate lines while needing successively gating, each the duration that gate line is strobed in display floater; IfGate driver circuit reverse scan, the number of the gate line in the described display floater of actual scanning is soN-h+1 bar, t=N/ (N-h+1) so, Ton1=N*Ton2/ (N-h+1).
Like this, although only scan the part of grid pole line in display floater,, the time of each frame scan is allThe time of each frame scan is identical with need to scan in display floater whole gate lines time.
The driving method that subregion that the embodiment of the present invention provides shows, is applied to that the embodiment of the present invention providesGate driver circuit, as shown in Figure 4, comprising:
S401, determine the gate line that the pixel in the region that needs in display floater to show connects;
S402, determine described gate driver circuit forward scan, for the initial j in definite gate lineIn each shifting deposit unit in the described gate driver circuit that each gate line in bar gate line connectsA shifting deposit unit, control the forward of this shifting deposit unit and select signal end to receive initial trigger letterNumber (even this shifting deposit unit is f shifting deposit unit in gate driver circuit, and this moves soOriginal trigger signal and mod ((f-1)/j)+1 displacement that the forward of position deposit unit selects signal end to receiveThe original trigger signal phase that the first on-off circuit that the forward of deposit unit selects signal end to connect receivesWith); Described in connecting for each the gate line except initial j bar gate line in definite gate lineA shifting deposit unit in each shifting deposit unit in gate driver circuit, controls this shift LDThe forward selection signal end of unit receives j the shifting deposit unit output before of this shifting deposit unit(even this shifting deposit unit is f shifting deposit unit in gate driver circuit to signal, so shouldThe forward of shifting deposit unit selects signal end to receive the signal of f-j shifting deposit unit output); ForEach shift LD list in the described gate driver circuit that each gate line in definite gate line connectsA shifting deposit unit in unit, connects second at the reverse selection signal end of this shifting deposit unit and selectsWhen circuit, the reverse selection signal end of controlling this shifting deposit unit receives the after this shifting deposit unit(even this shifting deposit unit connects second and selects circuit and this to move for the signal of j shifting deposit unit outputPosition deposit unit is f shifting deposit unit in gate driver circuit, this shifting deposit unit soOppositely select signal end to receive the signal that f+j shifting deposit unit exported), at this shifting deposit unitWhile oppositely selecting signal end to connect second switch circuit, control the reverse selection signal end of this shifting deposit unitThe second switch closing of circuit connecting;
Taking the structure of the gate driver circuit shown in Fig. 2 a as example (j=1), need to show when determining in display floaterThe gate line that pixel in the region showing connects is h article of gate line to the N-h article grid in display floaterWhen line (h is less than N/2), if when the gate driver circuit forward scan shown in Fig. 2 a, h article of gate lineThe last item gate line to N-h article of gate line is N-h article of gate line, an initial gate lineBe h article of gate line; Therefore,, in the time carrying out S402, can control the displacement of h article of gate line connection and postThe forward of the SRh of deposit receipt unit selects signal end to receive original trigger signal STV, h+1 article gate line to theThe forward selection signal end of the shifting deposit unit that each gate line in N-h bar gate line connects receives this and movesThe signal of the previous shifting deposit unit output of position deposit unit, and at h article of gate line to the N-h articleIn the shifting deposit unit that each gate line in gate line connects, control it and oppositely select signal end to connect theThe reverse selection signal end of the shifting deposit unit of two selection circuit receives latter of this shifting deposit unitThe signal of shifting deposit unit output, and control it and oppositely select signal end to connect the displacement of second switch circuitThe second switch closing of circuit that the reverse selection signal end of deposit unit connects, makes this shift LD Dan YuanReverse selection signal end receive gating end signal;
Taking the structure of the gate driver circuit shown in Fig. 2 b as example (j=2), need when determining in display floaterThe gate line that pixel in the region showing connects is h article of gate line to the N-h article grid in display floaterWhen polar curve (h is less than N/2, and taking h as odd number, N is that odd number is example explanation), if the grid shown in Fig. 2 bWhen drive circuit forward scan, last j article of gate line in h article of gate line to the N-h article gate line isN-h article of gate line and N-h-1 article of gate line, initial j article gate line is h article of gate line andH+1 bar gate line; Therefore,, in the time carrying out S402, can control the shift LD that h article of gate line connectsThe forward of cell S Rh selects signal end to receive the first original trigger signal STV1, and h+1 article of gate line connectsThe forward of the shifting deposit unit SRh+1 connecing selects signal end to receive the second original trigger signal STV2, theThe forward choosing of the shifting deposit unit that each gate line in h+2 article of gate line to the N-h bar gate line connectsSelect the signal that signal end receives second shifting deposit unit output before this shifting deposit unit, and theIn the shifting deposit unit that each gate line in h article of gate line to the N-h bar gate line connects, control itThe reverse selection signal end of oppositely selecting signal end to connect the shifting deposit unit of the second selection circuit receives shouldThe signal of second shifting deposit unit output after shifting deposit unit, and control it and oppositely select letterNumber end connects the second switch that the reverse selection signal end of the shifting deposit unit of second switch circuit connectsClosing of circuit, (specifically connects the reverse selection signal end reception gating end signal of this shift LD Dan YuanReceiving which gating end signal, is in the gate driver circuit shown in Fig. 2 b by this shifting deposit unitWhich shifting deposit unit determines);
S403, determine described gate driver circuit reverse scan, for the initial j in definite gate lineIn each shifting deposit unit in the described gate driver circuit that each gate line in bar gate line connectsA shifting deposit unit, the reverse selection signal end of controlling this shifting deposit unit receives gating and finishes letterNumber (even this shifting deposit unit is f shifting deposit unit in gate driver circuit, and this moves soGating end signal and N-mod ((f-1)/j) individual displacement that the reverse selection signal end of position deposit unit receivesThe gating end signal phase that the second switch circuit that the reverse selection signal end of deposit unit connects receivesWith); Described in connecting for each the gate line except initial j bar gate line in definite gate lineA shifting deposit unit in each shifting deposit unit in gate driver circuit, controls this shift LDThe reverse selection signal end of unit receives j the shifting deposit unit output afterwards of this shifting deposit unit(even this shifting deposit unit is f shifting deposit unit in gate driver circuit to signal, so shouldThe reverse selection signal end of shifting deposit unit receives the signal of f+j shifting deposit unit output); ForEach shift LD list in the described gate driver circuit that each gate line in definite gate line connectsA shifting deposit unit in unit, controls the forward of this shifting deposit unit and selects signal end to receive this displacement(even this shifting deposit unit is grid to the signal of j shifting deposit unit output before deposit unitF shifting deposit unit in drive circuit, the forward of this shifting deposit unit is selected signal termination soReceive the signal of f-j shifting deposit unit output);
Taking the structure of the gate driver circuit shown in Fig. 1 a as example (j=1), need to show when determining in display floaterThe gate line that pixel in the region showing connects is h article of gate line to the N-h article grid in display floaterWhen line (h is less than N/2), if when the gate driver circuit reverse scan shown in Fig. 1 a, h article of gate lineThe last item gate line to N-h article of gate line is h article of gate line, and an initial gate line isN-h article of gate line; Therefore,, in the time carrying out S403, can control the displacement even of N-h article of gate line and postThe reverse selection signal end of the SRN-h of deposit receipt unit receives gating end signal CF, and N-h-1 article of gate line extremelyThe reverse selection signal end of the shifting deposit unit that each article of gate line in h article of gate line connects receives this and movesThe signal of the rear shifting deposit unit output of position deposit unit, and at h article of gate line to the N-h articleIn the shifting deposit unit that each gate line in gate line connects, control its forward and select signal end to connect theOne selects the forward of the shifting deposit unit of circuit to select signal end to receive the previous of this shifting deposit unitThe signal of shifting deposit unit output, and control its forward and select signal end to connect the displacement of the first on-off circuitThe first on-off circuit closure that the forward of deposit unit selects signal end to connect, makes this shift LD Dan YuanReverse selection signal end receive original trigger signal;
Taking the structure of the gate driver circuit shown in Fig. 2 b as example (j=2), need when determining in display floaterThe gate line that pixel in the region showing connects is h article of gate line to the N-h article grid in display floaterWhen polar curve (h is less than N/2, and taking h as odd number, N is that odd number is example explanation), if the grid shown in Fig. 2 bWhen drive circuit reverse scan, last j article of gate line in h article of gate line to the N-h article gate line isH article of gate line and h+1 article of gate line, initial j article gate line is N-h article of gate line andN-h-1 bar gate line; Therefore,, in the time carrying out S402, can control the displacement of N-h article of gate line connection and postThe reverse selection signal end of the SRh of deposit receipt unit receives the second gating end signal CF2, N-h-1 article of gate lineThe reverse selection signal end of the shifting deposit unit SRh+1 connecting receives the first gating end signal CF1, theThe reverse choosing of the shifting deposit unit that each gate line in h article of gate line to the N-h-2 bar gate line connectsSelect the signal that signal end receives second shifting deposit unit output after this shifting deposit unit, and theIn the shifting deposit unit that each gate line in h article of gate line to the N-h bar gate line connects, control itThe forward that forward selects signal end to connect the shifting deposit unit of the first selection circuit selects signal end to receive shouldThe signal of second shifting deposit unit output before shifting deposit unit, and control its forward and select letterNumber end connects the forward of the shifting deposit unit of the first on-off circuit and selects the first switch of connecting of signal endClosing of circuit, makes the forward of this shift LD Dan Yuan select signal end reception original trigger signal (specifically to connectReceiving which original trigger signal, is in the gate driver circuit shown in Fig. 2 b by this shifting deposit unitWhich shifting deposit unit determines);
S404, control described gate driver circuit and carry out present frame scanning, last in definite gate lineWhen each gate line gating in j bar gate line finishes, control each displacement in described gate driver circuitThe first control signal that the control signal termination of deposit unit is received is high level, until described grid drives electricityWhen road starts to carry out next frame scanning, control the control of each shifting deposit unit in described gate driver circuitThe first control signal that signal end processed receives is low level.
Wherein, S402 and S403 there is no temporal sequencing.
Preferably, a displacement in each shifting deposit unit connecting for described definite gate line is postedDeposit receipt unit, in the time that described definite gate line need to be by gating successively, this shifting deposit unit receive timeThe Cycle Length of clock signal, equals whole gate lines in described display floater need to be by gating successively time,The m of the Cycle Length of the clock signal that this shifting deposit unit receives doubly;
Wherein, m equals the number of the gate line in described display floater divided by the bar of described definite gate lineNumber.
For example, the gate line connecting when the pixel of determining in the region that needs to show in display floater is display surfaceWhen h article of gate line to the N-h article of gate line in plate, m=N/ (N-2h+1), the h in display floaterThe clock that the shifting deposit unit that each gate line in article gate line to the N-h bar gate line connects receivesThe Cycle Length T1=N*T2/ (N-2h+1) of signal, T2 is that the whole gate lines in display floater need successivelyWhen gating, the week of the clock signal that the shifting deposit unit that each gate line in display floater connects receivesPhase length.
Preferably, for a gate line in described definite gate line, need at described definite gate lineWill be by gating successively time, the duration that this gate line is strobed, equals the whole grid in described display floaterWhen polar curve need to be by gating successively, the m of the duration that this gate line is strobed doubly.
For example, the gate line connecting when the pixel of determining in the region that needs to show in display floater is display surfaceWhen h article of gate line to the N-h article of gate line in plate, m=N/ (N-2h+1), the h in display floaterThe duration Ton1=that each gate line in article gate line to the N-h bar gate line is strobedN*Ton2/ (N-2h+1), Ton2 is whole gate lines in display floater while needing successively gating, display surfaceEach the duration that gate line is strobed in plate.
Like this, although only scan the part of grid pole line in display floater,, the time of each frame scan is allThe time of each frame scan is identical with need to scan in display floater whole gate lines time. By above enforcementThe description of mode, those skilled in the art can be well understood to the embodiment of the present invention can pass through hardwareRealize, the mode that also can add necessary general hardware platform by software realizes. Based on such understanding,The technical scheme of the embodiment of the present invention can embody with the form of software product, and this software product can be depositedStorage, in a non-volatile memory medium (can be CD-ROM, USB flash disk, portable hard drive etc.), comprisesSome instructions in order to make a computer equipment (can be personal computer, server, or network is establishedStandby etc.) carry out the method described in each embodiment of the present invention.
It will be appreciated by those skilled in the art that accompanying drawing is the schematic diagram of a preferred embodiment, the mould in accompanying drawingPiece or flow process might not be that enforcement the present invention is necessary.
It will be appreciated by those skilled in the art that the module in the device in embodiment can describe according to embodimentBe distributed in the device of embodiment, also can carry out respective change and be positioned at and be different from of the present embodimentOr in multiple devices. The module of above-described embodiment can be merged into a module, also can further split intoMultiple submodules.
The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.
Obviously, those skilled in the art can carry out various changes and modification and not depart from this present inventionBright spirit and scope. Like this, if of the present invention these amendment and modification belong to the claims in the present invention andWithin the scope of its equivalent technologies, the present invention be also intended to comprise these change and modification interior.
Claims (7)
1. a gate driver circuit, is characterized in that, comprises N shifting deposit unit;
The forward selection signal end of p shifting deposit unit receives p-j shifting deposit unit outputSignal, p=j+1 ... .N, first shifting deposit unit is to each displacement in j shifting deposit unitThe forward of deposit unit is selected the signal end mutually different original trigger signal of received bit respectively;
The reverse selection signal end of r shifting deposit unit receives r+j shifting deposit unit outputSignal, r=1,2 ... N-j, N-j+1 shifting deposit unit is to each in N shifting deposit unitThe reverse selection signal end of the shifting deposit unit mutually different gating end signal of received bit respectively;
The clock signal terminal of k shifting deposit unit receives mod ((k-1)/(2*j))+1 clock signal,K=1,2 ..., N; J is positive integer;
The control signal termination of each shifting deposit unit is received the first control signal, each shifting deposit unitForward scan signal end receives the first level signal, and the reverse scan signal end of each shifting deposit unit receivesSecond electrical level signal, the low level signal termination of each shifting deposit unit is received low level signal;
When the first level signal is high level signal, second electrical level signal is low level signal; The first level letterWhile number being low level signal, second electrical level signal is high level signal;
In the time of described gate driver circuit forward scan, each shifting deposit unit, for believing in the first controlThe first control signal that number termination is received is that to select the signal that signal end receives be high electricity for low level and forwardAt ordinary times, the high level signal receiving with forward scan signal end is transistorized to driving grid line in selfGrid charges to the stable unlatching of this transistor; After the stable unlatching of this transistor, will pass through clock signalThe clock signal output that termination is received; The first control signal of receiving in the first control signal termination is low electricityFlat and while oppositely selecting signal that signal end receives to be high level, receive with reverse scan signal endLow level signal is discharged to this transistor to the transistorized grid of driving grid line in self and closes; WithAnd the first control signal of receiving in the first control signal termination is while being high level, the gate line that self is connectedLogical with low level signal termination;
In the time of described gate driver circuit reverse scan, each shifting deposit unit, for believing in the first controlThe first control signal that number termination is received is low level and oppositely to select the signal that signal end receives be high electricityAt ordinary times, the high level signal receiving with reverse scan signal end is transistorized to driving grid line in selfGrid charges to the stable unlatching of this transistor; After the stable unlatching of this transistor, will pass through clock signalThe clock signal output that termination is received; The first control signal of receiving in the first control signal termination is low electricityWhen signal flat and that forward selects signal end to receive is high level, receive with forward scan signal endLow level signal is discharged to this transistor to the transistorized grid of driving grid line in self and closes; WithAnd the first control signal of receiving in the first control signal termination is while being high level, the gate line that self is connectedLogical with low level signal termination;
Described circuit also comprises the first selection circuit, the second selection circuit, the first on-off circuit and second switchCircuit;
The forward of p shifting deposit unit selects signal end to select circuit to receive p-j by one firstThe signal of individual shifting deposit unit output, this first selects circuit also to receive that ((p-1)/j)+1 is moved with modThe identical signal of signal that the forward of position deposit unit selects signal end to receive;
This first selection circuit, selects signal end receiving for controlling the forward of p shifting deposit unitThe signal of p-j shifting deposit unit output, and receive and mod ((p-1)/j)+1 shifting deposit unitForward select to switch between signal that the signal that receives of signal end is identical;
First shifting deposit unit is to the forward of each shifting deposit unit in j shifting deposit unitSelect signal end to receive an original trigger signal by first on-off circuit respectively;
Each the first on-off circuit, selects signal for the forward of controlling the shifting deposit unit being connected with selfWhether end receives original trigger signal;
The reverse selection signal end of r shifting deposit unit selects circuit to receive r+j by one secondThe signal of individual shifting deposit unit output, this second selection circuit also receives ((r-1)/j) individual displacement with N-modThe identical signal of signal that the reverse selection signal end of deposit unit receives;
This second selection circuit, is receiving for the reverse selection signal end of controlling r shifting deposit unitThe signal of r+j shifting deposit unit output, and receive and N-mod ((r-1)/j) individual shifting deposit unitThe identical signal of the signal that receives of reverse selection signal end between switch;
N-j+1 shifting deposit unit is to each shifting deposit unit in N shifting deposit unitOppositely select signal end to receive a gating end signal by a second switch circuit respectively;
Each second switch circuit, for controlling the reverse selection signal of the shifting deposit unit being connected with selfWhether end receives gating end signal.
2. a display unit, is characterized in that, comprises gate driver circuit as claimed in claim 1.
3. the driving method that subregion shows, is applied to gate driver circuit claimed in claim 1,It is characterized in that, comprising:
Determine the gate line that the pixel in the region that needs to show in display floater connects;
Control described gate driver circuit and carry out present frame scanning, the last j bar grid in definite gate lineWhen each gate line gating in polar curve finishes, control each shift LD list in described gate driver circuitThe first control signal that the control signal termination of unit is received is high level, until described gate driver circuit startsWhile carrying out next frame scanning, control the control signal of each shifting deposit unit in described gate driver circuitThe first control signal that termination is received is low level;
A shifting deposit unit in each shifting deposit unit connecting for described definite gate line,In the time that described definite gate line need to be by gating successively, the clock signal that this shifting deposit unit receivesCycle Length, equals whole gate lines in described display floater need to be by gating successively time, and this displacement is postedThe t of the Cycle Length of the clock signal that deposit receipt unit receives doubly;
Wherein, the number that t equals the gate line in described display floater is divided by scanning described definite gridThe number of gate line when line in the described display floater of actual scanning.
4. method as claimed in claim 3, is characterized in that, in described definite gate line, a gate line, in the time that described definite gate line need to be by gating successively, this gate line be strobed timeLong, equal whole gate lines in described display floater need to be by gating successively time, this gate line is selectedThe t of logical duration doubly.
5. the driving method that subregion shows, is applied to gate driver circuit claimed in claim 1,It is characterized in that, comprising:
Determine the gate line that the pixel in the region that needs to show in display floater connects;
Determine described gate driver circuit forward scan, for the initial j bar grid in definite gate lineIn each shifting deposit unit in the described gate driver circuit that each gate line in line connects oneShifting deposit unit, controls the forward of this shifting deposit unit and selects signal end to receive original trigger signal; PinThe described grid that each gate line except initial j bar gate line in definite gate line connected drivesA shifting deposit unit in each shifting deposit unit in moving circuit, controls this shifting deposit unitForward selects signal end to receive the signal of this shifting deposit unit j shifting deposit unit output before;Each displacement in the described gate driver circuit connecting for each gate line in definite gate line is postedA shifting deposit unit in deposit receipt unit, connects second at the reverse selection signal end of this shifting deposit unitSelect when circuit, after the reverse selection signal end of controlling this shifting deposit unit receives this shifting deposit unitThe signal of j shifting deposit unit output, connect at the reverse selection signal end of this shifting deposit unitWhen second switch circuit, control the second switch circuit of the reverse selection signal end connection of this shifting deposit unitClosed;
Determine described gate driver circuit reverse scan, for the initial j bar grid in definite gate lineIn each shifting deposit unit in the described gate driver circuit that each gate line in line connects oneShifting deposit unit, the reverse selection signal end of controlling this shifting deposit unit receives gating end signal; PinThe described grid that each gate line except initial j bar gate line in definite gate line connected drivesA shifting deposit unit in each shifting deposit unit in moving circuit, controls this shifting deposit unitOppositely select signal end to receive the signal of this shifting deposit unit j shifting deposit unit output afterwards;Each displacement in the described gate driver circuit connecting for each gate line in definite gate line is postedA shifting deposit unit in deposit receipt unit, selects signal end to connect first at the forward of this shifting deposit unitSelect when circuit, the forward of controlling this shifting deposit unit is selected before signal end receives this shifting deposit unitThe signal of j shifting deposit unit output, select signal end to connect at the forward of this shifting deposit unitWhen the first on-off circuit, the forward of controlling this shifting deposit unit is selected the first on-off circuit of signal end connectionClosed;
Control described gate driver circuit and carry out present frame scanning, the last j bar grid in definite gate lineWhen each gate line gating in polar curve finishes, control each shift LD list in described gate driver circuitThe first control signal that the control signal termination of unit is received is high level, until described gate driver circuit startsWhile carrying out next frame scanning, control the control signal of each shifting deposit unit in described gate driver circuitThe first control signal that termination is received is low level.
6. method as claimed in claim 5, is characterized in that, connects for described definite gate lineEach shifting deposit unit in a shifting deposit unit, need to be by successively at described definite gate lineWhen gating, the Cycle Length of the clock signal that this shifting deposit unit receives, equals at described display floaterIn whole gate lines need to be by gating successively time, the cycle of the clock signal that this shifting deposit unit receivesThe m of length doubly;
Wherein, m equals the number of the gate line in described display floater divided by the bar of described definite gate lineNumber.
7. method as claimed in claim 6, is characterized in that, in described definite gate line, a gate line, in the time that described definite gate line need to be by gating successively, this gate line be strobed timeLong, equal whole gate lines in described display floater need to be by gating successively time, this gate line is selectedThe m of logical duration doubly.
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2014
- 2014-04-02 CN CN201410130951.0A patent/CN103943085B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101877202A (en) * | 2009-04-30 | 2010-11-03 | 三星电子株式会社 | Gate driver circuit and driving method thereof |
| CN103021309A (en) * | 2011-09-23 | 2013-04-03 | 海蒂斯技术有限公司 | Shift register and driving circuit using the same |
| CN103050077A (en) * | 2012-12-14 | 2013-04-17 | 京东方科技集团股份有限公司 | Grid electrode driving circuit, driving method and liquid crystal display device |
| CN103226979A (en) * | 2013-02-18 | 2013-07-31 | 合肥京东方光电科技有限公司 | Bidirectional shifting register unit, bidirectional shifting register and display device |
| CN103680439A (en) * | 2013-11-27 | 2014-03-26 | 合肥京东方光电科技有限公司 | Gate driving circuit and display device |
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| CN103943085A (en) | 2014-07-23 |
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